From: Matthew Brost <matthew.brost@intel.com> To: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: intel-gfx@lists.freedesktop.org, john.c.harrison@intel.com, dri-devel@lists.freedesktop.org Subject: Re: [PATCH 12/51] drm/i915/guc: Ensure request ordering via completion fences Date: Mon, 19 Jul 2021 19:48:17 -0700 [thread overview] Message-ID: <20210720024817.GA20354@sdutt-i7> (raw) In-Reply-To: <16b360b6-50fe-aaa9-4277-2ee3f3db8d0c@intel.com> On Mon, Jul 19, 2021 at 04:46:57PM -0700, Daniele Ceraolo Spurio wrote: > > > On 7/16/2021 1:16 PM, Matthew Brost wrote: > > If two requests are on the same ring, they are explicitly ordered by the > > HW. So, a submission fence is sufficient to ensure ordering when using > > the new GuC submission interface. Conversely, if two requests share a > > timeline and are on the same physical engine but different context this > > doesn't ensure ordering on the new GuC submission interface. So, a > > completion fence needs to be used to ensure ordering. > > > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > > --- > > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 - > > drivers/gpu/drm/i915/i915_request.c | 12 ++++++++++-- > > 2 files changed, 10 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > index 9dc1a256e185..4443cc6f5320 100644 > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > @@ -933,7 +933,6 @@ static void guc_context_sched_disable(struct intel_context *ce) > > * a request before we set the 'context_pending_disable' flag here. > > */ > > if (unlikely(atomic_add_unless(&ce->pin_count, -2, 2))) { > > - spin_unlock_irqrestore(&ce->guc_state.lock, flags); > > incorrect spinlock drop is still here. Everything else looks ok (my No it isn't not. See the return directly below the drop of the spin lock. Matt > suggestion to use an engine flag stands, but can be addressed as a follow > up). > Not sure I follow this one, but we can sync and address in a follow if needed. Matt > Daniele > > > return; > > } > > guc_id = prep_context_pending_disable(ce); > > diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c > > index b48c4905d3fc..2b2b63cba06c 100644 > > --- a/drivers/gpu/drm/i915/i915_request.c > > +++ b/drivers/gpu/drm/i915/i915_request.c > > @@ -432,6 +432,7 @@ void i915_request_retire_upto(struct i915_request *rq) > > do { > > tmp = list_first_entry(&tl->requests, typeof(*tmp), link); > > + GEM_BUG_ON(!i915_request_completed(tmp)); > > } while (i915_request_retire(tmp) && tmp != rq); > > } > > @@ -1380,6 +1381,9 @@ i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) > > return err; > > } > > +static int > > +i915_request_await_request(struct i915_request *to, struct i915_request *from); > > + > > int > > i915_request_await_execution(struct i915_request *rq, > > struct dma_fence *fence) > > @@ -1465,7 +1469,8 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from) > > return ret; > > } > > - if (is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask))) > > + if (!intel_engine_uses_guc(to->engine) && > > + is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask))) > > ret = await_request_submit(to, from); > > else > > ret = emit_semaphore_wait(to, from, I915_FENCE_GFP); > > @@ -1626,6 +1631,8 @@ __i915_request_add_to_timeline(struct i915_request *rq) > > prev = to_request(__i915_active_fence_set(&timeline->last_request, > > &rq->fence)); > > if (prev && !__i915_request_is_complete(prev)) { > > + bool uses_guc = intel_engine_uses_guc(rq->engine); > > + > > /* > > * The requests are supposed to be kept in order. However, > > * we need to be wary in case the timeline->last_request > > @@ -1636,7 +1643,8 @@ __i915_request_add_to_timeline(struct i915_request *rq) > > i915_seqno_passed(prev->fence.seqno, > > rq->fence.seqno)); > > - if (is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask)) > > + if ((!uses_guc && is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask)) || > > + (uses_guc && prev->context == rq->context)) > > i915_sw_fence_await_sw_fence(&rq->submit, > > &prev->submit, > > &rq->submitq); >
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 12/51] drm/i915/guc: Ensure request ordering via completion fences Date: Mon, 19 Jul 2021 19:48:17 -0700 [thread overview] Message-ID: <20210720024817.GA20354@sdutt-i7> (raw) In-Reply-To: <16b360b6-50fe-aaa9-4277-2ee3f3db8d0c@intel.com> On Mon, Jul 19, 2021 at 04:46:57PM -0700, Daniele Ceraolo Spurio wrote: > > > On 7/16/2021 1:16 PM, Matthew Brost wrote: > > If two requests are on the same ring, they are explicitly ordered by the > > HW. So, a submission fence is sufficient to ensure ordering when using > > the new GuC submission interface. Conversely, if two requests share a > > timeline and are on the same physical engine but different context this > > doesn't ensure ordering on the new GuC submission interface. So, a > > completion fence needs to be used to ensure ordering. > > > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > > --- > > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 - > > drivers/gpu/drm/i915/i915_request.c | 12 ++++++++++-- > > 2 files changed, 10 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > index 9dc1a256e185..4443cc6f5320 100644 > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > @@ -933,7 +933,6 @@ static void guc_context_sched_disable(struct intel_context *ce) > > * a request before we set the 'context_pending_disable' flag here. > > */ > > if (unlikely(atomic_add_unless(&ce->pin_count, -2, 2))) { > > - spin_unlock_irqrestore(&ce->guc_state.lock, flags); > > incorrect spinlock drop is still here. Everything else looks ok (my No it isn't not. See the return directly below the drop of the spin lock. Matt > suggestion to use an engine flag stands, but can be addressed as a follow > up). > Not sure I follow this one, but we can sync and address in a follow if needed. Matt > Daniele > > > return; > > } > > guc_id = prep_context_pending_disable(ce); > > diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c > > index b48c4905d3fc..2b2b63cba06c 100644 > > --- a/drivers/gpu/drm/i915/i915_request.c > > +++ b/drivers/gpu/drm/i915/i915_request.c > > @@ -432,6 +432,7 @@ void i915_request_retire_upto(struct i915_request *rq) > > do { > > tmp = list_first_entry(&tl->requests, typeof(*tmp), link); > > + GEM_BUG_ON(!i915_request_completed(tmp)); > > } while (i915_request_retire(tmp) && tmp != rq); > > } > > @@ -1380,6 +1381,9 @@ i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) > > return err; > > } > > +static int > > +i915_request_await_request(struct i915_request *to, struct i915_request *from); > > + > > int > > i915_request_await_execution(struct i915_request *rq, > > struct dma_fence *fence) > > @@ -1465,7 +1469,8 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from) > > return ret; > > } > > - if (is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask))) > > + if (!intel_engine_uses_guc(to->engine) && > > + is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask))) > > ret = await_request_submit(to, from); > > else > > ret = emit_semaphore_wait(to, from, I915_FENCE_GFP); > > @@ -1626,6 +1631,8 @@ __i915_request_add_to_timeline(struct i915_request *rq) > > prev = to_request(__i915_active_fence_set(&timeline->last_request, > > &rq->fence)); > > if (prev && !__i915_request_is_complete(prev)) { > > + bool uses_guc = intel_engine_uses_guc(rq->engine); > > + > > /* > > * The requests are supposed to be kept in order. However, > > * we need to be wary in case the timeline->last_request > > @@ -1636,7 +1643,8 @@ __i915_request_add_to_timeline(struct i915_request *rq) > > i915_seqno_passed(prev->fence.seqno, > > rq->fence.seqno)); > > - if (is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask)) > > + if ((!uses_guc && is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask)) || > > + (uses_guc && prev->context == rq->context)) > > i915_sw_fence_await_sw_fence(&rq->submit, > > &prev->submit, > > &rq->submitq); > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-20 2:59 UTC|newest] Thread overview: 221+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-16 20:16 [PATCH 00/51] GuC submission support Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 01/51] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 02/51] drm/i915/guc: Remove GuC stage descriptor, add LRC descriptor Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 03/51] drm/i915/guc: Add LRC descriptor context lookup array Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 04/51] drm/i915/guc: Implement GuC submission tasklet Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-19 23:01 ` John Harrison 2021-07-19 23:01 ` [Intel-gfx] " John Harrison 2021-07-19 22:55 ` Matthew Brost 2021-07-19 22:55 ` [Intel-gfx] " Matthew Brost 2021-07-20 0:26 ` John Harrison 2021-07-20 0:26 ` [Intel-gfx] " John Harrison 2021-07-16 20:16 ` [PATCH 05/51] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 06/51] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 0:23 ` John Harrison 2021-07-20 0:23 ` [Intel-gfx] " John Harrison 2021-07-20 2:45 ` Matthew Brost 2021-07-20 2:45 ` [Intel-gfx] " Matthew Brost 2021-07-20 0:51 ` Daniele Ceraolo Spurio 2021-07-20 0:51 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-20 4:04 ` Matthew Brost 2021-07-20 4:04 ` [Intel-gfx] " Matthew Brost 2021-07-21 23:51 ` Daniele Ceraolo Spurio 2021-07-21 23:51 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-22 7:57 ` Michal Wajdeczko 2021-07-22 7:57 ` Michal Wajdeczko 2021-07-22 15:48 ` Matthew Brost 2021-07-22 15:48 ` Matthew Brost 2021-07-16 20:16 ` [PATCH 07/51] drm/i915/guc: Insert fence on context when deregistering Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 08/51] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 09/51] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 10/51] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 11/51] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 12/51] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-19 23:46 ` Daniele Ceraolo Spurio 2021-07-19 23:46 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-20 2:48 ` Matthew Brost [this message] 2021-07-20 2:48 ` Matthew Brost 2021-07-20 2:50 ` Matthew Brost 2021-07-20 2:50 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 13/51] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 0:33 ` John Harrison 2021-07-20 0:33 ` [Intel-gfx] " John Harrison 2021-07-16 20:16 ` [PATCH 14/51] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 15/51] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 1:03 ` John Harrison 2021-07-20 1:03 ` [Intel-gfx] " John Harrison 2021-07-20 1:53 ` Matthew Brost 2021-07-20 1:53 ` [Intel-gfx] " Matthew Brost 2021-07-20 19:49 ` John Harrison 2021-07-20 19:49 ` [Intel-gfx] " John Harrison 2021-07-16 20:16 ` [PATCH 16/51] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 1:13 ` John Harrison 2021-07-20 1:13 ` [Intel-gfx] " John Harrison 2021-07-16 20:16 ` [PATCH 17/51] drm/i915/guc: Add several request trace points Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 1:27 ` John Harrison 2021-07-20 1:27 ` [Intel-gfx] " John Harrison 2021-07-20 2:10 ` Matthew Brost 2021-07-20 2:10 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 18/51] drm/i915: Add intel_context tracing Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 19/51] drm/i915/guc: GuC virtual engines Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-19 23:33 ` Daniele Ceraolo Spurio 2021-07-19 23:33 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-19 23:27 ` Matthew Brost 2021-07-19 23:27 ` [Intel-gfx] " Matthew Brost 2021-07-19 23:42 ` Daniele Ceraolo Spurio 2021-07-19 23:42 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-19 23:32 ` Matthew Brost 2021-07-19 23:32 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 20/51] drm/i915: Track 'serial' counts for " Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 1:28 ` John Harrison 2021-07-20 1:28 ` [Intel-gfx] " John Harrison 2021-07-20 1:54 ` Matthew Brost 2021-07-20 1:54 ` [Intel-gfx] " Matthew Brost 2021-07-20 16:47 ` Matthew Brost 2021-07-20 16:47 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 21/51] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 22/51] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 23/51] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 19:45 ` John Harrison 2021-07-20 19:45 ` [Intel-gfx] " John Harrison 2021-07-22 12:46 ` Tvrtko Ursulin 2021-07-22 12:46 ` Tvrtko Ursulin 2021-07-26 22:25 ` Matthew Brost 2021-07-26 22:25 ` Matthew Brost 2021-07-16 20:16 ` [PATCH 24/51] drm/i915: Add i915_sched_engine destroy vfunc Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 19:55 ` John Harrison 2021-07-20 19:55 ` [Intel-gfx] " John Harrison 2021-07-20 19:53 ` Matthew Brost 2021-07-20 19:53 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:16 ` [PATCH 25/51] drm/i915: Move active request tracking to a vfunc Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 20:05 ` John Harrison 2021-07-20 20:05 ` [Intel-gfx] " John Harrison 2021-07-16 20:16 ` [PATCH 26/51] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost 2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost 2021-07-20 20:19 ` John Harrison 2021-07-20 20:19 ` [Intel-gfx] " John Harrison 2021-07-20 20:59 ` Matthew Brost 2021-07-20 20:59 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 27/51] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 28/51] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 29/51] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 30/51] drm/i915/guc: Handle context reset notification Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-20 20:29 ` John Harrison 2021-07-20 20:29 ` [Intel-gfx] " John Harrison 2021-07-20 20:38 ` Matthew Brost 2021-07-20 20:38 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 31/51] drm/i915/guc: Handle engine reset failure notification Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 32/51] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 33/51] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-22 4:47 ` Matthew Brost 2021-07-22 4:47 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 34/51] drm/i915/guc: Don't complain about reset races Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 35/51] drm/i915/guc: Enable GuC engine reset Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 36/51] drm/i915/guc: Capture error state on context reset Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 37/51] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 38/51] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 39/51] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:04 ` Matthew Brost 2021-07-16 20:04 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 40/51] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 41/51] drm/i915/guc: Add golden context to GuC ADS Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-19 17:24 ` Matthew Brost 2021-07-19 17:24 ` Matthew Brost 2021-07-19 18:25 ` John Harrison 2021-07-19 18:25 ` John Harrison 2021-07-19 18:30 ` Matthew Brost 2021-07-19 18:30 ` Matthew Brost 2021-07-16 20:17 ` [PATCH 42/51] drm/i915/guc: Implement banned contexts for GuC submission Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-20 21:41 ` John Harrison 2021-07-20 21:41 ` [Intel-gfx] " John Harrison 2021-07-16 20:17 ` [PATCH 43/51] drm/i915/guc: Support request cancellation Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-22 19:56 ` Daniele Ceraolo Spurio 2021-07-22 19:56 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-22 20:13 ` Matthew Brost 2021-07-22 20:13 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 44/51] drm/i915/selftest: Better error reporting from hangcheck selftest Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:13 ` Matthew Brost 2021-07-16 20:13 ` Matthew Brost 2021-07-16 20:17 ` [PATCH 45/51] drm/i915/selftest: Fix workarounds selftest for GuC submission Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-20 17:14 ` Matthew Brost 2021-07-20 17:14 ` Matthew Brost 2021-07-16 20:17 ` [PATCH 46/51] drm/i915/selftest: Fix MOCS " Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 23:57 ` Matthew Brost 2021-07-16 23:57 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 47/51] drm/i915/selftest: Increase some timeouts in live_requests Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-20 21:46 ` John Harrison 2021-07-20 21:46 ` [Intel-gfx] " John Harrison 2021-07-22 8:13 ` Tvrtko Ursulin 2021-07-22 8:13 ` Tvrtko Ursulin 2021-07-16 20:17 ` [PATCH 48/51] drm/i915/selftest: Fix hangcheck self test for GuC submission Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 23:43 ` Matthew Brost 2021-07-16 23:43 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 49/51] drm/i915/selftest: Bump selftest timeouts for hangcheck Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-16 22:23 ` Matthew Brost 2021-07-16 22:23 ` [Intel-gfx] " Matthew Brost 2021-07-22 8:17 ` Tvrtko Ursulin 2021-07-22 8:17 ` Tvrtko Ursulin 2021-07-16 20:17 ` [PATCH 50/51] drm/i915/guc: Implement GuC priority management Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-22 20:26 ` Daniele Ceraolo Spurio 2021-07-22 20:26 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-22 21:38 ` Matthew Brost 2021-07-22 21:38 ` [Intel-gfx] " Matthew Brost 2021-07-22 21:50 ` Daniele Ceraolo Spurio 2021-07-22 21:50 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-22 21:55 ` Matthew Brost 2021-07-22 21:55 ` [Intel-gfx] " Matthew Brost 2021-07-16 20:17 ` [PATCH 51/51] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost 2021-07-16 20:17 ` [Intel-gfx] " Matthew Brost 2021-07-17 1:10 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev3) Patchwork 2021-07-19 9:06 ` [Intel-gfx] [PATCH 00/51] GuC submission support Tvrtko Ursulin 2021-07-19 9:06 ` Tvrtko Ursulin
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210720024817.GA20354@sdutt-i7 \ --to=matthew.brost@intel.com \ --cc=daniele.ceraolospurio@intel.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ --cc=john.c.harrison@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.