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From: Matthew Brost <matthew.brost@intel.com>
To: John Harrison <john.c.harrison@intel.com>
Cc: intel-gfx@lists.freedesktop.org, daniele.ceraolospurio@intel.com,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 20/51] drm/i915: Track 'serial' counts for virtual engines
Date: Tue, 20 Jul 2021 09:47:28 -0700	[thread overview]
Message-ID: <20210720164728.GA26575@sdutt-i7> (raw)
In-Reply-To: <20210720015400.GA13888@sdutt-i7>

On Mon, Jul 19, 2021 at 06:54:00PM -0700, Matthew Brost wrote:
> On Mon, Jul 19, 2021 at 06:28:47PM -0700, John Harrison wrote:
> > On 7/16/2021 13:16, Matthew Brost wrote:
> > > From: John Harrison <John.C.Harrison@Intel.com>
> > > 
> > > The serial number tracking of engines happens at the backend of
> > > request submission and was expecting to only be given physical
> > > engines. However, in GuC submission mode, the decomposition of virtual
> > > to physical engines does not happen in i915. Instead, requests are
> > > submitted to their virtual engine mask all the way through to the
> > > hardware (i.e. to GuC). This would mean that the heart beat code
> > > thinks the physical engines are idle due to the serial number not
> > > incrementing.
> > > 
> > > This patch updates the tracking to decompose virtual engines into
> > > their physical constituents and tracks the request against each. This
> > > is not entirely accurate as the GuC will only be issuing the request
> > > to one physical engine. However, it is the best that i915 can do given
> > > that it has no knowledge of the GuC's scheduling decisions.
> > > 
> > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > Still needs to pull in Tvrtko's updated subject and description.
> > 
> 
> Forgot this in the post, already have it fixed locally.
> 

In addition to updated comment, I took his advise to have a default
behavior without the vfunc to just increment engine->serial.

With those changes:
Reviewed-by: Matthew Brost <matthew.brost@intel.com> 

> Matt
> 
> > John.
> > 
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_engine_types.h     |  2 ++
> > >   .../gpu/drm/i915/gt/intel_execlists_submission.c |  6 ++++++
> > >   drivers/gpu/drm/i915/gt/intel_ring_submission.c  |  6 ++++++
> > >   drivers/gpu/drm/i915/gt/mock_engine.c            |  6 ++++++
> > >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c    | 16 ++++++++++++++++
> > >   drivers/gpu/drm/i915/i915_request.c              |  4 +++-
> > >   6 files changed, 39 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > index 1cb9c3b70b29..8ad304b2f2e4 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > @@ -388,6 +388,8 @@ struct intel_engine_cs {
> > >   	void		(*park)(struct intel_engine_cs *engine);
> > >   	void		(*unpark)(struct intel_engine_cs *engine);
> > > +	void		(*bump_serial)(struct intel_engine_cs *engine);
> > > +
> > >   	void		(*set_default_submission)(struct intel_engine_cs *engine);
> > >   	const struct intel_context_ops *cops;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > index 28492cdce706..920707e22eb0 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > @@ -3191,6 +3191,11 @@ static void execlists_release(struct intel_engine_cs *engine)
> > >   	lrc_fini_wa_ctx(engine);
> > >   }
> > > +static void execlist_bump_serial(struct intel_engine_cs *engine)
> > > +{
> > > +	engine->serial++;
> > > +}
> > > +
> > >   static void
> > >   logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> > >   {
> > > @@ -3200,6 +3205,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> > >   	engine->cops = &execlists_context_ops;
> > >   	engine->request_alloc = execlists_request_alloc;
> > > +	engine->bump_serial = execlist_bump_serial;
> > >   	engine->reset.prepare = execlists_reset_prepare;
> > >   	engine->reset.rewind = execlists_reset_rewind;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > index 5c4d204d07cc..61469c631057 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > @@ -1047,6 +1047,11 @@ static void setup_irq(struct intel_engine_cs *engine)
> > >   	}
> > >   }
> > > +static void ring_bump_serial(struct intel_engine_cs *engine)
> > > +{
> > > +	engine->serial++;
> > > +}
> > > +
> > >   static void setup_common(struct intel_engine_cs *engine)
> > >   {
> > >   	struct drm_i915_private *i915 = engine->i915;
> > > @@ -1066,6 +1071,7 @@ static void setup_common(struct intel_engine_cs *engine)
> > >   	engine->cops = &ring_context_ops;
> > >   	engine->request_alloc = ring_request_alloc;
> > > +	engine->bump_serial = ring_bump_serial;
> > >   	/*
> > >   	 * Using a global execution timeline; the previous final breadcrumb is
> > > diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
> > > index 68970398e4ef..9203c766db80 100644
> > > --- a/drivers/gpu/drm/i915/gt/mock_engine.c
> > > +++ b/drivers/gpu/drm/i915/gt/mock_engine.c
> > > @@ -292,6 +292,11 @@ static void mock_engine_release(struct intel_engine_cs *engine)
> > >   	intel_engine_fini_retire(engine);
> > >   }
> > > +static void mock_bump_serial(struct intel_engine_cs *engine)
> > > +{
> > > +	engine->serial++;
> > > +}
> > > +
> > >   struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
> > >   				    const char *name,
> > >   				    int id)
> > > @@ -318,6 +323,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
> > >   	engine->base.cops = &mock_context_ops;
> > >   	engine->base.request_alloc = mock_request_alloc;
> > > +	engine->base.bump_serial = mock_bump_serial;
> > >   	engine->base.emit_flush = mock_emit_flush;
> > >   	engine->base.emit_fini_breadcrumb = mock_emit_breadcrumb;
> > >   	engine->base.submit_request = mock_submit_request;
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > index 7b3e1c91e689..372e0dc7617a 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > @@ -1485,6 +1485,20 @@ static void guc_release(struct intel_engine_cs *engine)
> > >   	lrc_fini_wa_ctx(engine);
> > >   }
> > > +static void guc_bump_serial(struct intel_engine_cs *engine)
> > > +{
> > > +	engine->serial++;
> > > +}
> > > +
> > > +static void virtual_guc_bump_serial(struct intel_engine_cs *engine)
> > > +{
> > > +	struct intel_engine_cs *e;
> > > +	intel_engine_mask_t tmp, mask = engine->mask;
> > > +
> > > +	for_each_engine_masked(e, engine->gt, mask, tmp)
> > > +		e->serial++;
> > > +}
> > > +
> > >   static void guc_default_vfuncs(struct intel_engine_cs *engine)
> > >   {
> > >   	/* Default vfuncs which can be overridden by each engine. */
> > > @@ -1493,6 +1507,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> > >   	engine->cops = &guc_context_ops;
> > >   	engine->request_alloc = guc_request_alloc;
> > > +	engine->bump_serial = guc_bump_serial;
> > >   	engine->sched_engine->schedule = i915_schedule;
> > > @@ -1828,6 +1843,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count)
> > >   	ve->base.cops = &virtual_guc_context_ops;
> > >   	ve->base.request_alloc = guc_request_alloc;
> > > +	ve->base.bump_serial = virtual_guc_bump_serial;
> > >   	ve->base.submit_request = guc_submit_request;
> > > diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> > > index 01aa3d1ee2b1..30ecdc46a12f 100644
> > > --- a/drivers/gpu/drm/i915/i915_request.c
> > > +++ b/drivers/gpu/drm/i915/i915_request.c
> > > @@ -669,7 +669,9 @@ bool __i915_request_submit(struct i915_request *request)
> > >   				     request->ring->vaddr + request->postfix);
> > >   	trace_i915_request_execute(request);
> > > -	engine->serial++;
> > > +	if (engine->bump_serial)
> > > +		engine->bump_serial(engine);
> > > +
> > >   	result = true;
> > >   	GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
> > 

WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com>
To: John Harrison <john.c.harrison@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 20/51] drm/i915: Track 'serial' counts for virtual engines
Date: Tue, 20 Jul 2021 09:47:28 -0700	[thread overview]
Message-ID: <20210720164728.GA26575@sdutt-i7> (raw)
In-Reply-To: <20210720015400.GA13888@sdutt-i7>

On Mon, Jul 19, 2021 at 06:54:00PM -0700, Matthew Brost wrote:
> On Mon, Jul 19, 2021 at 06:28:47PM -0700, John Harrison wrote:
> > On 7/16/2021 13:16, Matthew Brost wrote:
> > > From: John Harrison <John.C.Harrison@Intel.com>
> > > 
> > > The serial number tracking of engines happens at the backend of
> > > request submission and was expecting to only be given physical
> > > engines. However, in GuC submission mode, the decomposition of virtual
> > > to physical engines does not happen in i915. Instead, requests are
> > > submitted to their virtual engine mask all the way through to the
> > > hardware (i.e. to GuC). This would mean that the heart beat code
> > > thinks the physical engines are idle due to the serial number not
> > > incrementing.
> > > 
> > > This patch updates the tracking to decompose virtual engines into
> > > their physical constituents and tracks the request against each. This
> > > is not entirely accurate as the GuC will only be issuing the request
> > > to one physical engine. However, it is the best that i915 can do given
> > > that it has no knowledge of the GuC's scheduling decisions.
> > > 
> > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > Still needs to pull in Tvrtko's updated subject and description.
> > 
> 
> Forgot this in the post, already have it fixed locally.
> 

In addition to updated comment, I took his advise to have a default
behavior without the vfunc to just increment engine->serial.

With those changes:
Reviewed-by: Matthew Brost <matthew.brost@intel.com> 

> Matt
> 
> > John.
> > 
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_engine_types.h     |  2 ++
> > >   .../gpu/drm/i915/gt/intel_execlists_submission.c |  6 ++++++
> > >   drivers/gpu/drm/i915/gt/intel_ring_submission.c  |  6 ++++++
> > >   drivers/gpu/drm/i915/gt/mock_engine.c            |  6 ++++++
> > >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c    | 16 ++++++++++++++++
> > >   drivers/gpu/drm/i915/i915_request.c              |  4 +++-
> > >   6 files changed, 39 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > index 1cb9c3b70b29..8ad304b2f2e4 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > @@ -388,6 +388,8 @@ struct intel_engine_cs {
> > >   	void		(*park)(struct intel_engine_cs *engine);
> > >   	void		(*unpark)(struct intel_engine_cs *engine);
> > > +	void		(*bump_serial)(struct intel_engine_cs *engine);
> > > +
> > >   	void		(*set_default_submission)(struct intel_engine_cs *engine);
> > >   	const struct intel_context_ops *cops;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > index 28492cdce706..920707e22eb0 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > @@ -3191,6 +3191,11 @@ static void execlists_release(struct intel_engine_cs *engine)
> > >   	lrc_fini_wa_ctx(engine);
> > >   }
> > > +static void execlist_bump_serial(struct intel_engine_cs *engine)
> > > +{
> > > +	engine->serial++;
> > > +}
> > > +
> > >   static void
> > >   logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> > >   {
> > > @@ -3200,6 +3205,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> > >   	engine->cops = &execlists_context_ops;
> > >   	engine->request_alloc = execlists_request_alloc;
> > > +	engine->bump_serial = execlist_bump_serial;
> > >   	engine->reset.prepare = execlists_reset_prepare;
> > >   	engine->reset.rewind = execlists_reset_rewind;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > index 5c4d204d07cc..61469c631057 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > @@ -1047,6 +1047,11 @@ static void setup_irq(struct intel_engine_cs *engine)
> > >   	}
> > >   }
> > > +static void ring_bump_serial(struct intel_engine_cs *engine)
> > > +{
> > > +	engine->serial++;
> > > +}
> > > +
> > >   static void setup_common(struct intel_engine_cs *engine)
> > >   {
> > >   	struct drm_i915_private *i915 = engine->i915;
> > > @@ -1066,6 +1071,7 @@ static void setup_common(struct intel_engine_cs *engine)
> > >   	engine->cops = &ring_context_ops;
> > >   	engine->request_alloc = ring_request_alloc;
> > > +	engine->bump_serial = ring_bump_serial;
> > >   	/*
> > >   	 * Using a global execution timeline; the previous final breadcrumb is
> > > diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
> > > index 68970398e4ef..9203c766db80 100644
> > > --- a/drivers/gpu/drm/i915/gt/mock_engine.c
> > > +++ b/drivers/gpu/drm/i915/gt/mock_engine.c
> > > @@ -292,6 +292,11 @@ static void mock_engine_release(struct intel_engine_cs *engine)
> > >   	intel_engine_fini_retire(engine);
> > >   }
> > > +static void mock_bump_serial(struct intel_engine_cs *engine)
> > > +{
> > > +	engine->serial++;
> > > +}
> > > +
> > >   struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
> > >   				    const char *name,
> > >   				    int id)
> > > @@ -318,6 +323,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
> > >   	engine->base.cops = &mock_context_ops;
> > >   	engine->base.request_alloc = mock_request_alloc;
> > > +	engine->base.bump_serial = mock_bump_serial;
> > >   	engine->base.emit_flush = mock_emit_flush;
> > >   	engine->base.emit_fini_breadcrumb = mock_emit_breadcrumb;
> > >   	engine->base.submit_request = mock_submit_request;
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > index 7b3e1c91e689..372e0dc7617a 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > @@ -1485,6 +1485,20 @@ static void guc_release(struct intel_engine_cs *engine)
> > >   	lrc_fini_wa_ctx(engine);
> > >   }
> > > +static void guc_bump_serial(struct intel_engine_cs *engine)
> > > +{
> > > +	engine->serial++;
> > > +}
> > > +
> > > +static void virtual_guc_bump_serial(struct intel_engine_cs *engine)
> > > +{
> > > +	struct intel_engine_cs *e;
> > > +	intel_engine_mask_t tmp, mask = engine->mask;
> > > +
> > > +	for_each_engine_masked(e, engine->gt, mask, tmp)
> > > +		e->serial++;
> > > +}
> > > +
> > >   static void guc_default_vfuncs(struct intel_engine_cs *engine)
> > >   {
> > >   	/* Default vfuncs which can be overridden by each engine. */
> > > @@ -1493,6 +1507,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> > >   	engine->cops = &guc_context_ops;
> > >   	engine->request_alloc = guc_request_alloc;
> > > +	engine->bump_serial = guc_bump_serial;
> > >   	engine->sched_engine->schedule = i915_schedule;
> > > @@ -1828,6 +1843,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count)
> > >   	ve->base.cops = &virtual_guc_context_ops;
> > >   	ve->base.request_alloc = guc_request_alloc;
> > > +	ve->base.bump_serial = virtual_guc_bump_serial;
> > >   	ve->base.submit_request = guc_submit_request;
> > > diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> > > index 01aa3d1ee2b1..30ecdc46a12f 100644
> > > --- a/drivers/gpu/drm/i915/i915_request.c
> > > +++ b/drivers/gpu/drm/i915/i915_request.c
> > > @@ -669,7 +669,9 @@ bool __i915_request_submit(struct i915_request *request)
> > >   				     request->ring->vaddr + request->postfix);
> > >   	trace_i915_request_execute(request);
> > > -	engine->serial++;
> > > +	if (engine->bump_serial)
> > > +		engine->bump_serial(engine);
> > > +
> > >   	result = true;
> > >   	GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
> > 
_______________________________________________
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  reply	other threads:[~2021-07-20 16:58 UTC|newest]

Thread overview: 221+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-16 20:16 [PATCH 00/51] GuC submission support Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 01/51] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 02/51] drm/i915/guc: Remove GuC stage descriptor, add LRC descriptor Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 03/51] drm/i915/guc: Add LRC descriptor context lookup array Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 04/51] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-19 23:01   ` John Harrison
2021-07-19 23:01     ` [Intel-gfx] " John Harrison
2021-07-19 22:55     ` Matthew Brost
2021-07-19 22:55       ` [Intel-gfx] " Matthew Brost
2021-07-20  0:26       ` John Harrison
2021-07-20  0:26         ` [Intel-gfx] " John Harrison
2021-07-16 20:16 ` [PATCH 05/51] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 06/51] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  0:23   ` John Harrison
2021-07-20  0:23     ` [Intel-gfx] " John Harrison
2021-07-20  2:45     ` Matthew Brost
2021-07-20  2:45       ` [Intel-gfx] " Matthew Brost
2021-07-20  0:51   ` Daniele Ceraolo Spurio
2021-07-20  0:51     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-20  4:04     ` Matthew Brost
2021-07-20  4:04       ` [Intel-gfx] " Matthew Brost
2021-07-21 23:51       ` Daniele Ceraolo Spurio
2021-07-21 23:51         ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-22  7:57         ` Michal Wajdeczko
2021-07-22  7:57           ` Michal Wajdeczko
2021-07-22 15:48           ` Matthew Brost
2021-07-22 15:48             ` Matthew Brost
2021-07-16 20:16 ` [PATCH 07/51] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 08/51] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 09/51] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 10/51] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 11/51] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 12/51] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-19 23:46   ` Daniele Ceraolo Spurio
2021-07-19 23:46     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-20  2:48     ` Matthew Brost
2021-07-20  2:48       ` [Intel-gfx] " Matthew Brost
2021-07-20  2:50       ` Matthew Brost
2021-07-20  2:50         ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 13/51] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  0:33   ` John Harrison
2021-07-20  0:33     ` [Intel-gfx] " John Harrison
2021-07-16 20:16 ` [PATCH 14/51] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 15/51] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  1:03   ` John Harrison
2021-07-20  1:03     ` [Intel-gfx] " John Harrison
2021-07-20  1:53     ` Matthew Brost
2021-07-20  1:53       ` [Intel-gfx] " Matthew Brost
2021-07-20 19:49       ` John Harrison
2021-07-20 19:49         ` [Intel-gfx] " John Harrison
2021-07-16 20:16 ` [PATCH 16/51] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  1:13   ` John Harrison
2021-07-20  1:13     ` [Intel-gfx] " John Harrison
2021-07-16 20:16 ` [PATCH 17/51] drm/i915/guc: Add several request trace points Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  1:27   ` John Harrison
2021-07-20  1:27     ` [Intel-gfx] " John Harrison
2021-07-20  2:10     ` Matthew Brost
2021-07-20  2:10       ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 18/51] drm/i915: Add intel_context tracing Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 19/51] drm/i915/guc: GuC virtual engines Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-19 23:33   ` Daniele Ceraolo Spurio
2021-07-19 23:33     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-19 23:27     ` Matthew Brost
2021-07-19 23:27       ` [Intel-gfx] " Matthew Brost
2021-07-19 23:42       ` Daniele Ceraolo Spurio
2021-07-19 23:42         ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-19 23:32         ` Matthew Brost
2021-07-19 23:32           ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 20/51] drm/i915: Track 'serial' counts for " Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  1:28   ` John Harrison
2021-07-20  1:28     ` [Intel-gfx] " John Harrison
2021-07-20  1:54     ` Matthew Brost
2021-07-20  1:54       ` [Intel-gfx] " Matthew Brost
2021-07-20 16:47       ` Matthew Brost [this message]
2021-07-20 16:47         ` Matthew Brost
2021-07-16 20:16 ` [PATCH 21/51] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 22/51] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 23/51] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20 19:45   ` John Harrison
2021-07-20 19:45     ` [Intel-gfx] " John Harrison
2021-07-22 12:46   ` Tvrtko Ursulin
2021-07-22 12:46     ` Tvrtko Ursulin
2021-07-26 22:25     ` Matthew Brost
2021-07-26 22:25       ` Matthew Brost
2021-07-16 20:16 ` [PATCH 24/51] drm/i915: Add i915_sched_engine destroy vfunc Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20 19:55   ` John Harrison
2021-07-20 19:55     ` [Intel-gfx] " John Harrison
2021-07-20 19:53     ` Matthew Brost
2021-07-20 19:53       ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 25/51] drm/i915: Move active request tracking to a vfunc Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20 20:05   ` John Harrison
2021-07-20 20:05     ` [Intel-gfx] " John Harrison
2021-07-16 20:16 ` [PATCH 26/51] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20 20:19   ` John Harrison
2021-07-20 20:19     ` [Intel-gfx] " John Harrison
2021-07-20 20:59     ` Matthew Brost
2021-07-20 20:59       ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 27/51] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 28/51] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 29/51] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 30/51] drm/i915/guc: Handle context reset notification Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-20 20:29   ` John Harrison
2021-07-20 20:29     ` [Intel-gfx] " John Harrison
2021-07-20 20:38     ` Matthew Brost
2021-07-20 20:38       ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 31/51] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 32/51] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 33/51] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-22  4:47   ` Matthew Brost
2021-07-22  4:47     ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 34/51] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 35/51] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 36/51] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 37/51] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 38/51] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 39/51] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:04   ` Matthew Brost
2021-07-16 20:04     ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 40/51] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 41/51] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-19 17:24   ` Matthew Brost
2021-07-19 17:24     ` Matthew Brost
2021-07-19 18:25     ` John Harrison
2021-07-19 18:25       ` John Harrison
2021-07-19 18:30       ` Matthew Brost
2021-07-19 18:30         ` Matthew Brost
2021-07-16 20:17 ` [PATCH 42/51] drm/i915/guc: Implement banned contexts for GuC submission Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-20 21:41   ` John Harrison
2021-07-20 21:41     ` [Intel-gfx] " John Harrison
2021-07-16 20:17 ` [PATCH 43/51] drm/i915/guc: Support request cancellation Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-22 19:56   ` Daniele Ceraolo Spurio
2021-07-22 19:56     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-22 20:13     ` Matthew Brost
2021-07-22 20:13       ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 44/51] drm/i915/selftest: Better error reporting from hangcheck selftest Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:13   ` Matthew Brost
2021-07-16 20:13     ` Matthew Brost
2021-07-16 20:17 ` [PATCH 45/51] drm/i915/selftest: Fix workarounds selftest for GuC submission Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-20 17:14   ` Matthew Brost
2021-07-20 17:14     ` Matthew Brost
2021-07-16 20:17 ` [PATCH 46/51] drm/i915/selftest: Fix MOCS " Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 23:57   ` Matthew Brost
2021-07-16 23:57     ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 47/51] drm/i915/selftest: Increase some timeouts in live_requests Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-20 21:46   ` John Harrison
2021-07-20 21:46     ` [Intel-gfx] " John Harrison
2021-07-22  8:13   ` Tvrtko Ursulin
2021-07-22  8:13     ` Tvrtko Ursulin
2021-07-16 20:17 ` [PATCH 48/51] drm/i915/selftest: Fix hangcheck self test for GuC submission Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 23:43   ` Matthew Brost
2021-07-16 23:43     ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 49/51] drm/i915/selftest: Bump selftest timeouts for hangcheck Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 22:23   ` Matthew Brost
2021-07-16 22:23     ` [Intel-gfx] " Matthew Brost
2021-07-22  8:17   ` Tvrtko Ursulin
2021-07-22  8:17     ` Tvrtko Ursulin
2021-07-16 20:17 ` [PATCH 50/51] drm/i915/guc: Implement GuC priority management Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-22 20:26   ` Daniele Ceraolo Spurio
2021-07-22 20:26     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-22 21:38     ` Matthew Brost
2021-07-22 21:38       ` [Intel-gfx] " Matthew Brost
2021-07-22 21:50       ` Daniele Ceraolo Spurio
2021-07-22 21:50         ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-22 21:55         ` Matthew Brost
2021-07-22 21:55           ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 51/51] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-17  1:10 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev3) Patchwork
2021-07-19  9:06 ` [Intel-gfx] [PATCH 00/51] GuC submission support Tvrtko Ursulin
2021-07-19  9:06   ` Tvrtko Ursulin

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