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From: John Harrison <john.c.harrison@intel.com>
To: Matthew Brost <matthew.brost@intel.com>,
	<intel-gfx@lists.freedesktop.org>,
	<dri-devel@lists.freedesktop.org>
Cc: daniele.ceraolospurio@intel.com
Subject: Re: [PATCH 25/51] drm/i915: Move active request tracking to a vfunc
Date: Tue, 20 Jul 2021 13:05:15 -0700	[thread overview]
Message-ID: <5f9f2578-5711-4c88-e7ae-77c843fdf483@intel.com> (raw)
In-Reply-To: <20210716201724.54804-26-matthew.brost@intel.com>

On 7/16/2021 13:16, Matthew Brost wrote:
> Move active request tracking to a backend vfunc rather than assuming all
> backends want to do this in the maner. In the case execlists /
maner -> manner.
In the case *of* execlists

With those fixed...
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>


> ring submission the tracking is on the physical engine while with GuC
> submission it is on the context.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_context.c       |  3 ++
>   drivers/gpu/drm/i915/gt/intel_context_types.h |  7 ++++
>   drivers/gpu/drm/i915/gt/intel_engine_types.h  |  6 +++
>   .../drm/i915/gt/intel_execlists_submission.c  | 40 ++++++++++++++++++
>   .../gpu/drm/i915/gt/intel_ring_submission.c   | 22 ++++++++++
>   drivers/gpu/drm/i915/gt/mock_engine.c         | 30 ++++++++++++++
>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 33 +++++++++++++++
>   drivers/gpu/drm/i915/i915_request.c           | 41 ++-----------------
>   drivers/gpu/drm/i915/i915_request.h           |  2 +
>   9 files changed, 147 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> index 251ff7eea22d..bfb05d8697d1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -393,6 +393,9 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)
>   	spin_lock_init(&ce->guc_state.lock);
>   	INIT_LIST_HEAD(&ce->guc_state.fences);
>   
> +	spin_lock_init(&ce->guc_active.lock);
> +	INIT_LIST_HEAD(&ce->guc_active.requests);
> +
>   	ce->guc_id = GUC_INVALID_LRC_ID;
>   	INIT_LIST_HEAD(&ce->guc_id_link);
>   
> diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
> index 542c98418771..035108c10b2c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> @@ -162,6 +162,13 @@ struct intel_context {
>   		struct list_head fences;
>   	} guc_state;
>   
> +	struct {
> +		/** lock: protects everything in guc_active */
> +		spinlock_t lock;
> +		/** requests: active requests on this context */
> +		struct list_head requests;
> +	} guc_active;
> +
>   	/* GuC scheduling state flags that do not require a lock. */
>   	atomic_t guc_sched_state_no_lock;
>   
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 03a81e8d87f4..950fc73ed6af 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -420,6 +420,12 @@ struct intel_engine_cs {
>   
>   	void		(*release)(struct intel_engine_cs *engine);
>   
> +	/*
> +	 * Add / remove request from engine active tracking
> +	 */
> +	void		(*add_active_request)(struct i915_request *rq);
> +	void		(*remove_active_request)(struct i915_request *rq);
> +
>   	struct intel_engine_execlists execlists;
>   
>   	/*
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index abe48421fd7a..f9b5f54a5abe 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3106,6 +3106,42 @@ static void execlists_park(struct intel_engine_cs *engine)
>   	cancel_timer(&engine->execlists.preempt);
>   }
>   
> +static void add_to_engine(struct i915_request *rq)
> +{
> +	lockdep_assert_held(&rq->engine->sched_engine->lock);
> +	list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);
> +}
> +
> +static void remove_from_engine(struct i915_request *rq)
> +{
> +	struct intel_engine_cs *engine, *locked;
> +
> +	/*
> +	 * Virtual engines complicate acquiring the engine timeline lock,
> +	 * as their rq->engine pointer is not stable until under that
> +	 * engine lock. The simple ploy we use is to take the lock then
> +	 * check that the rq still belongs to the newly locked engine.
> +	 */
> +	locked = READ_ONCE(rq->engine);
> +	spin_lock_irq(&locked->sched_engine->lock);
> +	while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
> +		spin_unlock(&locked->sched_engine->lock);
> +		spin_lock(&engine->sched_engine->lock);
> +		locked = engine;
> +	}
> +	list_del_init(&rq->sched.link);
> +
> +	clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
> +	clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
> +
> +	/* Prevent further __await_execution() registering a cb, then flush */
> +	set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
> +
> +	spin_unlock_irq(&locked->sched_engine->lock);
> +
> +	i915_request_notify_execute_cb_imm(rq);
> +}
> +
>   static bool can_preempt(struct intel_engine_cs *engine)
>   {
>   	if (GRAPHICS_VER(engine->i915) > 8)
> @@ -3206,6 +3242,8 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>   	engine->cops = &execlists_context_ops;
>   	engine->request_alloc = execlists_request_alloc;
>   	engine->bump_serial = execlist_bump_serial;
> +	engine->add_active_request = add_to_engine;
> +	engine->remove_active_request = remove_from_engine;
>   
>   	engine->reset.prepare = execlists_reset_prepare;
>   	engine->reset.rewind = execlists_reset_rewind;
> @@ -3797,6 +3835,8 @@ execlists_create_virtual(struct intel_engine_cs **siblings, unsigned int count)
>   			 "v%dx%d", ve->base.class, count);
>   		ve->base.context_size = sibling->context_size;
>   
> +		ve->base.add_active_request = sibling->add_active_request;
> +		ve->base.remove_active_request = sibling->remove_active_request;
>   		ve->base.emit_bb_start = sibling->emit_bb_start;
>   		ve->base.emit_flush = sibling->emit_flush;
>   		ve->base.emit_init_breadcrumb = sibling->emit_init_breadcrumb;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 61469c631057..3b1471c50d40 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -1052,6 +1052,25 @@ static void ring_bump_serial(struct intel_engine_cs *engine)
>   	engine->serial++;
>   }
>   
> +static void add_to_engine(struct i915_request *rq)
> +{
> +	lockdep_assert_held(&rq->engine->sched_engine->lock);
> +	list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);
> +}
> +
> +static void remove_from_engine(struct i915_request *rq)
> +{
> +	spin_lock_irq(&rq->engine->sched_engine->lock);
> +	list_del_init(&rq->sched.link);
> +
> +	/* Prevent further __await_execution() registering a cb, then flush */
> +	set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
> +
> +	spin_unlock_irq(&rq->engine->sched_engine->lock);
> +
> +	i915_request_notify_execute_cb_imm(rq);
> +}
> +
>   static void setup_common(struct intel_engine_cs *engine)
>   {
>   	struct drm_i915_private *i915 = engine->i915;
> @@ -1069,6 +1088,9 @@ static void setup_common(struct intel_engine_cs *engine)
>   	engine->reset.cancel = reset_cancel;
>   	engine->reset.finish = reset_finish;
>   
> +	engine->add_active_request = add_to_engine;
> +	engine->remove_active_request = remove_from_engine;
> +
>   	engine->cops = &ring_context_ops;
>   	engine->request_alloc = ring_request_alloc;
>   	engine->bump_serial = ring_bump_serial;
> diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
> index fc5a65ab1937..5f86ff79c98c 100644
> --- a/drivers/gpu/drm/i915/gt/mock_engine.c
> +++ b/drivers/gpu/drm/i915/gt/mock_engine.c
> @@ -235,6 +235,34 @@ static void mock_submit_request(struct i915_request *request)
>   	spin_unlock_irqrestore(&engine->hw_lock, flags);
>   }
>   
> +static void mock_add_to_engine(struct i915_request *rq)
> +{
> +	lockdep_assert_held(&rq->engine->sched_engine->lock);
> +	list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);
> +}
> +
> +static void mock_remove_from_engine(struct i915_request *rq)
> +{
> +	struct intel_engine_cs *engine, *locked;
> +
> +	/*
> +	 * Virtual engines complicate acquiring the engine timeline lock,
> +	 * as their rq->engine pointer is not stable until under that
> +	 * engine lock. The simple ploy we use is to take the lock then
> +	 * check that the rq still belongs to the newly locked engine.
> +	 */
> +
> +	locked = READ_ONCE(rq->engine);
> +	spin_lock_irq(&locked->sched_engine->lock);
> +	while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
> +		spin_unlock(&locked->sched_engine->lock);
> +		spin_lock(&engine->sched_engine->lock);
> +		locked = engine;
> +	}
> +	list_del_init(&rq->sched.link);
> +	spin_unlock_irq(&locked->sched_engine->lock);
> +}
> +
>   static void mock_reset_prepare(struct intel_engine_cs *engine)
>   {
>   }
> @@ -327,6 +355,8 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
>   	engine->base.emit_flush = mock_emit_flush;
>   	engine->base.emit_fini_breadcrumb = mock_emit_breadcrumb;
>   	engine->base.submit_request = mock_submit_request;
> +	engine->base.add_active_request = mock_add_to_engine;
> +	engine->base.remove_active_request = mock_remove_from_engine;
>   
>   	engine->base.reset.prepare = mock_reset_prepare;
>   	engine->base.reset.rewind = mock_reset_rewind;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 9f28899ff17f..f8a6077fa3f9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1147,6 +1147,33 @@ static int guc_context_alloc(struct intel_context *ce)
>   	return lrc_alloc(ce, ce->engine);
>   }
>   
> +static void add_to_context(struct i915_request *rq)
> +{
> +	struct intel_context *ce = rq->context;
> +
> +	spin_lock(&ce->guc_active.lock);
> +	list_move_tail(&rq->sched.link, &ce->guc_active.requests);
> +	spin_unlock(&ce->guc_active.lock);
> +}
> +
> +static void remove_from_context(struct i915_request *rq)
> +{
> +	struct intel_context *ce = rq->context;
> +
> +	spin_lock_irq(&ce->guc_active.lock);
> +
> +	list_del_init(&rq->sched.link);
> +	clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
> +
> +	/* Prevent further __await_execution() registering a cb, then flush */
> +	set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
> +
> +	spin_unlock_irq(&ce->guc_active.lock);
> +
> +	atomic_dec(&ce->guc_id_ref);
> +	i915_request_notify_execute_cb_imm(rq);
> +}
> +
>   static const struct intel_context_ops guc_context_ops = {
>   	.alloc = guc_context_alloc,
>   
> @@ -1567,6 +1594,8 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>   	engine->cops = &guc_context_ops;
>   	engine->request_alloc = guc_request_alloc;
>   	engine->bump_serial = guc_bump_serial;
> +	engine->add_active_request = add_to_context;
> +	engine->remove_active_request = remove_from_context;
>   
>   	engine->sched_engine->schedule = i915_schedule;
>   
> @@ -1931,6 +1960,10 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count)
>   				 "v%dx%d", ve->base.class, count);
>   			ve->base.context_size = sibling->context_size;
>   
> +			ve->base.add_active_request =
> +				sibling->add_active_request;
> +			ve->base.remove_active_request =
> +				sibling->remove_active_request;
>   			ve->base.emit_bb_start = sibling->emit_bb_start;
>   			ve->base.emit_flush = sibling->emit_flush;
>   			ve->base.emit_init_breadcrumb =
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index b3c792d55321..4eba848b20e3 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -182,7 +182,7 @@ static bool irq_work_imm(struct irq_work *wrk)
>   	return false;
>   }
>   
> -static void __notify_execute_cb_imm(struct i915_request *rq)
> +void i915_request_notify_execute_cb_imm(struct i915_request *rq)
>   {
>   	__notify_execute_cb(rq, irq_work_imm);
>   }
> @@ -256,37 +256,6 @@ i915_request_active_engine(struct i915_request *rq,
>   	return ret;
>   }
>   
> -
> -static void remove_from_engine(struct i915_request *rq)
> -{
> -	struct intel_engine_cs *engine, *locked;
> -
> -	/*
> -	 * Virtual engines complicate acquiring the engine timeline lock,
> -	 * as their rq->engine pointer is not stable until under that
> -	 * engine lock. The simple ploy we use is to take the lock then
> -	 * check that the rq still belongs to the newly locked engine.
> -	 */
> -	locked = READ_ONCE(rq->engine);
> -	spin_lock_irq(&locked->sched_engine->lock);
> -	while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
> -		spin_unlock(&locked->sched_engine->lock);
> -		spin_lock(&engine->sched_engine->lock);
> -		locked = engine;
> -	}
> -	list_del_init(&rq->sched.link);
> -
> -	clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
> -	clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
> -
> -	/* Prevent further __await_execution() registering a cb, then flush */
> -	set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
> -
> -	spin_unlock_irq(&locked->sched_engine->lock);
> -
> -	__notify_execute_cb_imm(rq);
> -}
> -
>   static void __rq_init_watchdog(struct i915_request *rq)
>   {
>   	rq->watchdog.timer.function = NULL;
> @@ -383,9 +352,7 @@ bool i915_request_retire(struct i915_request *rq)
>   	 * after removing the breadcrumb and signaling it, so that we do not
>   	 * inadvertently attach the breadcrumb to a completed request.
>   	 */
> -	if (!list_empty(&rq->sched.link))
> -		remove_from_engine(rq);
> -	atomic_dec(&rq->context->guc_id_ref);
> +	rq->engine->remove_active_request(rq);
>   	GEM_BUG_ON(!llist_empty(&rq->execute_cb));
>   
>   	__list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */
> @@ -516,7 +483,7 @@ __await_execution(struct i915_request *rq,
>   	if (llist_add(&cb->work.node.llist, &signal->execute_cb)) {
>   		if (i915_request_is_active(signal) ||
>   		    __request_in_flight(signal))
> -			__notify_execute_cb_imm(signal);
> +			i915_request_notify_execute_cb_imm(signal);
>   	}
>   
>   	return 0;
> @@ -653,7 +620,7 @@ bool __i915_request_submit(struct i915_request *request)
>   	result = true;
>   
>   	GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
> -	list_move_tail(&request->sched.link, &engine->sched_engine->requests);
> +	engine->add_active_request(request);
>   active:
>   	clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
>   	set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
> diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
> index 717e5b292046..128030f43bbf 100644
> --- a/drivers/gpu/drm/i915/i915_request.h
> +++ b/drivers/gpu/drm/i915/i915_request.h
> @@ -647,4 +647,6 @@ bool
>   i915_request_active_engine(struct i915_request *rq,
>   			   struct intel_engine_cs **active);
>   
> +void i915_request_notify_execute_cb_imm(struct i915_request *rq);
> +
>   #endif /* I915_REQUEST_H */


WARNING: multiple messages have this Message-ID (diff)
From: John Harrison <john.c.harrison@intel.com>
To: Matthew Brost <matthew.brost@intel.com>,
	<intel-gfx@lists.freedesktop.org>,
	<dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 25/51] drm/i915: Move active request tracking to a vfunc
Date: Tue, 20 Jul 2021 13:05:15 -0700	[thread overview]
Message-ID: <5f9f2578-5711-4c88-e7ae-77c843fdf483@intel.com> (raw)
In-Reply-To: <20210716201724.54804-26-matthew.brost@intel.com>

On 7/16/2021 13:16, Matthew Brost wrote:
> Move active request tracking to a backend vfunc rather than assuming all
> backends want to do this in the maner. In the case execlists /
maner -> manner.
In the case *of* execlists

With those fixed...
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>


> ring submission the tracking is on the physical engine while with GuC
> submission it is on the context.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_context.c       |  3 ++
>   drivers/gpu/drm/i915/gt/intel_context_types.h |  7 ++++
>   drivers/gpu/drm/i915/gt/intel_engine_types.h  |  6 +++
>   .../drm/i915/gt/intel_execlists_submission.c  | 40 ++++++++++++++++++
>   .../gpu/drm/i915/gt/intel_ring_submission.c   | 22 ++++++++++
>   drivers/gpu/drm/i915/gt/mock_engine.c         | 30 ++++++++++++++
>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 33 +++++++++++++++
>   drivers/gpu/drm/i915/i915_request.c           | 41 ++-----------------
>   drivers/gpu/drm/i915/i915_request.h           |  2 +
>   9 files changed, 147 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> index 251ff7eea22d..bfb05d8697d1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -393,6 +393,9 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)
>   	spin_lock_init(&ce->guc_state.lock);
>   	INIT_LIST_HEAD(&ce->guc_state.fences);
>   
> +	spin_lock_init(&ce->guc_active.lock);
> +	INIT_LIST_HEAD(&ce->guc_active.requests);
> +
>   	ce->guc_id = GUC_INVALID_LRC_ID;
>   	INIT_LIST_HEAD(&ce->guc_id_link);
>   
> diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
> index 542c98418771..035108c10b2c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> @@ -162,6 +162,13 @@ struct intel_context {
>   		struct list_head fences;
>   	} guc_state;
>   
> +	struct {
> +		/** lock: protects everything in guc_active */
> +		spinlock_t lock;
> +		/** requests: active requests on this context */
> +		struct list_head requests;
> +	} guc_active;
> +
>   	/* GuC scheduling state flags that do not require a lock. */
>   	atomic_t guc_sched_state_no_lock;
>   
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 03a81e8d87f4..950fc73ed6af 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -420,6 +420,12 @@ struct intel_engine_cs {
>   
>   	void		(*release)(struct intel_engine_cs *engine);
>   
> +	/*
> +	 * Add / remove request from engine active tracking
> +	 */
> +	void		(*add_active_request)(struct i915_request *rq);
> +	void		(*remove_active_request)(struct i915_request *rq);
> +
>   	struct intel_engine_execlists execlists;
>   
>   	/*
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index abe48421fd7a..f9b5f54a5abe 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3106,6 +3106,42 @@ static void execlists_park(struct intel_engine_cs *engine)
>   	cancel_timer(&engine->execlists.preempt);
>   }
>   
> +static void add_to_engine(struct i915_request *rq)
> +{
> +	lockdep_assert_held(&rq->engine->sched_engine->lock);
> +	list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);
> +}
> +
> +static void remove_from_engine(struct i915_request *rq)
> +{
> +	struct intel_engine_cs *engine, *locked;
> +
> +	/*
> +	 * Virtual engines complicate acquiring the engine timeline lock,
> +	 * as their rq->engine pointer is not stable until under that
> +	 * engine lock. The simple ploy we use is to take the lock then
> +	 * check that the rq still belongs to the newly locked engine.
> +	 */
> +	locked = READ_ONCE(rq->engine);
> +	spin_lock_irq(&locked->sched_engine->lock);
> +	while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
> +		spin_unlock(&locked->sched_engine->lock);
> +		spin_lock(&engine->sched_engine->lock);
> +		locked = engine;
> +	}
> +	list_del_init(&rq->sched.link);
> +
> +	clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
> +	clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
> +
> +	/* Prevent further __await_execution() registering a cb, then flush */
> +	set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
> +
> +	spin_unlock_irq(&locked->sched_engine->lock);
> +
> +	i915_request_notify_execute_cb_imm(rq);
> +}
> +
>   static bool can_preempt(struct intel_engine_cs *engine)
>   {
>   	if (GRAPHICS_VER(engine->i915) > 8)
> @@ -3206,6 +3242,8 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>   	engine->cops = &execlists_context_ops;
>   	engine->request_alloc = execlists_request_alloc;
>   	engine->bump_serial = execlist_bump_serial;
> +	engine->add_active_request = add_to_engine;
> +	engine->remove_active_request = remove_from_engine;
>   
>   	engine->reset.prepare = execlists_reset_prepare;
>   	engine->reset.rewind = execlists_reset_rewind;
> @@ -3797,6 +3835,8 @@ execlists_create_virtual(struct intel_engine_cs **siblings, unsigned int count)
>   			 "v%dx%d", ve->base.class, count);
>   		ve->base.context_size = sibling->context_size;
>   
> +		ve->base.add_active_request = sibling->add_active_request;
> +		ve->base.remove_active_request = sibling->remove_active_request;
>   		ve->base.emit_bb_start = sibling->emit_bb_start;
>   		ve->base.emit_flush = sibling->emit_flush;
>   		ve->base.emit_init_breadcrumb = sibling->emit_init_breadcrumb;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 61469c631057..3b1471c50d40 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -1052,6 +1052,25 @@ static void ring_bump_serial(struct intel_engine_cs *engine)
>   	engine->serial++;
>   }
>   
> +static void add_to_engine(struct i915_request *rq)
> +{
> +	lockdep_assert_held(&rq->engine->sched_engine->lock);
> +	list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);
> +}
> +
> +static void remove_from_engine(struct i915_request *rq)
> +{
> +	spin_lock_irq(&rq->engine->sched_engine->lock);
> +	list_del_init(&rq->sched.link);
> +
> +	/* Prevent further __await_execution() registering a cb, then flush */
> +	set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
> +
> +	spin_unlock_irq(&rq->engine->sched_engine->lock);
> +
> +	i915_request_notify_execute_cb_imm(rq);
> +}
> +
>   static void setup_common(struct intel_engine_cs *engine)
>   {
>   	struct drm_i915_private *i915 = engine->i915;
> @@ -1069,6 +1088,9 @@ static void setup_common(struct intel_engine_cs *engine)
>   	engine->reset.cancel = reset_cancel;
>   	engine->reset.finish = reset_finish;
>   
> +	engine->add_active_request = add_to_engine;
> +	engine->remove_active_request = remove_from_engine;
> +
>   	engine->cops = &ring_context_ops;
>   	engine->request_alloc = ring_request_alloc;
>   	engine->bump_serial = ring_bump_serial;
> diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
> index fc5a65ab1937..5f86ff79c98c 100644
> --- a/drivers/gpu/drm/i915/gt/mock_engine.c
> +++ b/drivers/gpu/drm/i915/gt/mock_engine.c
> @@ -235,6 +235,34 @@ static void mock_submit_request(struct i915_request *request)
>   	spin_unlock_irqrestore(&engine->hw_lock, flags);
>   }
>   
> +static void mock_add_to_engine(struct i915_request *rq)
> +{
> +	lockdep_assert_held(&rq->engine->sched_engine->lock);
> +	list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);
> +}
> +
> +static void mock_remove_from_engine(struct i915_request *rq)
> +{
> +	struct intel_engine_cs *engine, *locked;
> +
> +	/*
> +	 * Virtual engines complicate acquiring the engine timeline lock,
> +	 * as their rq->engine pointer is not stable until under that
> +	 * engine lock. The simple ploy we use is to take the lock then
> +	 * check that the rq still belongs to the newly locked engine.
> +	 */
> +
> +	locked = READ_ONCE(rq->engine);
> +	spin_lock_irq(&locked->sched_engine->lock);
> +	while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
> +		spin_unlock(&locked->sched_engine->lock);
> +		spin_lock(&engine->sched_engine->lock);
> +		locked = engine;
> +	}
> +	list_del_init(&rq->sched.link);
> +	spin_unlock_irq(&locked->sched_engine->lock);
> +}
> +
>   static void mock_reset_prepare(struct intel_engine_cs *engine)
>   {
>   }
> @@ -327,6 +355,8 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
>   	engine->base.emit_flush = mock_emit_flush;
>   	engine->base.emit_fini_breadcrumb = mock_emit_breadcrumb;
>   	engine->base.submit_request = mock_submit_request;
> +	engine->base.add_active_request = mock_add_to_engine;
> +	engine->base.remove_active_request = mock_remove_from_engine;
>   
>   	engine->base.reset.prepare = mock_reset_prepare;
>   	engine->base.reset.rewind = mock_reset_rewind;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 9f28899ff17f..f8a6077fa3f9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1147,6 +1147,33 @@ static int guc_context_alloc(struct intel_context *ce)
>   	return lrc_alloc(ce, ce->engine);
>   }
>   
> +static void add_to_context(struct i915_request *rq)
> +{
> +	struct intel_context *ce = rq->context;
> +
> +	spin_lock(&ce->guc_active.lock);
> +	list_move_tail(&rq->sched.link, &ce->guc_active.requests);
> +	spin_unlock(&ce->guc_active.lock);
> +}
> +
> +static void remove_from_context(struct i915_request *rq)
> +{
> +	struct intel_context *ce = rq->context;
> +
> +	spin_lock_irq(&ce->guc_active.lock);
> +
> +	list_del_init(&rq->sched.link);
> +	clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
> +
> +	/* Prevent further __await_execution() registering a cb, then flush */
> +	set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
> +
> +	spin_unlock_irq(&ce->guc_active.lock);
> +
> +	atomic_dec(&ce->guc_id_ref);
> +	i915_request_notify_execute_cb_imm(rq);
> +}
> +
>   static const struct intel_context_ops guc_context_ops = {
>   	.alloc = guc_context_alloc,
>   
> @@ -1567,6 +1594,8 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>   	engine->cops = &guc_context_ops;
>   	engine->request_alloc = guc_request_alloc;
>   	engine->bump_serial = guc_bump_serial;
> +	engine->add_active_request = add_to_context;
> +	engine->remove_active_request = remove_from_context;
>   
>   	engine->sched_engine->schedule = i915_schedule;
>   
> @@ -1931,6 +1960,10 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count)
>   				 "v%dx%d", ve->base.class, count);
>   			ve->base.context_size = sibling->context_size;
>   
> +			ve->base.add_active_request =
> +				sibling->add_active_request;
> +			ve->base.remove_active_request =
> +				sibling->remove_active_request;
>   			ve->base.emit_bb_start = sibling->emit_bb_start;
>   			ve->base.emit_flush = sibling->emit_flush;
>   			ve->base.emit_init_breadcrumb =
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index b3c792d55321..4eba848b20e3 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -182,7 +182,7 @@ static bool irq_work_imm(struct irq_work *wrk)
>   	return false;
>   }
>   
> -static void __notify_execute_cb_imm(struct i915_request *rq)
> +void i915_request_notify_execute_cb_imm(struct i915_request *rq)
>   {
>   	__notify_execute_cb(rq, irq_work_imm);
>   }
> @@ -256,37 +256,6 @@ i915_request_active_engine(struct i915_request *rq,
>   	return ret;
>   }
>   
> -
> -static void remove_from_engine(struct i915_request *rq)
> -{
> -	struct intel_engine_cs *engine, *locked;
> -
> -	/*
> -	 * Virtual engines complicate acquiring the engine timeline lock,
> -	 * as their rq->engine pointer is not stable until under that
> -	 * engine lock. The simple ploy we use is to take the lock then
> -	 * check that the rq still belongs to the newly locked engine.
> -	 */
> -	locked = READ_ONCE(rq->engine);
> -	spin_lock_irq(&locked->sched_engine->lock);
> -	while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
> -		spin_unlock(&locked->sched_engine->lock);
> -		spin_lock(&engine->sched_engine->lock);
> -		locked = engine;
> -	}
> -	list_del_init(&rq->sched.link);
> -
> -	clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
> -	clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
> -
> -	/* Prevent further __await_execution() registering a cb, then flush */
> -	set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
> -
> -	spin_unlock_irq(&locked->sched_engine->lock);
> -
> -	__notify_execute_cb_imm(rq);
> -}
> -
>   static void __rq_init_watchdog(struct i915_request *rq)
>   {
>   	rq->watchdog.timer.function = NULL;
> @@ -383,9 +352,7 @@ bool i915_request_retire(struct i915_request *rq)
>   	 * after removing the breadcrumb and signaling it, so that we do not
>   	 * inadvertently attach the breadcrumb to a completed request.
>   	 */
> -	if (!list_empty(&rq->sched.link))
> -		remove_from_engine(rq);
> -	atomic_dec(&rq->context->guc_id_ref);
> +	rq->engine->remove_active_request(rq);
>   	GEM_BUG_ON(!llist_empty(&rq->execute_cb));
>   
>   	__list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */
> @@ -516,7 +483,7 @@ __await_execution(struct i915_request *rq,
>   	if (llist_add(&cb->work.node.llist, &signal->execute_cb)) {
>   		if (i915_request_is_active(signal) ||
>   		    __request_in_flight(signal))
> -			__notify_execute_cb_imm(signal);
> +			i915_request_notify_execute_cb_imm(signal);
>   	}
>   
>   	return 0;
> @@ -653,7 +620,7 @@ bool __i915_request_submit(struct i915_request *request)
>   	result = true;
>   
>   	GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
> -	list_move_tail(&request->sched.link, &engine->sched_engine->requests);
> +	engine->add_active_request(request);
>   active:
>   	clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
>   	set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
> diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
> index 717e5b292046..128030f43bbf 100644
> --- a/drivers/gpu/drm/i915/i915_request.h
> +++ b/drivers/gpu/drm/i915/i915_request.h
> @@ -647,4 +647,6 @@ bool
>   i915_request_active_engine(struct i915_request *rq,
>   			   struct intel_engine_cs **active);
>   
> +void i915_request_notify_execute_cb_imm(struct i915_request *rq);
> +
>   #endif /* I915_REQUEST_H */

_______________________________________________
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  reply	other threads:[~2021-07-20 20:05 UTC|newest]

Thread overview: 221+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-16 20:16 [PATCH 00/51] GuC submission support Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 01/51] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 02/51] drm/i915/guc: Remove GuC stage descriptor, add LRC descriptor Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 03/51] drm/i915/guc: Add LRC descriptor context lookup array Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 04/51] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-19 23:01   ` John Harrison
2021-07-19 23:01     ` [Intel-gfx] " John Harrison
2021-07-19 22:55     ` Matthew Brost
2021-07-19 22:55       ` [Intel-gfx] " Matthew Brost
2021-07-20  0:26       ` John Harrison
2021-07-20  0:26         ` [Intel-gfx] " John Harrison
2021-07-16 20:16 ` [PATCH 05/51] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 06/51] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  0:23   ` John Harrison
2021-07-20  0:23     ` [Intel-gfx] " John Harrison
2021-07-20  2:45     ` Matthew Brost
2021-07-20  2:45       ` [Intel-gfx] " Matthew Brost
2021-07-20  0:51   ` Daniele Ceraolo Spurio
2021-07-20  0:51     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-20  4:04     ` Matthew Brost
2021-07-20  4:04       ` [Intel-gfx] " Matthew Brost
2021-07-21 23:51       ` Daniele Ceraolo Spurio
2021-07-21 23:51         ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-22  7:57         ` Michal Wajdeczko
2021-07-22  7:57           ` Michal Wajdeczko
2021-07-22 15:48           ` Matthew Brost
2021-07-22 15:48             ` Matthew Brost
2021-07-16 20:16 ` [PATCH 07/51] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 08/51] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 09/51] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 10/51] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 11/51] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 12/51] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-19 23:46   ` Daniele Ceraolo Spurio
2021-07-19 23:46     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-20  2:48     ` Matthew Brost
2021-07-20  2:48       ` [Intel-gfx] " Matthew Brost
2021-07-20  2:50       ` Matthew Brost
2021-07-20  2:50         ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 13/51] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  0:33   ` John Harrison
2021-07-20  0:33     ` [Intel-gfx] " John Harrison
2021-07-16 20:16 ` [PATCH 14/51] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 15/51] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  1:03   ` John Harrison
2021-07-20  1:03     ` [Intel-gfx] " John Harrison
2021-07-20  1:53     ` Matthew Brost
2021-07-20  1:53       ` [Intel-gfx] " Matthew Brost
2021-07-20 19:49       ` John Harrison
2021-07-20 19:49         ` [Intel-gfx] " John Harrison
2021-07-16 20:16 ` [PATCH 16/51] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  1:13   ` John Harrison
2021-07-20  1:13     ` [Intel-gfx] " John Harrison
2021-07-16 20:16 ` [PATCH 17/51] drm/i915/guc: Add several request trace points Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  1:27   ` John Harrison
2021-07-20  1:27     ` [Intel-gfx] " John Harrison
2021-07-20  2:10     ` Matthew Brost
2021-07-20  2:10       ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 18/51] drm/i915: Add intel_context tracing Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 19/51] drm/i915/guc: GuC virtual engines Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-19 23:33   ` Daniele Ceraolo Spurio
2021-07-19 23:33     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-19 23:27     ` Matthew Brost
2021-07-19 23:27       ` [Intel-gfx] " Matthew Brost
2021-07-19 23:42       ` Daniele Ceraolo Spurio
2021-07-19 23:42         ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-19 23:32         ` Matthew Brost
2021-07-19 23:32           ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 20/51] drm/i915: Track 'serial' counts for " Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20  1:28   ` John Harrison
2021-07-20  1:28     ` [Intel-gfx] " John Harrison
2021-07-20  1:54     ` Matthew Brost
2021-07-20  1:54       ` [Intel-gfx] " Matthew Brost
2021-07-20 16:47       ` Matthew Brost
2021-07-20 16:47         ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 21/51] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 22/51] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 23/51] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20 19:45   ` John Harrison
2021-07-20 19:45     ` [Intel-gfx] " John Harrison
2021-07-22 12:46   ` Tvrtko Ursulin
2021-07-22 12:46     ` Tvrtko Ursulin
2021-07-26 22:25     ` Matthew Brost
2021-07-26 22:25       ` Matthew Brost
2021-07-16 20:16 ` [PATCH 24/51] drm/i915: Add i915_sched_engine destroy vfunc Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20 19:55   ` John Harrison
2021-07-20 19:55     ` [Intel-gfx] " John Harrison
2021-07-20 19:53     ` Matthew Brost
2021-07-20 19:53       ` [Intel-gfx] " Matthew Brost
2021-07-16 20:16 ` [PATCH 25/51] drm/i915: Move active request tracking to a vfunc Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20 20:05   ` John Harrison [this message]
2021-07-20 20:05     ` John Harrison
2021-07-16 20:16 ` [PATCH 26/51] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-07-16 20:16   ` [Intel-gfx] " Matthew Brost
2021-07-20 20:19   ` John Harrison
2021-07-20 20:19     ` [Intel-gfx] " John Harrison
2021-07-20 20:59     ` Matthew Brost
2021-07-20 20:59       ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 27/51] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 28/51] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 29/51] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 30/51] drm/i915/guc: Handle context reset notification Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-20 20:29   ` John Harrison
2021-07-20 20:29     ` [Intel-gfx] " John Harrison
2021-07-20 20:38     ` Matthew Brost
2021-07-20 20:38       ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 31/51] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 32/51] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 33/51] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-22  4:47   ` Matthew Brost
2021-07-22  4:47     ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 34/51] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 35/51] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 36/51] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 37/51] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 38/51] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 39/51] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:04   ` Matthew Brost
2021-07-16 20:04     ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 40/51] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 41/51] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-19 17:24   ` Matthew Brost
2021-07-19 17:24     ` Matthew Brost
2021-07-19 18:25     ` John Harrison
2021-07-19 18:25       ` John Harrison
2021-07-19 18:30       ` Matthew Brost
2021-07-19 18:30         ` Matthew Brost
2021-07-16 20:17 ` [PATCH 42/51] drm/i915/guc: Implement banned contexts for GuC submission Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-20 21:41   ` John Harrison
2021-07-20 21:41     ` [Intel-gfx] " John Harrison
2021-07-16 20:17 ` [PATCH 43/51] drm/i915/guc: Support request cancellation Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-22 19:56   ` Daniele Ceraolo Spurio
2021-07-22 19:56     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-22 20:13     ` Matthew Brost
2021-07-22 20:13       ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 44/51] drm/i915/selftest: Better error reporting from hangcheck selftest Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 20:13   ` Matthew Brost
2021-07-16 20:13     ` Matthew Brost
2021-07-16 20:17 ` [PATCH 45/51] drm/i915/selftest: Fix workarounds selftest for GuC submission Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-20 17:14   ` Matthew Brost
2021-07-20 17:14     ` Matthew Brost
2021-07-16 20:17 ` [PATCH 46/51] drm/i915/selftest: Fix MOCS " Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 23:57   ` Matthew Brost
2021-07-16 23:57     ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 47/51] drm/i915/selftest: Increase some timeouts in live_requests Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-20 21:46   ` John Harrison
2021-07-20 21:46     ` [Intel-gfx] " John Harrison
2021-07-22  8:13   ` Tvrtko Ursulin
2021-07-22  8:13     ` Tvrtko Ursulin
2021-07-16 20:17 ` [PATCH 48/51] drm/i915/selftest: Fix hangcheck self test for GuC submission Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 23:43   ` Matthew Brost
2021-07-16 23:43     ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 49/51] drm/i915/selftest: Bump selftest timeouts for hangcheck Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-16 22:23   ` Matthew Brost
2021-07-16 22:23     ` [Intel-gfx] " Matthew Brost
2021-07-22  8:17   ` Tvrtko Ursulin
2021-07-22  8:17     ` Tvrtko Ursulin
2021-07-16 20:17 ` [PATCH 50/51] drm/i915/guc: Implement GuC priority management Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-22 20:26   ` Daniele Ceraolo Spurio
2021-07-22 20:26     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-22 21:38     ` Matthew Brost
2021-07-22 21:38       ` [Intel-gfx] " Matthew Brost
2021-07-22 21:50       ` Daniele Ceraolo Spurio
2021-07-22 21:50         ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-07-22 21:55         ` Matthew Brost
2021-07-22 21:55           ` [Intel-gfx] " Matthew Brost
2021-07-16 20:17 ` [PATCH 51/51] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-07-16 20:17   ` [Intel-gfx] " Matthew Brost
2021-07-17  1:10 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev3) Patchwork
2021-07-19  9:06 ` [Intel-gfx] [PATCH 00/51] GuC submission support Tvrtko Ursulin
2021-07-19  9:06   ` Tvrtko Ursulin

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