From: Apurva Nandan <a-nandan@ti.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Mark Brown <broonie@kernel.org>, Apurva Nandan <a-nandan@ti.com>, Patrice Chotard <patrice.chotard@foss.st.com>, Christophe Kerello <christophe.kerello@foss.st.com>, Boris Brezillon <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org> Cc: <p.yadav@ti.com> Subject: [PATCH v2 09/14] mtd: spinand: winbond: Add octal_dtr_enable() for manufacturer_ops Date: Tue, 12 Oct 2021 02:16:14 +0530 [thread overview] Message-ID: <20211011204619.81893-10-a-nandan@ti.com> (raw) In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> Add implementation of octal_dtr_enable() manufacturer_ops for Winbond. To switch to Ocatl DTR mode, setting programmable dummy cycles and SPI IO mode using the volatile configuration register is required. To function at max 120MHz SPI clock in Octal DTR mode, 12 programmable dummy clock cycle setting is required. (Default number of dummy cycle are 8 clocks) Set the programmable dummy cycle to 12 clocks, and SPI IO mode to Octal DTR with Data Strobe in the VCR. Also, perform a READ ID operation in Octal DTR SPI mode to ensure the switch was successful. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan <a-nandan@ti.com> --- drivers/mtd/nand/spi/winbond.c | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 89d8ee801f56..e2cb82d68f96 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -16,6 +16,14 @@ #define WINBOND_CFG_BUF_READ BIT(3) +/* Octal DTR SPI mode (8D-8D-8D) with Data Strobe output*/ +#define WINBOND_IO_MODE_VCR_OCTAL_DTR 0xE7 +#define WINBOND_IO_MODE_VCR_ADDR 0x00 + +/* Use 12 dummy clk cycles for using Octal DTR SPI at max 120MHZ */ +#define WINBOND_DUMMY_CLK_COUNT 12 +#define WINBOND_DUMMY_CLK_VCR_ADDR 0x01 + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), @@ -156,8 +164,42 @@ static int winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, u8 val) return 0; } +static int winbond_spinand_octal_dtr_enable(struct spinand_device *spinand) +{ + int ret; + struct spi_mem_op op; + + ret = winbond_write_vcr_op(spinand, WINBOND_DUMMY_CLK_VCR_ADDR, + WINBOND_DUMMY_CLK_COUNT); + if (ret) + return ret; + + ret = winbond_write_vcr_op(spinand, WINBOND_IO_MODE_VCR_ADDR, + WINBOND_IO_MODE_VCR_OCTAL_DTR); + if (ret) + return ret; + + /* Read flash ID to make sure the switch was successful. */ + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD_DTR(2, 0x9f9f, 8), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_DUMMY_DTR(16, 8), + SPI_MEM_OP_DATA_IN_DTR(SPINAND_MAX_ID_LEN, + spinand->scratchbuf, 8)); + + ret = spi_mem_exec_op(spinand->spimem, &op); + if (ret) + return ret; + + if (memcmp(spinand->scratchbuf, spinand->id.data, SPINAND_MAX_ID_LEN)) + return -EINVAL; + + return 0; +} + static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { .init = winbond_spinand_init, + .octal_dtr_enable = winbond_spinand_octal_dtr_enable, }; const struct spinand_manufacturer winbond_spinand_manufacturer = { -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Apurva Nandan <a-nandan@ti.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Mark Brown <broonie@kernel.org>, Apurva Nandan <a-nandan@ti.com>, Patrice Chotard <patrice.chotard@foss.st.com>, Christophe Kerello <christophe.kerello@foss.st.com>, Boris Brezillon <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org> Cc: <p.yadav@ti.com> Subject: [PATCH v2 09/14] mtd: spinand: winbond: Add octal_dtr_enable() for manufacturer_ops Date: Tue, 12 Oct 2021 02:16:14 +0530 [thread overview] Message-ID: <20211011204619.81893-10-a-nandan@ti.com> (raw) In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> Add implementation of octal_dtr_enable() manufacturer_ops for Winbond. To switch to Ocatl DTR mode, setting programmable dummy cycles and SPI IO mode using the volatile configuration register is required. To function at max 120MHz SPI clock in Octal DTR mode, 12 programmable dummy clock cycle setting is required. (Default number of dummy cycle are 8 clocks) Set the programmable dummy cycle to 12 clocks, and SPI IO mode to Octal DTR with Data Strobe in the VCR. Also, perform a READ ID operation in Octal DTR SPI mode to ensure the switch was successful. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan <a-nandan@ti.com> --- drivers/mtd/nand/spi/winbond.c | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 89d8ee801f56..e2cb82d68f96 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -16,6 +16,14 @@ #define WINBOND_CFG_BUF_READ BIT(3) +/* Octal DTR SPI mode (8D-8D-8D) with Data Strobe output*/ +#define WINBOND_IO_MODE_VCR_OCTAL_DTR 0xE7 +#define WINBOND_IO_MODE_VCR_ADDR 0x00 + +/* Use 12 dummy clk cycles for using Octal DTR SPI at max 120MHZ */ +#define WINBOND_DUMMY_CLK_COUNT 12 +#define WINBOND_DUMMY_CLK_VCR_ADDR 0x01 + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), @@ -156,8 +164,42 @@ static int winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, u8 val) return 0; } +static int winbond_spinand_octal_dtr_enable(struct spinand_device *spinand) +{ + int ret; + struct spi_mem_op op; + + ret = winbond_write_vcr_op(spinand, WINBOND_DUMMY_CLK_VCR_ADDR, + WINBOND_DUMMY_CLK_COUNT); + if (ret) + return ret; + + ret = winbond_write_vcr_op(spinand, WINBOND_IO_MODE_VCR_ADDR, + WINBOND_IO_MODE_VCR_OCTAL_DTR); + if (ret) + return ret; + + /* Read flash ID to make sure the switch was successful. */ + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD_DTR(2, 0x9f9f, 8), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_DUMMY_DTR(16, 8), + SPI_MEM_OP_DATA_IN_DTR(SPINAND_MAX_ID_LEN, + spinand->scratchbuf, 8)); + + ret = spi_mem_exec_op(spinand->spimem, &op); + if (ret) + return ret; + + if (memcmp(spinand->scratchbuf, spinand->id.data, SPINAND_MAX_ID_LEN)) + return -EINVAL; + + return 0; +} + static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { .init = winbond_spinand_init, + .octal_dtr_enable = winbond_spinand_octal_dtr_enable, }; const struct spinand_manufacturer winbond_spinand_manufacturer = { -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2021-10-11 20:49 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-11 20:46 [PATCH v2 00/14] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 01/14] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 02/14] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:39 ` Boris Brezillon 2021-10-12 6:39 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 03/14] mtd: spinand: Patch spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:40 ` Boris Brezillon 2021-10-12 6:40 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 04/14] mtd: spinand: Fix odd byte addr and data phase in read and write reg op for Octal DTR mode Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 05/14] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:54 ` Boris Brezillon 2021-10-12 6:54 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 06/14] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 07/14] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 7:14 ` Boris Brezillon 2021-10-12 7:14 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 08/14] mtd: spinand: winbond: Add support for write volatile configuration register op Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan [this message] 2021-10-11 20:46 ` [PATCH v2 09/14] mtd: spinand: winbond: Add octal_dtr_enable() for manufacturer_ops Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 10/14] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 11/14] mtd: spinand: Perform Power-on-Reset on the flash in mtd_suspend() Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 7:25 ` Boris Brezillon 2021-10-12 7:25 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 12/14] mtd: spinand: Add adjust_op() in Winbond manufacturer_ops Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 13/14] mtd: spinand: winbond: Rename cache op_variants struct variable Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 14/14] mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan
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