From: Boris Brezillon <boris.brezillon@collabora.com> To: Apurva Nandan <a-nandan@ti.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Mark Brown <broonie@kernel.org>, Patrice Chotard <patrice.chotard@foss.st.com>, Christophe Kerello <christophe.kerello@foss.st.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, <p.yadav@ti.com> Subject: Re: [PATCH v2 02/14] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Date: Tue, 12 Oct 2021 08:39:06 +0200 [thread overview] Message-ID: <20211012083906.30c50009@collabora.com> (raw) In-Reply-To: <20211011204619.81893-3-a-nandan@ti.com> On Tue, 12 Oct 2021 02:16:07 +0530 Apurva Nandan <a-nandan@ti.com> wrote: > Unlike Dual and Quad SPI modes flashes, Octal DTR SPI NAND flashes > require all instructions to be made in 8D-8D-8D protocol when the > flash is in Octal DTR mode. Hence, storing the current SPI IO mode > becomes necessary for correctly generating non-array access operations. > > Store the current SPI IO mode in the spinand struct using a reg_proto > enum. This would act as a flag, denoting that the core should use > the given SPI protocol for non-page access operations. > > Also provide basic macros for extracting buswidth and dtr mode > information from the spinand_proto enum. > > Signed-off-by: Apurva Nandan <a-nandan@ti.com> > --- > drivers/mtd/nand/spi/core.c | 2 ++ > include/linux/mtd/spinand.h | 30 ++++++++++++++++++++++++++++++ > 2 files changed, 32 insertions(+) > > diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c > index 2c8685f1f2fa..d82a3e6d9bb5 100644 > --- a/drivers/mtd/nand/spi/core.c > +++ b/drivers/mtd/nand/spi/core.c > @@ -1155,6 +1155,7 @@ static void spinand_mtd_resume(struct mtd_info *mtd) > struct spinand_device *spinand = mtd_to_spinand(mtd); > int ret; > > + spinand->reg_proto = SPINAND_SINGLE_STR; > ret = spinand_reset_op(spinand); > if (ret) > return; > @@ -1181,6 +1182,7 @@ static int spinand_init(struct spinand_device *spinand) > if (!spinand->scratchbuf) > return -ENOMEM; > > + spinand->reg_proto = SPINAND_SINGLE_STR; > ret = spinand_detect(spinand); > if (ret) > goto err_free_bufs; > diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h > index 6988956b8492..f6093cd98d7b 100644 > --- a/include/linux/mtd/spinand.h > +++ b/include/linux/mtd/spinand.h > @@ -140,6 +140,31 @@ > SPI_MEM_OP_NO_DUMMY, \ > SPI_MEM_OP_DATA_OUT(len, buf, 4)) > > +#define SPINAND_PROTO_BUSWIDTH_MASK GENMASK(6, 0) > +#define SPINAND_PROTO_DTR_BIT BIT(7) > + > +#define SPINAND_PROTO_STR(__buswidth) \ > + ((u8)(((__buswidth) - 1) & SPINAND_PROTO_BUSWIDTH_MASK)) > +#define SPINAND_PROTO_DTR(__buswidth) \ > + (SPINAND_PROTO_DTR_BIT | SPINAND_PROTO_STR(__buswidth)) > + > +#define SPINAND_PROTO_BUSWIDTH(__proto) \ > + ((u8)(((__proto) & SPINAND_PROTO_BUSWIDTH_MASK) + 1)) > +#define SPINAND_PROTO_IS_DTR(__proto) (!!((__proto) & SPINAND_PROTO_DTR_BIT)) > + > +/** > + * enum spinand_proto - List allowable SPI protocol variants for read reg, > + * write reg, blk erase, write enable/disable, page read > + * and program exec operations. > + */ > +enum spinand_proto { s/spinand_proto/spinand_protocol/ > + SPINAND_SINGLE_STR = SPINAND_PROTO_STR(1), > + SPINAND_DUAL_STR = SPINAND_PROTO_STR(2), > + SPINAND_QUAD_STR = SPINAND_PROTO_STR(4), > + SPINAND_OCTAL_STR = SPINAND_PROTO_STR(8), > + SPINAND_OCTAL_DTR = SPINAND_PROTO_DTR(8), Why not have a contiguous enum listing all the modes? Are you extracting the buswidth from these values? > +}; > + > /** > * Standard SPI NAND flash commands > */ > @@ -407,6 +432,9 @@ struct spinand_dirmap { > * this die. Only required if your chip exposes several dies > * @cur_target: currently selected target/die > * @eccinfo: on-die ECC information > + * @reg_proto: select a variant of SPI IO protocol (single, quad, octal or > + * octal DTR) for read_reg/write_reg/erase operations. Update on > + * successful transition into a different SPI IO protocol. > * @cfg_cache: config register cache. One entry per die > * @databuf: bounce buffer for data > * @oobbuf: bounce buffer for OOB data > @@ -438,6 +466,8 @@ struct spinand_device { > > struct spinand_ecc_info eccinfo; > > + enum spinand_proto reg_proto; > + I guess this mode will apply to all sort of commands, not just reg accesses, so why not name it protocol or mode? > u8 *cfg_cache; > u8 *databuf; > u8 *oobbuf;
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com> To: Apurva Nandan <a-nandan@ti.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Mark Brown <broonie@kernel.org>, Patrice Chotard <patrice.chotard@foss.st.com>, Christophe Kerello <christophe.kerello@foss.st.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, <p.yadav@ti.com> Subject: Re: [PATCH v2 02/14] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Date: Tue, 12 Oct 2021 08:39:06 +0200 [thread overview] Message-ID: <20211012083906.30c50009@collabora.com> (raw) In-Reply-To: <20211011204619.81893-3-a-nandan@ti.com> On Tue, 12 Oct 2021 02:16:07 +0530 Apurva Nandan <a-nandan@ti.com> wrote: > Unlike Dual and Quad SPI modes flashes, Octal DTR SPI NAND flashes > require all instructions to be made in 8D-8D-8D protocol when the > flash is in Octal DTR mode. Hence, storing the current SPI IO mode > becomes necessary for correctly generating non-array access operations. > > Store the current SPI IO mode in the spinand struct using a reg_proto > enum. This would act as a flag, denoting that the core should use > the given SPI protocol for non-page access operations. > > Also provide basic macros for extracting buswidth and dtr mode > information from the spinand_proto enum. > > Signed-off-by: Apurva Nandan <a-nandan@ti.com> > --- > drivers/mtd/nand/spi/core.c | 2 ++ > include/linux/mtd/spinand.h | 30 ++++++++++++++++++++++++++++++ > 2 files changed, 32 insertions(+) > > diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c > index 2c8685f1f2fa..d82a3e6d9bb5 100644 > --- a/drivers/mtd/nand/spi/core.c > +++ b/drivers/mtd/nand/spi/core.c > @@ -1155,6 +1155,7 @@ static void spinand_mtd_resume(struct mtd_info *mtd) > struct spinand_device *spinand = mtd_to_spinand(mtd); > int ret; > > + spinand->reg_proto = SPINAND_SINGLE_STR; > ret = spinand_reset_op(spinand); > if (ret) > return; > @@ -1181,6 +1182,7 @@ static int spinand_init(struct spinand_device *spinand) > if (!spinand->scratchbuf) > return -ENOMEM; > > + spinand->reg_proto = SPINAND_SINGLE_STR; > ret = spinand_detect(spinand); > if (ret) > goto err_free_bufs; > diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h > index 6988956b8492..f6093cd98d7b 100644 > --- a/include/linux/mtd/spinand.h > +++ b/include/linux/mtd/spinand.h > @@ -140,6 +140,31 @@ > SPI_MEM_OP_NO_DUMMY, \ > SPI_MEM_OP_DATA_OUT(len, buf, 4)) > > +#define SPINAND_PROTO_BUSWIDTH_MASK GENMASK(6, 0) > +#define SPINAND_PROTO_DTR_BIT BIT(7) > + > +#define SPINAND_PROTO_STR(__buswidth) \ > + ((u8)(((__buswidth) - 1) & SPINAND_PROTO_BUSWIDTH_MASK)) > +#define SPINAND_PROTO_DTR(__buswidth) \ > + (SPINAND_PROTO_DTR_BIT | SPINAND_PROTO_STR(__buswidth)) > + > +#define SPINAND_PROTO_BUSWIDTH(__proto) \ > + ((u8)(((__proto) & SPINAND_PROTO_BUSWIDTH_MASK) + 1)) > +#define SPINAND_PROTO_IS_DTR(__proto) (!!((__proto) & SPINAND_PROTO_DTR_BIT)) > + > +/** > + * enum spinand_proto - List allowable SPI protocol variants for read reg, > + * write reg, blk erase, write enable/disable, page read > + * and program exec operations. > + */ > +enum spinand_proto { s/spinand_proto/spinand_protocol/ > + SPINAND_SINGLE_STR = SPINAND_PROTO_STR(1), > + SPINAND_DUAL_STR = SPINAND_PROTO_STR(2), > + SPINAND_QUAD_STR = SPINAND_PROTO_STR(4), > + SPINAND_OCTAL_STR = SPINAND_PROTO_STR(8), > + SPINAND_OCTAL_DTR = SPINAND_PROTO_DTR(8), Why not have a contiguous enum listing all the modes? Are you extracting the buswidth from these values? > +}; > + > /** > * Standard SPI NAND flash commands > */ > @@ -407,6 +432,9 @@ struct spinand_dirmap { > * this die. Only required if your chip exposes several dies > * @cur_target: currently selected target/die > * @eccinfo: on-die ECC information > + * @reg_proto: select a variant of SPI IO protocol (single, quad, octal or > + * octal DTR) for read_reg/write_reg/erase operations. Update on > + * successful transition into a different SPI IO protocol. > * @cfg_cache: config register cache. One entry per die > * @databuf: bounce buffer for data > * @oobbuf: bounce buffer for OOB data > @@ -438,6 +466,8 @@ struct spinand_device { > > struct spinand_ecc_info eccinfo; > > + enum spinand_proto reg_proto; > + I guess this mode will apply to all sort of commands, not just reg accesses, so why not name it protocol or mode? > u8 *cfg_cache; > u8 *databuf; > u8 *oobbuf; ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2021-10-12 6:39 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-11 20:46 [PATCH v2 00/14] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 01/14] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 02/14] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:39 ` Boris Brezillon [this message] 2021-10-12 6:39 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 03/14] mtd: spinand: Patch spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:40 ` Boris Brezillon 2021-10-12 6:40 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 04/14] mtd: spinand: Fix odd byte addr and data phase in read and write reg op for Octal DTR mode Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 05/14] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:54 ` Boris Brezillon 2021-10-12 6:54 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 06/14] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 07/14] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 7:14 ` Boris Brezillon 2021-10-12 7:14 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 08/14] mtd: spinand: winbond: Add support for write volatile configuration register op Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 09/14] mtd: spinand: winbond: Add octal_dtr_enable() for manufacturer_ops Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 10/14] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 11/14] mtd: spinand: Perform Power-on-Reset on the flash in mtd_suspend() Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 7:25 ` Boris Brezillon 2021-10-12 7:25 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 12/14] mtd: spinand: Add adjust_op() in Winbond manufacturer_ops Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 13/14] mtd: spinand: winbond: Rename cache op_variants struct variable Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 14/14] mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan
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