From: Apurva Nandan <a-nandan@ti.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Mark Brown <broonie@kernel.org>, Apurva Nandan <a-nandan@ti.com>, Patrice Chotard <patrice.chotard@foss.st.com>, Christophe Kerello <christophe.kerello@foss.st.com>, Boris Brezillon <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org> Cc: <p.yadav@ti.com> Subject: [PATCH v2 04/14] mtd: spinand: Fix odd byte addr and data phase in read and write reg op for Octal DTR mode Date: Tue, 12 Oct 2021 02:16:09 +0530 [thread overview] Message-ID: <20211011204619.81893-5-a-nandan@ti.com> (raw) In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> In Octal DTR SPI mode, 2 bytes of data gets transmitted over one clock cycle, and half-cycle instruction phases aren't supported yet. So, every DTR spi_mem_op needs to have even nbytes in all phases for non-erratic behaviour from the SPI controller. The odd length cmd and dummy phases get handled by spimem_patch_op() but the odd length address and data phases need to be handled according to the use case. For example in Octal DTR mode, read register operation has one byte long address and data phase. So it needs to extend it by adding a suitable extra byte in addr and reading 2 bytes of data, discarding the second byte. Handle address and data phases for Octal DTR mode in read and write register operations by adding a suitable extra byte in the address and data phase. Create spimem_patch_reg_op() helper function to ease setting up read/write register operations in other functions, e.g. wait(). Signed-off-by: Apurva Nandan <a-nandan@ti.com> --- drivers/mtd/nand/spi/core.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 11746d858f87..4da794ae728d 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -63,12 +63,29 @@ static void spinand_patch_op(const struct spinand_device *spinand, } } +static void spinand_patch_reg_op(const struct spinand_device *spinand, + struct spi_mem_op *op) +{ + if (spinand->reg_proto == SPINAND_OCTAL_DTR) { + /* + * Assigning same first and second byte will result in constant + * bits on the SPI bus between positive and negative clock edges + */ + op->addr.val = (op->addr.val << 8) | op->addr.val; + op->addr.nbytes = 2; + op->data.nbytes = 2; + } + + spinand_patch_op(spinand, op); +} + static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) { struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg, spinand->scratchbuf); int ret; + spinand_patch_reg_op(spinand, &op); ret = spi_mem_exec_op(spinand->spimem, &op); if (ret) return ret; @@ -82,7 +99,8 @@ static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val) struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg, spinand->scratchbuf); - *spinand->scratchbuf = val; + spinand_patch_reg_op(spinand, &op); + memset(spinand->scratchbuf, val, op.data.nbytes); return spi_mem_exec_op(spinand->spimem, &op); } @@ -547,6 +565,7 @@ static int spinand_wait(struct spinand_device *spinand, u8 status; int ret; + spinand_patch_reg_op(spinand, &op); ret = spi_mem_poll_status(spinand->spimem, &op, STATUS_BUSY, 0, initial_delay_us, poll_delay_us, -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: Apurva Nandan <a-nandan@ti.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Mark Brown <broonie@kernel.org>, Apurva Nandan <a-nandan@ti.com>, Patrice Chotard <patrice.chotard@foss.st.com>, Christophe Kerello <christophe.kerello@foss.st.com>, Boris Brezillon <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org> Cc: <p.yadav@ti.com> Subject: [PATCH v2 04/14] mtd: spinand: Fix odd byte addr and data phase in read and write reg op for Octal DTR mode Date: Tue, 12 Oct 2021 02:16:09 +0530 [thread overview] Message-ID: <20211011204619.81893-5-a-nandan@ti.com> (raw) In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> In Octal DTR SPI mode, 2 bytes of data gets transmitted over one clock cycle, and half-cycle instruction phases aren't supported yet. So, every DTR spi_mem_op needs to have even nbytes in all phases for non-erratic behaviour from the SPI controller. The odd length cmd and dummy phases get handled by spimem_patch_op() but the odd length address and data phases need to be handled according to the use case. For example in Octal DTR mode, read register operation has one byte long address and data phase. So it needs to extend it by adding a suitable extra byte in addr and reading 2 bytes of data, discarding the second byte. Handle address and data phases for Octal DTR mode in read and write register operations by adding a suitable extra byte in the address and data phase. Create spimem_patch_reg_op() helper function to ease setting up read/write register operations in other functions, e.g. wait(). Signed-off-by: Apurva Nandan <a-nandan@ti.com> --- drivers/mtd/nand/spi/core.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 11746d858f87..4da794ae728d 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -63,12 +63,29 @@ static void spinand_patch_op(const struct spinand_device *spinand, } } +static void spinand_patch_reg_op(const struct spinand_device *spinand, + struct spi_mem_op *op) +{ + if (spinand->reg_proto == SPINAND_OCTAL_DTR) { + /* + * Assigning same first and second byte will result in constant + * bits on the SPI bus between positive and negative clock edges + */ + op->addr.val = (op->addr.val << 8) | op->addr.val; + op->addr.nbytes = 2; + op->data.nbytes = 2; + } + + spinand_patch_op(spinand, op); +} + static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) { struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg, spinand->scratchbuf); int ret; + spinand_patch_reg_op(spinand, &op); ret = spi_mem_exec_op(spinand->spimem, &op); if (ret) return ret; @@ -82,7 +99,8 @@ static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val) struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg, spinand->scratchbuf); - *spinand->scratchbuf = val; + spinand_patch_reg_op(spinand, &op); + memset(spinand->scratchbuf, val, op.data.nbytes); return spi_mem_exec_op(spinand->spimem, &op); } @@ -547,6 +565,7 @@ static int spinand_wait(struct spinand_device *spinand, u8 status; int ret; + spinand_patch_reg_op(spinand, &op); ret = spi_mem_poll_status(spinand->spimem, &op, STATUS_BUSY, 0, initial_delay_us, poll_delay_us, -- 2.25.1
next prev parent reply other threads:[~2021-10-11 20:48 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-11 20:46 [PATCH v2 00/14] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 01/14] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 02/14] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:39 ` Boris Brezillon 2021-10-12 6:39 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 03/14] mtd: spinand: Patch spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:40 ` Boris Brezillon 2021-10-12 6:40 ` Boris Brezillon 2021-10-11 20:46 ` Apurva Nandan [this message] 2021-10-11 20:46 ` [PATCH v2 04/14] mtd: spinand: Fix odd byte addr and data phase in read and write reg op for Octal DTR mode Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 05/14] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:54 ` Boris Brezillon 2021-10-12 6:54 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 06/14] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 07/14] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 7:14 ` Boris Brezillon 2021-10-12 7:14 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 08/14] mtd: spinand: winbond: Add support for write volatile configuration register op Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 09/14] mtd: spinand: winbond: Add octal_dtr_enable() for manufacturer_ops Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 10/14] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 11/14] mtd: spinand: Perform Power-on-Reset on the flash in mtd_suspend() Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 7:25 ` Boris Brezillon 2021-10-12 7:25 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 12/14] mtd: spinand: Add adjust_op() in Winbond manufacturer_ops Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 13/14] mtd: spinand: winbond: Rename cache op_variants struct variable Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 14/14] mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan
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