* [PATCH v2 1/3] rockchip: Kconfig: Enable SPL support for rk3568
2021-10-25 6:33 [PATCH v2 0/3] Add SPL build support for RK3568 Nico Cheng
@ 2021-10-25 6:33 ` Nico Cheng
2021-10-25 12:57 ` Philipp Tomsich
2021-10-25 6:33 ` [PATCH v2 2/3] arm: dts: rockchip: rk3568: Enable sdhci and sdmmc0 node Nico Cheng
2021-10-25 6:33 ` [PATCH v2 3/3] rockchip: rk3568: add arch_cpu_init() Nico Cheng
2 siblings, 1 reply; 7+ messages in thread
From: Nico Cheng @ 2021-10-25 6:33 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: yamada.masahiro, chenjh, jason.zhu, trini, yifeng.zhao,
nico.cheng, u-boot
Enable SPL support in Kconfig and add some related option in
rk3568_common.h
Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
---
(no changes since v1)
arch/arm/mach-rockchip/Kconfig | 2 ++
configs/evb-rk3568_defconfig | 25 ++++++++++++++++++++++++-
include/configs/rk3568_common.h | 4 ++++
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index b164afb529..21b9c381cf 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -260,6 +260,8 @@ config ROCKCHIP_RK3399
config ROCKCHIP_RK3568
bool "Support Rockchip RK3568"
select ARM64
+ select SUPPORT_SPL
+ select SPL
select CLK
select PINCTRL
select RAM
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index a102a5a999..a145b71ac2 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -1,20 +1,42 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
@@ -28,6 +50,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h
index b6568917ea..47fc91779e 100644
--- a/include/configs/rk3568_common.h
+++ b/include/configs/rk3568_common.h
@@ -18,6 +18,10 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
#define CONFIG_SYS_LOAD_ADDR 0x00c00800
+#define CONFIG_SPL_STACK 0x00400000
+#define CONFIG_SPL_MAX_SIZE 0x20000
+#define CONFIG_SPL_BSS_START_ADDR 0x4000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x4000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define CONFIG_SYS_SDRAM_BASE 0
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/3] rockchip: Kconfig: Enable SPL support for rk3568
2021-10-25 6:33 ` [PATCH v2 1/3] rockchip: Kconfig: Enable SPL support for rk3568 Nico Cheng
@ 2021-10-25 12:57 ` Philipp Tomsich
0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2021-10-25 12:57 UTC (permalink / raw)
To: Nico Cheng
Cc: Simon Glass, Kever Yang, yamada.masahiro, chenjh, jason.zhu,
trini, Yifeng Zhao, U-Boot Mailing List
On Mon, 25 Oct 2021 at 08:34, Nico Cheng <nico.cheng@rock-chips.com> wrote:
>
> Enable SPL support in Kconfig and add some related option in
> rk3568_common.h
>
> Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
> Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 2/3] arm: dts: rockchip: rk3568: Enable sdhci and sdmmc0 node
2021-10-25 6:33 [PATCH v2 0/3] Add SPL build support for RK3568 Nico Cheng
2021-10-25 6:33 ` [PATCH v2 1/3] rockchip: Kconfig: Enable SPL support for rk3568 Nico Cheng
@ 2021-10-25 6:33 ` Nico Cheng
2021-10-25 12:59 ` Philipp Tomsich
2021-10-25 6:33 ` [PATCH v2 3/3] rockchip: rk3568: add arch_cpu_init() Nico Cheng
2 siblings, 1 reply; 7+ messages in thread
From: Nico Cheng @ 2021-10-25 6:33 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: yamada.masahiro, chenjh, jason.zhu, trini, yifeng.zhao,
nico.cheng, u-boot
Enable sdhci and sdmmc0 node in rk3568-u-boot.dtsi
Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
---
(no changes since v1)
arch/arm/dts/rk3568-u-boot.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi
index 1570f13fc7..5a80dda275 100644
--- a/arch/arm/dts/rk3568-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-u-boot.dtsi
@@ -9,6 +9,10 @@
mmc1 = &sdmmc0;
};
+ chosen {
+ u-boot,spl-boot-order = &sdhci, &sdmmc0;
+ };
+
dmc: dmc {
compatible = "rockchip,rk3568-dmc";
u-boot,dm-pre-reloc;
@@ -35,3 +39,16 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&sdmmc0 {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ u-boot,dm-spl;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2 2/3] arm: dts: rockchip: rk3568: Enable sdhci and sdmmc0 node
2021-10-25 6:33 ` [PATCH v2 2/3] arm: dts: rockchip: rk3568: Enable sdhci and sdmmc0 node Nico Cheng
@ 2021-10-25 12:59 ` Philipp Tomsich
0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2021-10-25 12:59 UTC (permalink / raw)
To: Nico Cheng
Cc: Simon Glass, Kever Yang, yamada.masahiro, chenjh, jason.zhu,
trini, Yifeng Zhao, U-Boot Mailing List
On Mon, 25 Oct 2021 at 08:34, Nico Cheng <nico.cheng@rock-chips.com> wrote:
>
> Enable sdhci and sdmmc0 node in rk3568-u-boot.dtsi
>
> Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/3] rockchip: rk3568: add arch_cpu_init()
2021-10-25 6:33 [PATCH v2 0/3] Add SPL build support for RK3568 Nico Cheng
2021-10-25 6:33 ` [PATCH v2 1/3] rockchip: Kconfig: Enable SPL support for rk3568 Nico Cheng
2021-10-25 6:33 ` [PATCH v2 2/3] arm: dts: rockchip: rk3568: Enable sdhci and sdmmc0 node Nico Cheng
@ 2021-10-25 6:33 ` Nico Cheng
2021-10-25 13:04 ` Philipp Tomsich
2 siblings, 1 reply; 7+ messages in thread
From: Nico Cheng @ 2021-10-25 6:33 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: yamada.masahiro, chenjh, jason.zhu, trini, yifeng.zhao,
nico.cheng, u-boot
We configured the drive strength and security of EMMC in
arch_cpu_init().
Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
---
Changes in v2:
We use the rk_clrreg function instead of the writel to set eMMC sdmmc0 to
secure.
Modify comments to make them more explicit.
arch/arm/mach-rockchip/rk3568/rk3568.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 973b4f9dcb..1a62052731 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -13,6 +13,14 @@
#define PMUGRF_BASE 0xfdc20000
#define GRF_BASE 0xfdc60000
+#define GRF_GPIO1B_DS_2 0x218
+#define GRF_GPIO1B_DS_3 0x21c
+#define GRF_GPIO1C_DS_0 0x220
+#define GRF_GPIO1C_DS_1 0x224
+#define GRF_GPIO1C_DS_2 0x228
+#define GRF_GPIO1C_DS_3 0x22c
+#define SGRF_BASE 0xFDD18000
+#define SGRF_SOC_CON4 0x10
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
@@ -81,5 +89,16 @@ void board_debug_uart_init(void)
int arch_cpu_init(void)
{
+#ifdef CONFIG_SPL_BUILD
+ /* Set the emmc sdmmc0 to secure */
+ rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (0x3 << 11 | 0x1 << 4));
+ /* set the emmc driver strength to level 2 */
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
+#endif
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2 3/3] rockchip: rk3568: add arch_cpu_init()
2021-10-25 6:33 ` [PATCH v2 3/3] rockchip: rk3568: add arch_cpu_init() Nico Cheng
@ 2021-10-25 13:04 ` Philipp Tomsich
0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2021-10-25 13:04 UTC (permalink / raw)
To: Nico Cheng
Cc: Simon Glass, Kever Yang, yamada.masahiro, chenjh, jason.zhu,
trini, Yifeng Zhao, U-Boot Mailing List
On Mon, 25 Oct 2021 at 08:34, Nico Cheng <nico.cheng@rock-chips.com> wrote:
>
> We configured the drive strength and security of EMMC in
> arch_cpu_init().
>
> Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
> ---
>
> Changes in v2:
> We use the rk_clrreg function instead of the writel to set eMMC sdmmc0 to
> secure.
> Modify comments to make them more explicit.
>
> arch/arm/mach-rockchip/rk3568/rk3568.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
> index 973b4f9dcb..1a62052731 100644
> --- a/arch/arm/mach-rockchip/rk3568/rk3568.c
> +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
> @@ -13,6 +13,14 @@
>
> #define PMUGRF_BASE 0xfdc20000
> #define GRF_BASE 0xfdc60000
> +#define GRF_GPIO1B_DS_2 0x218
> +#define GRF_GPIO1B_DS_3 0x21c
> +#define GRF_GPIO1C_DS_0 0x220
> +#define GRF_GPIO1C_DS_1 0x224
> +#define GRF_GPIO1C_DS_2 0x228
> +#define GRF_GPIO1C_DS_3 0x22c
> +#define SGRF_BASE 0xFDD18000
> +#define SGRF_SOC_CON4 0x10
>
> /* PMU_GRF_GPIO0D_IOMUX_L */
> enum {
> @@ -81,5 +89,16 @@ void board_debug_uart_init(void)
>
> int arch_cpu_init(void)
> {
> +#ifdef CONFIG_SPL_BUILD
> + /* Set the emmc sdmmc0 to secure */
> + rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (0x3 << 11 | 0x1 << 4));
Please introduce symbolic constants (or at least a C99 'const'
expressions with a suitable names) to clarify what bits[12:11]
and bit[4] control?
> + /* set the emmc driver strength to level 2 */
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
> +#endif
> return 0;
> }
> --
> 2.17.1
>
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread