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* [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU
@ 2021-11-26 11:55 ` Marc Zyngier
  0 siblings, 0 replies; 8+ messages in thread
From: Marc Zyngier @ 2021-11-26 11:55 UTC (permalink / raw)
  To: linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team

When running a KVM guest hosted on an ARMv8.7 machine, the host
kernel complains that it doesn't know about the architected number
of events.

Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 1 +
 arch/arm64/kvm/pmu-emul.c       | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index cdb590840b3f..5de90138d0a4 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1036,6 +1036,7 @@
 #define ID_AA64DFR0_PMUVER_8_1		0x4
 #define ID_AA64DFR0_PMUVER_8_4		0x5
 #define ID_AA64DFR0_PMUVER_8_5		0x6
+#define ID_AA64DFR0_PMUVER_8_7		0x7
 #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
 
 #define ID_AA64DFR0_PMSVER_8_2		0x1
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index a5e4bbf5e68f..ca92cc5c71c6 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
 	case ID_AA64DFR0_PMUVER_8_1:
 	case ID_AA64DFR0_PMUVER_8_4:
 	case ID_AA64DFR0_PMUVER_8_5:
+	case ID_AA64DFR0_PMUVER_8_7:
 		return GENMASK(15, 0);
 	default:		/* Shouldn't be here, just for sanity */
 		WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
-- 
2.30.2

_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU
@ 2021-11-26 11:55 ` Marc Zyngier
  0 siblings, 0 replies; 8+ messages in thread
From: Marc Zyngier @ 2021-11-26 11:55 UTC (permalink / raw)
  To: linux-arm-kernel, kvmarm, kvm
  Cc: James Morse, Suzuki K Poulose, Alexandru Elisei, kernel-team

When running a KVM guest hosted on an ARMv8.7 machine, the host
kernel complains that it doesn't know about the architected number
of events.

Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 1 +
 arch/arm64/kvm/pmu-emul.c       | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index cdb590840b3f..5de90138d0a4 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1036,6 +1036,7 @@
 #define ID_AA64DFR0_PMUVER_8_1		0x4
 #define ID_AA64DFR0_PMUVER_8_4		0x5
 #define ID_AA64DFR0_PMUVER_8_5		0x6
+#define ID_AA64DFR0_PMUVER_8_7		0x7
 #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
 
 #define ID_AA64DFR0_PMSVER_8_2		0x1
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index a5e4bbf5e68f..ca92cc5c71c6 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
 	case ID_AA64DFR0_PMUVER_8_1:
 	case ID_AA64DFR0_PMUVER_8_4:
 	case ID_AA64DFR0_PMUVER_8_5:
+	case ID_AA64DFR0_PMUVER_8_7:
 		return GENMASK(15, 0);
 	default:		/* Shouldn't be here, just for sanity */
 		WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU
@ 2021-11-26 11:55 ` Marc Zyngier
  0 siblings, 0 replies; 8+ messages in thread
From: Marc Zyngier @ 2021-11-26 11:55 UTC (permalink / raw)
  To: linux-arm-kernel, kvmarm, kvm
  Cc: James Morse, Suzuki K Poulose, Alexandru Elisei, kernel-team

When running a KVM guest hosted on an ARMv8.7 machine, the host
kernel complains that it doesn't know about the architected number
of events.

Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 1 +
 arch/arm64/kvm/pmu-emul.c       | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index cdb590840b3f..5de90138d0a4 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1036,6 +1036,7 @@
 #define ID_AA64DFR0_PMUVER_8_1		0x4
 #define ID_AA64DFR0_PMUVER_8_4		0x5
 #define ID_AA64DFR0_PMUVER_8_5		0x6
+#define ID_AA64DFR0_PMUVER_8_7		0x7
 #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
 
 #define ID_AA64DFR0_PMSVER_8_2		0x1
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index a5e4bbf5e68f..ca92cc5c71c6 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
 	case ID_AA64DFR0_PMUVER_8_1:
 	case ID_AA64DFR0_PMUVER_8_4:
 	case ID_AA64DFR0_PMUVER_8_5:
+	case ID_AA64DFR0_PMUVER_8_7:
 		return GENMASK(15, 0);
 	default:		/* Shouldn't be here, just for sanity */
 		WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU
  2021-11-26 11:55 ` Marc Zyngier
  (?)
@ 2021-11-29 16:59   ` Alexandru Elisei
  -1 siblings, 0 replies; 8+ messages in thread
From: Alexandru Elisei @ 2021-11-29 16:59 UTC (permalink / raw)
  To: Marc Zyngier; +Cc: kvm, kernel-team, kvmarm, linux-arm-kernel

Hi Marc,

Tested on FVP and the nasty splat goes away, so it works for me:

Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>

The guest visible PMCR_EL0.FZ0 bit added by FEAT_PMUv3p7 is cleared on
register reset/write because ARMV8_PMU_PMCR_MASK is 0xff. This makes the
bit behave as RES0, which is the architectural value for the field when
FEAT_PMUv3p7 is absent. So the patch looks correct to me:

Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>

Thanks,
Alex

On Fri, Nov 26, 2021 at 11:55:33AM +0000, Marc Zyngier wrote:
> When running a KVM guest hosted on an ARMv8.7 machine, the host
> kernel complains that it doesn't know about the architected number
> of events.
> 
> Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 1 +
>  arch/arm64/kvm/pmu-emul.c       | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index cdb590840b3f..5de90138d0a4 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -1036,6 +1036,7 @@
>  #define ID_AA64DFR0_PMUVER_8_1		0x4
>  #define ID_AA64DFR0_PMUVER_8_4		0x5
>  #define ID_AA64DFR0_PMUVER_8_5		0x6
> +#define ID_AA64DFR0_PMUVER_8_7		0x7
>  #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
>  
>  #define ID_AA64DFR0_PMSVER_8_2		0x1
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index a5e4bbf5e68f..ca92cc5c71c6 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
>  	case ID_AA64DFR0_PMUVER_8_1:
>  	case ID_AA64DFR0_PMUVER_8_4:
>  	case ID_AA64DFR0_PMUVER_8_5:
> +	case ID_AA64DFR0_PMUVER_8_7:
>  		return GENMASK(15, 0);
>  	default:		/* Shouldn't be here, just for sanity */
>  		WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
> -- 
> 2.30.2
> 
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU
@ 2021-11-29 16:59   ` Alexandru Elisei
  0 siblings, 0 replies; 8+ messages in thread
From: Alexandru Elisei @ 2021-11-29 16:59 UTC (permalink / raw)
  To: Marc Zyngier
  Cc: linux-arm-kernel, kvmarm, kvm, James Morse, Suzuki K Poulose,
	kernel-team

Hi Marc,

Tested on FVP and the nasty splat goes away, so it works for me:

Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>

The guest visible PMCR_EL0.FZ0 bit added by FEAT_PMUv3p7 is cleared on
register reset/write because ARMV8_PMU_PMCR_MASK is 0xff. This makes the
bit behave as RES0, which is the architectural value for the field when
FEAT_PMUv3p7 is absent. So the patch looks correct to me:

Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>

Thanks,
Alex

On Fri, Nov 26, 2021 at 11:55:33AM +0000, Marc Zyngier wrote:
> When running a KVM guest hosted on an ARMv8.7 machine, the host
> kernel complains that it doesn't know about the architected number
> of events.
> 
> Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 1 +
>  arch/arm64/kvm/pmu-emul.c       | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index cdb590840b3f..5de90138d0a4 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -1036,6 +1036,7 @@
>  #define ID_AA64DFR0_PMUVER_8_1		0x4
>  #define ID_AA64DFR0_PMUVER_8_4		0x5
>  #define ID_AA64DFR0_PMUVER_8_5		0x6
> +#define ID_AA64DFR0_PMUVER_8_7		0x7
>  #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
>  
>  #define ID_AA64DFR0_PMSVER_8_2		0x1
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index a5e4bbf5e68f..ca92cc5c71c6 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
>  	case ID_AA64DFR0_PMUVER_8_1:
>  	case ID_AA64DFR0_PMUVER_8_4:
>  	case ID_AA64DFR0_PMUVER_8_5:
> +	case ID_AA64DFR0_PMUVER_8_7:
>  		return GENMASK(15, 0);
>  	default:		/* Shouldn't be here, just for sanity */
>  		WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
> -- 
> 2.30.2
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU
@ 2021-11-29 16:59   ` Alexandru Elisei
  0 siblings, 0 replies; 8+ messages in thread
From: Alexandru Elisei @ 2021-11-29 16:59 UTC (permalink / raw)
  To: Marc Zyngier
  Cc: linux-arm-kernel, kvmarm, kvm, James Morse, Suzuki K Poulose,
	kernel-team

Hi Marc,

Tested on FVP and the nasty splat goes away, so it works for me:

Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>

The guest visible PMCR_EL0.FZ0 bit added by FEAT_PMUv3p7 is cleared on
register reset/write because ARMV8_PMU_PMCR_MASK is 0xff. This makes the
bit behave as RES0, which is the architectural value for the field when
FEAT_PMUv3p7 is absent. So the patch looks correct to me:

Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>

Thanks,
Alex

On Fri, Nov 26, 2021 at 11:55:33AM +0000, Marc Zyngier wrote:
> When running a KVM guest hosted on an ARMv8.7 machine, the host
> kernel complains that it doesn't know about the architected number
> of events.
> 
> Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 1 +
>  arch/arm64/kvm/pmu-emul.c       | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index cdb590840b3f..5de90138d0a4 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -1036,6 +1036,7 @@
>  #define ID_AA64DFR0_PMUVER_8_1		0x4
>  #define ID_AA64DFR0_PMUVER_8_4		0x5
>  #define ID_AA64DFR0_PMUVER_8_5		0x6
> +#define ID_AA64DFR0_PMUVER_8_7		0x7
>  #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
>  
>  #define ID_AA64DFR0_PMSVER_8_2		0x1
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index a5e4bbf5e68f..ca92cc5c71c6 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
>  	case ID_AA64DFR0_PMUVER_8_1:
>  	case ID_AA64DFR0_PMUVER_8_4:
>  	case ID_AA64DFR0_PMUVER_8_5:
> +	case ID_AA64DFR0_PMUVER_8_7:
>  		return GENMASK(15, 0);
>  	default:		/* Shouldn't be here, just for sanity */
>  		WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
> -- 
> 2.30.2
> 

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [irqchip: irq/irqchip-next] KVM: arm64: Add minimal handling for the ARMv8.7 PMU
  2021-11-26 11:55 ` Marc Zyngier
                   ` (2 preceding siblings ...)
  (?)
@ 2021-12-20 14:00 ` irqchip-bot for Marc Zyngier
  2021-12-20 14:04   ` Marc Zyngier
  -1 siblings, 1 reply; 8+ messages in thread
From: irqchip-bot for Marc Zyngier @ 2021-12-20 14:00 UTC (permalink / raw)
  To: linux-kernel; +Cc: Alexandru Elisei, Marc Zyngier, tglx

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     00e228b31596c6bf5f08b5ef76f80cb26e620f02
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/00e228b31596c6bf5f08b5ef76f80cb26e620f02
Author:        Marc Zyngier <maz@kernel.org>
AuthorDate:    Fri, 26 Nov 2021 11:36:43 
Committer:     Marc Zyngier <maz@kernel.org>
CommitterDate: Wed, 01 Dec 2021 13:11:22 

KVM: arm64: Add minimal handling for the ARMv8.7 PMU

When running a KVM guest hosted on an ARMv8.7 machine, the host
kernel complains that it doesn't know about the architected number
of events.

Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.

Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211126115533.217903-1-maz@kernel.org
---
 arch/arm64/include/asm/sysreg.h | 1 +
 arch/arm64/kvm/pmu-emul.c       | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 16b3f1a..615dd62 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -937,6 +937,7 @@
 #define ID_AA64DFR0_PMUVER_8_1		0x4
 #define ID_AA64DFR0_PMUVER_8_4		0x5
 #define ID_AA64DFR0_PMUVER_8_5		0x6
+#define ID_AA64DFR0_PMUVER_8_7		0x7
 #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
 
 #define ID_AA64DFR0_PMSVER_8_2		0x1
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index a5e4bbf..ca92cc5 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
 	case ID_AA64DFR0_PMUVER_8_1:
 	case ID_AA64DFR0_PMUVER_8_4:
 	case ID_AA64DFR0_PMUVER_8_5:
+	case ID_AA64DFR0_PMUVER_8_7:
 		return GENMASK(15, 0);
 	default:		/* Shouldn't be here, just for sanity */
 		WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [irqchip: irq/irqchip-next] KVM: arm64: Add minimal handling for the ARMv8.7 PMU
  2021-12-20 14:00 ` [irqchip: irq/irqchip-next] " irqchip-bot for Marc Zyngier
@ 2021-12-20 14:04   ` Marc Zyngier
  0 siblings, 0 replies; 8+ messages in thread
From: Marc Zyngier @ 2021-12-20 14:04 UTC (permalink / raw)
  To: linux-kernel; +Cc: Alexandru Elisei, tglx, irqchip-bot for Marc Zyngier

On 2021-12-20 14:00, irqchip-bot for Marc Zyngier wrote:
> The following commit has been merged into the irq/irqchip-next branch
> of irqchip:
> 
> Commit-ID:     00e228b31596c6bf5f08b5ef76f80cb26e620f02
> Gitweb:
> https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/00e228b31596c6bf5f08b5ef76f80cb26e620f02
> Author:        Marc Zyngier <maz@kernel.org>
> AuthorDate:    Fri, 26 Nov 2021 11:36:43
> Committer:     Marc Zyngier <maz@kernel.org>
> CommitterDate: Wed, 01 Dec 2021 13:11:22
> 
> KVM: arm64: Add minimal handling for the ARMv8.7 PMU

Dang... I merged the kvm-arm64/misc-5.17 branch in the irqchip tree
instead of the irq/misc-5.17 branch. I guess holidays are in order...

Now fixed.

         M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-12-20 14:05 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-26 11:55 [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU Marc Zyngier
2021-11-26 11:55 ` Marc Zyngier
2021-11-26 11:55 ` Marc Zyngier
2021-11-29 16:59 ` Alexandru Elisei
2021-11-29 16:59   ` Alexandru Elisei
2021-11-29 16:59   ` Alexandru Elisei
2021-12-20 14:00 ` [irqchip: irq/irqchip-next] " irqchip-bot for Marc Zyngier
2021-12-20 14:04   ` Marc Zyngier

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