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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff
Date: Wed,  1 Dec 2021 17:25:41 +0200	[thread overview]
Message-ID: <20211201152552.7821-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20211201152552.7821-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the "sizes are 0 based" stuff with just straight
up -1 where needed. Less confusing all around.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c   | 26 ++++---------------
 .../drm/i915/display/skl_universal_plane.c    |  6 +----
 2 files changed, 6 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 1b99a9501a45..2067a7bca4a8 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -431,10 +431,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
 	u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
 	unsigned long irqflags;
 
-	/* Sizes are 0 based */
-	crtc_w--;
-	crtc_h--;
-
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
@@ -442,7 +438,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
 	intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
 			  (crtc_y << 16) | crtc_x);
 	intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
-			  (crtc_h << 16) | crtc_w);
+			  ((crtc_h - 1) << 16) | (crtc_w - 1));
 
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
@@ -866,21 +862,15 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
 	u32 sprscale = 0;
 	unsigned long irqflags;
 
-	/* Sizes are 0 based */
-	src_w--;
-	src_h--;
-	crtc_w--;
-	crtc_h--;
-
 	if (crtc_w != src_w || crtc_h != src_h)
-		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
+		sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
 			  plane_state->view.color_plane[0].mapping_stride);
 	intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
-	intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
+	intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
 	if (IS_IVYBRIDGE(dev_priv))
 		intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
 
@@ -1208,21 +1198,15 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
 	u32 dvsscale = 0;
 	unsigned long irqflags;
 
-	/* Sizes are 0 based */
-	src_w--;
-	src_h--;
-	crtc_w--;
-	crtc_h--;
-
 	if (crtc_w != src_w || crtc_h != src_h)
-		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
+		dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
 			  plane_state->view.color_plane[0].mapping_stride);
 	intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
-	intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
+	intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
 	intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
 
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 9ff24a0e79b4..09948922016b 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1022,10 +1022,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
 	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 	unsigned long irqflags;
 
-	/* Sizes are 0 based */
-	src_w--;
-	src_h--;
-
 	/* The scaler will handle the output position */
 	if (plane_state->scaler_id >= 0) {
 		crtc_x = 0;
@@ -1045,7 +1041,7 @@ skl_program_plane_noarm(struct intel_plane *plane,
 	intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
 			  (crtc_y << 16) | crtc_x);
 	intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
-			  (src_h << 16) | src_w);
+			  ((src_h - 1) << 16) | (src_w - 1));
 
 	if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
 		intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
-- 
2.32.0


  parent reply	other threads:[~2021-12-01 15:26 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
2021-12-01 15:25 ` [Intel-gfx] [PATCH 01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio Ville Syrjala
2021-12-01 17:13   ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits Ville Syrjala
2021-12-01 17:14   ` Souza, Jose
2021-12-02 11:53     ` Ville Syrjälä
2021-12-06 13:13   ` kernel test robot
2021-12-06 13:13     ` kernel test robot
2021-12-01 15:25 ` Ville Syrjala [this message]
2021-12-01 17:18   ` [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff Souza, Jose
2021-12-02 11:56     ` Ville Syrjälä
2021-12-03 13:40       ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 04/14] drm/i915: Sipmplify PLANE_STRIDE masking Ville Syrjala
2022-01-12 19:50   ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 05/14] drm/i915: Rename PLANE_CUS_CTL Y plane bits Ville Syrjala
2021-12-01 17:17   ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal " Ville Syrjala
2021-12-01 17:26   ` Souza, Jose
2021-12-02 11:57     ` Ville Syrjälä
2022-01-12 19:52       ` Souza, Jose
2021-12-06 15:57   ` kernel test robot
2021-12-06 15:57     ` kernel test robot
2021-12-01 15:25 ` [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
2021-12-06 19:22   ` kernel test robot
2021-12-06 19:22     ` kernel test robot
2022-01-12 20:12   ` Souza, Jose
2022-01-18  0:55     ` Ville Syrjälä
2022-01-18 13:40       ` Souza, Jose
2022-01-18 16:27         ` Ville Syrjälä
2021-12-01 15:25 ` [Intel-gfx] [PATCH 08/14] drm/i915: Clean up ivb+ sprite " Ville Syrjala
2022-01-14 16:26   ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 09/14] drm/i915: Clean up vlv/chv " Ville Syrjala
2022-01-14 16:34   ` Souza, Jose
2022-01-18  1:11     ` Ville Syrjälä
2021-12-01 15:25 ` [Intel-gfx] [PATCH 10/14] drm/i915: Clean up g4x+ " Ville Syrjala
2022-01-14 16:38   ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 11/14] drm/i915: Clean up cursor registers Ville Syrjala
2022-01-14 16:45   ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 12/14] drm/i915: Extract skl_plane_aux_dist() Ville Syrjala
2021-12-01 17:28   ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 13/14] drm/i915: Declutter color key register stuff Ville Syrjala
2021-12-01 17:31   ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 14/14] drm/i915: Nuke pointless middle men for skl+ plane programming Ville Syrjala
2021-12-01 17:32   ` Souza, Jose
2021-12-01 18:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanup Patchwork
2021-12-01 18:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-12-01 19:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-12-02  1:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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