From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits
Date: Wed, 1 Dec 2021 17:14:39 +0000 [thread overview]
Message-ID: <e5d1f9751cc409c608b3b7aa833fbe4f6642fae1.camel@intel.com> (raw)
In-Reply-To: <20211201152552.7821-3-ville.syrjala@linux.intel.com>
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename the YUV byte order bits to be a bit more consistent.
Why rename bits not used? Would be better already nuke it.
Anyways up to you.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 8 ++++----
> drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 845b99844ec6..9ff24a0e79b4 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -672,13 +672,13 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> case DRM_FORMAT_XYUV8888:
> return PLANE_CTL_FORMAT_XYUV;
> case DRM_FORMAT_YUYV:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
> case DRM_FORMAT_YVYU:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
> case DRM_FORMAT_UYVY:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
> case DRM_FORMAT_VYUY:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
> case DRM_FORMAT_NV12:
> return PLANE_CTL_FORMAT_NV12;
> case DRM_FORMAT_P010:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3c0471f20e53..02d8db03c0bf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6966,7 +6966,7 @@ enum {
> #define DVS_SOURCE_KEY (1 << 22)
> #define DVS_RGB_ORDER_XBGR (1 << 20)
> #define DVS_YUV_FORMAT_BT709 (1 << 18)
> -#define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
> +#define DVS_YUV_ORDER_MASK (3 << 16)
> #define DVS_YUV_ORDER_YUYV (0 << 16)
> #define DVS_YUV_ORDER_UYVY (1 << 16)
> #define DVS_YUV_ORDER_YVYU (2 << 16)
> @@ -7045,7 +7045,7 @@ enum {
> #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
> #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
> #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
> -#define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
> +#define SPRITE_YUV_ORDER_MASK (3 << 16)
> #define SPRITE_YUV_ORDER_YUYV (0 << 16)
> #define SPRITE_YUV_ORDER_UYVY (1 << 16)
> #define SPRITE_YUV_ORDER_YVYU (2 << 16)
> @@ -7130,7 +7130,7 @@ enum {
> #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
> #define SP_SOURCE_KEY (1 << 22)
> #define SP_YUV_FORMAT_BT709 (1 << 18)
> -#define SP_YUV_BYTE_ORDER_MASK (3 << 16)
> +#define SP_YUV_ORDER_MASK (3 << 16)
> #define SP_YUV_ORDER_YUYV (0 << 16)
> #define SP_YUV_ORDER_UYVY (1 << 16)
> #define SP_YUV_ORDER_YVYU (2 << 16)
> @@ -7271,10 +7271,10 @@ enum {
> #define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
> #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
> #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
> -#define PLANE_CTL_YUV422_YUYV (0 << 16)
> -#define PLANE_CTL_YUV422_UYVY (1 << 16)
> -#define PLANE_CTL_YUV422_YVYU (2 << 16)
> -#define PLANE_CTL_YUV422_VYUY (3 << 16)
> +#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
> +#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
> +#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
> +#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
> #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
> #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> #define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
next prev parent reply other threads:[~2021-12-01 17:16 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
2021-12-01 15:25 ` [Intel-gfx] [PATCH 01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio Ville Syrjala
2021-12-01 17:13 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits Ville Syrjala
2021-12-01 17:14 ` Souza, Jose [this message]
2021-12-02 11:53 ` Ville Syrjälä
2021-12-06 13:13 ` kernel test robot
2021-12-06 13:13 ` kernel test robot
2021-12-01 15:25 ` [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff Ville Syrjala
2021-12-01 17:18 ` Souza, Jose
2021-12-02 11:56 ` Ville Syrjälä
2021-12-03 13:40 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 04/14] drm/i915: Sipmplify PLANE_STRIDE masking Ville Syrjala
2022-01-12 19:50 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 05/14] drm/i915: Rename PLANE_CUS_CTL Y plane bits Ville Syrjala
2021-12-01 17:17 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal " Ville Syrjala
2021-12-01 17:26 ` Souza, Jose
2021-12-02 11:57 ` Ville Syrjälä
2022-01-12 19:52 ` Souza, Jose
2021-12-06 15:57 ` kernel test robot
2021-12-06 15:57 ` kernel test robot
2021-12-01 15:25 ` [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
2021-12-06 19:22 ` kernel test robot
2021-12-06 19:22 ` kernel test robot
2022-01-12 20:12 ` Souza, Jose
2022-01-18 0:55 ` Ville Syrjälä
2022-01-18 13:40 ` Souza, Jose
2022-01-18 16:27 ` Ville Syrjälä
2021-12-01 15:25 ` [Intel-gfx] [PATCH 08/14] drm/i915: Clean up ivb+ sprite " Ville Syrjala
2022-01-14 16:26 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 09/14] drm/i915: Clean up vlv/chv " Ville Syrjala
2022-01-14 16:34 ` Souza, Jose
2022-01-18 1:11 ` Ville Syrjälä
2021-12-01 15:25 ` [Intel-gfx] [PATCH 10/14] drm/i915: Clean up g4x+ " Ville Syrjala
2022-01-14 16:38 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 11/14] drm/i915: Clean up cursor registers Ville Syrjala
2022-01-14 16:45 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 12/14] drm/i915: Extract skl_plane_aux_dist() Ville Syrjala
2021-12-01 17:28 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 13/14] drm/i915: Declutter color key register stuff Ville Syrjala
2021-12-01 17:31 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 14/14] drm/i915: Nuke pointless middle men for skl+ plane programming Ville Syrjala
2021-12-01 17:32 ` Souza, Jose
2021-12-01 18:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanup Patchwork
2021-12-01 18:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-12-01 19:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-12-02 1:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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