* [PATCH 01/10] target/ppc: Merge 7x5 and 7x0 exception model IDs
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
@ 2022-02-03 22:42 ` Fabiano Rosas
2022-02-03 22:42 ` [PATCH 02/10] target/ppc: Introduce powerpc_excp_7xx Fabiano Rosas
` (9 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-03 22:42 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Since we've split the exception code by exception model, the exception
model IDs are becoming less useful. These two can be merged.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/cpu-qom.h | 6 ++----
target/ppc/cpu_init.c | 16 ++++++++--------
target/ppc/excp_helper.c | 2 +-
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 3880fb3337..98facee9fa 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -90,10 +90,8 @@ enum powerpc_excp_t {
POWERPC_EXCP_40x,
/* PowerPC 603/604/G2 exception model */
POWERPC_EXCP_6xx,
- /* PowerPC 7x0 exception model */
- POWERPC_EXCP_7x0,
- /* PowerPC 7x5 exception model */
- POWERPC_EXCP_7x5,
+ /* PowerPC 7xx exception model */
+ POWERPC_EXCP_7xx,
/* PowerPC 74xx exception model */
POWERPC_EXCP_74xx,
/* BookE exception model */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 95c5831ba6..d97f718354 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -4021,7 +4021,7 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_32B;
- pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->excp_model = POWERPC_EXCP_7xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
@@ -4098,7 +4098,7 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_32B;
- pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->excp_model = POWERPC_EXCP_7xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
@@ -4298,7 +4298,7 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_32B;
- pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->excp_model = POWERPC_EXCP_7xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
@@ -4378,7 +4378,7 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_32B;
- pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->excp_model = POWERPC_EXCP_7xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
@@ -4463,7 +4463,7 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_32B;
- pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->excp_model = POWERPC_EXCP_7xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
@@ -4548,7 +4548,7 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_32B;
- pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->excp_model = POWERPC_EXCP_7xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
@@ -4624,7 +4624,7 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_7x5;
+ pcc->excp_model = POWERPC_EXCP_7xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
@@ -4711,7 +4711,7 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_7x5;
+ pcc->excp_model = POWERPC_EXCP_7xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 7bdda6f165..b6a5c36fd2 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1844,7 +1844,7 @@ static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp)
hreg_swap_gpr_tgpr(env);
}
/* fall through */
- case POWERPC_EXCP_7x5:
+ case POWERPC_EXCP_7xx:
ppc_excp_debug_sw_tlb(env, excp);
msr |= env->crf[0] << 28;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 02/10] target/ppc: Introduce powerpc_excp_7xx
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
2022-02-03 22:42 ` [PATCH 01/10] target/ppc: Merge 7x5 and 7x0 exception model IDs Fabiano Rosas
@ 2022-02-03 22:42 ` Fabiano Rosas
2022-02-03 22:42 ` [PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx Fabiano Rosas
` (8 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-03 22:42 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Introduce a new powerpc_excp function specific for PowerPC 7xx CPUs
(740, 745, 750, 750cl, 750cx, 750fx, 750gx, 755). This commit copies
powerpc_excp_legacy verbatim so the next one has a clean diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 469 +++++++++++++++++++++++++++++++++++++++
1 file changed, 469 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index b6a5c36fd2..df96f620b2 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -741,6 +741,472 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
powerpc_set_excp_state(cpu, vector, new_msr);
}
+static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
+{
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ int excp_model = env->excp_model;
+ target_ulong msr, new_msr, vector;
+ int srr0, srr1, lev = -1;
+
+ if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ }
+
+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
+ " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
+ excp, env->error_code);
+
+ /* new srr1 value excluding must-be-zero bits */
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ msr = env->msr;
+ } else {
+ msr = env->msr & ~0x783f0000ULL;
+ }
+
+ /*
+ * new interrupt handler msr preserves existing HV and ME unless
+ * explicitly overriden
+ */
+ new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+
+ /* target registers */
+ srr0 = SPR_SRR0;
+ srr1 = SPR_SRR1;
+
+ /*
+ * check for special resume at 0x100 from doze/nap/sleep/winkle on
+ * P7/P8/P9
+ */
+ if (env->resume_as_sreset) {
+ excp = powerpc_reset_wakeup(cs, env, excp, &msr);
+ }
+
+ /*
+ * Hypervisor emulation assistance interrupt only exists on server
+ * arch 2.05 server or later. We also don't want to generate it if
+ * we don't have HVB in msr_mask (PAPR mode).
+ */
+ if (excp == POWERPC_EXCP_HV_EMU
+#if defined(TARGET_PPC64)
+ && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
+#endif /* defined(TARGET_PPC64) */
+
+ ) {
+ excp = POWERPC_EXCP_PROGRAM;
+ }
+
+#ifdef TARGET_PPC64
+ /*
+ * SPEU and VPU share the same IVOR but they exist in different
+ * processors. SPEU is e500v1/2 only and VPU is e6500 only.
+ */
+ if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
+ excp = POWERPC_EXCP_SPEU;
+ }
+#endif
+
+ vector = env->excp_vectors[excp];
+ if (vector == (target_ulong)-1ULL) {
+ cpu_abort(cs, "Raised an exception without defined vector %d\n",
+ excp);
+ }
+
+ vector |= env->excp_prefix;
+
+ switch (excp) {
+ case POWERPC_EXCP_CRITICAL: /* Critical input */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_6xx:
+ break;
+ default:
+ goto excp_invalid;
+ }
+ break;
+ case POWERPC_EXCP_MCHECK: /* Machine check exception */
+ if (msr_me == 0) {
+ /*
+ * Machine check exception is not enabled. Enter
+ * checkstop state.
+ */
+ fprintf(stderr, "Machine check while not allowed. "
+ "Entering checkstop state\n");
+ if (qemu_log_separate()) {
+ qemu_log("Machine check while not allowed. "
+ "Entering checkstop state\n");
+ }
+ cs->halted = 1;
+ cpu_interrupt_exittb(cs);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+
+ /* machine check exceptions don't have ME set */
+ new_msr &= ~((target_ulong)1 << MSR_ME);
+
+ /* XXX: should also have something loaded in DAR / DSISR */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_MCSRR0;
+ srr1 = SPR_BOOKE_MCSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DSI: /* Data storage exception */
+ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ break;
+ case POWERPC_EXCP_ISI: /* Instruction storage exception */
+ trace_ppc_excp_isi(msr, env->nip);
+ msr |= env->error_code;
+ break;
+ case POWERPC_EXCP_EXTERNAL: /* External input */
+ {
+ bool lpes0;
+
+ cs = CPU(cpu);
+
+ /*
+ * Exception targeting modifiers
+ *
+ * LPES0 is supported on POWER7/8/9
+ * LPES1 is not supported (old iSeries mode)
+ *
+ * On anything else, we behave as if LPES0 is 1
+ * (externals don't alter MSR:HV)
+ */
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_POWER7 ||
+ excp_model == POWERPC_EXCP_POWER8 ||
+ excp_model == POWERPC_EXCP_POWER9 ||
+ excp_model == POWERPC_EXCP_POWER10) {
+ lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+ } else
+#endif /* defined(TARGET_PPC64) */
+ {
+ lpes0 = true;
+ }
+
+ if (!lpes0) {
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ }
+ if (env->mpic_proxy) {
+ /* IACK the IRQ on delivery */
+ env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
+ }
+ break;
+ }
+ case POWERPC_EXCP_ALIGN: /* Alignment exception */
+ /* Get rS/rD and rA from faulting opcode */
+ /*
+ * Note: the opcode fields will not be set properly for a
+ * direct store load/store, but nobody cares as nobody
+ * actually uses direct store segments.
+ */
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ break;
+ case POWERPC_EXCP_PROGRAM: /* Program exception */
+ switch (env->error_code & ~0xF) {
+ case POWERPC_EXCP_FP:
+ if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ trace_ppc_excp_fp_ignore();
+ cs->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+ return;
+ }
+
+ /*
+ * FP exceptions always have NIP pointing to the faulting
+ * instruction, so always use store_next and claim we are
+ * precise in the MSR.
+ */
+ msr |= 0x00100000;
+ env->spr[SPR_BOOKE_ESR] = ESR_FP;
+ break;
+ case POWERPC_EXCP_INVAL:
+ trace_ppc_excp_inval(env->nip);
+ msr |= 0x00080000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PIL;
+ break;
+ case POWERPC_EXCP_PRIV:
+ msr |= 0x00040000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PPR;
+ break;
+ case POWERPC_EXCP_TRAP:
+ msr |= 0x00020000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PTR;
+ break;
+ default:
+ /* Should never occur */
+ cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ env->error_code);
+ break;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL: /* System call exception */
+ lev = env->error_code;
+
+ if ((lev == 1) && cpu->vhyp) {
+ dump_hcall(env);
+ } else {
+ dump_syscall(env);
+ }
+
+ /*
+ * We need to correct the NIP which in this case is supposed
+ * to point to the next instruction
+ */
+ env->nip += 4;
+
+ /* "PAPR mode" built-in hypercall emulation */
+ if ((lev == 1) && cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->hypercall(cpu->vhyp, cpu);
+ return;
+ }
+ if (lev == 1) {
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
+ lev = env->error_code;
+ dump_syscall(env);
+ env->nip += 4;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+
+ vector += lev * 0x20;
+
+ env->lr = env->nip;
+ env->ctr = msr;
+ break;
+ case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
+ case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
+ case POWERPC_EXCP_DECR: /* Decrementer exception */
+ break;
+ case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
+ /* FIT on 4xx */
+ trace_ppc_excp_print("FIT");
+ break;
+ case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
+ trace_ppc_excp_print("WDT");
+ switch (excp_model) {
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DTLB: /* Data TLB error */
+ case POWERPC_EXCP_ITLB: /* Instruction TLB error */
+ break;
+ case POWERPC_EXCP_DEBUG: /* Debug interrupt */
+ if (env->flags & POWERPC_FLAG_DE) {
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_DSRR0;
+ srr1 = SPR_BOOKE_DSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+
+ /* DBSR already modified by caller */
+ } else {
+ cpu_abort(cs, "Debug exception triggered on unsupported model\n");
+ }
+ break;
+ case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
+ env->spr[SPR_BOOKE_ESR] = ESR_SPV;
+ break;
+ case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
+ break;
+ case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_RESET: /* System reset exception */
+ /* A power-saving exception sets ME, otherwise it is unchanged */
+ if (msr_pow) {
+ /* indicate that we resumed from power save mode */
+ msr |= 0x10000;
+ new_msr |= ((target_ulong)1 << MSR_ME);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ } else {
+ if (msr_pow) {
+ cpu_abort(cs, "Trying to deliver power-saving system reset "
+ "exception %d with no HV support\n", excp);
+ }
+ }
+ break;
+ case POWERPC_EXCP_DSEG: /* Data segment exception */
+ case POWERPC_EXCP_ISEG: /* Instruction segment exception */
+ case POWERPC_EXCP_TRACE: /* Trace exception */
+ break;
+ case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
+ msr |= env->error_code;
+ /* fall through */
+ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
+ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
+ case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
+ case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
+ case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
+ case POWERPC_EXCP_HV_EMU:
+ case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ break;
+ case POWERPC_EXCP_VPU: /* Vector unavailable exception */
+ case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
+ case POWERPC_EXCP_FU: /* Facility unavailable exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
+#endif
+ break;
+ case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+#endif
+ break;
+ case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
+ trace_ppc_excp_print("PIT");
+ break;
+ case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
+ case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
+ case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
+ switch (excp_model) {
+ case POWERPC_EXCP_6xx:
+ /* Swap temporary saved registers with GPRs */
+ if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
+ new_msr |= (target_ulong)1 << MSR_TGPR;
+ hreg_swap_gpr_tgpr(env);
+ }
+ /* fall through */
+ case POWERPC_EXCP_7xx:
+ ppc_excp_debug_sw_tlb(env, excp);
+
+ msr |= env->crf[0] << 28;
+ msr |= env->error_code; /* key, D/I, S/L bits */
+ /* Set way using a LRU mechanism */
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
+ break;
+ default:
+ cpu_abort(cs, "Invalid TLB miss exception\n");
+ break;
+ }
+ break;
+ case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
+ case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
+ case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_FPA: /* Floating-point assist exception */
+ case POWERPC_EXCP_DABR: /* Data address breakpoint */
+ case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
+ case POWERPC_EXCP_SMI: /* System management interrupt */
+ case POWERPC_EXCP_THERM: /* Thermal interrupt */
+ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_VPUA: /* Vector assist exception */
+ case POWERPC_EXCP_SOFTP: /* Soft patch exception */
+ case POWERPC_EXCP_MAINT: /* Maintenance exception */
+ case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
+ case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
+ cpu_abort(cs, "%s exception not implemented\n",
+ powerpc_excp_name(excp));
+ break;
+ default:
+ excp_invalid:
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ break;
+ }
+
+ /* Sanity check */
+ if (!(env->msr_mask & MSR_HVB)) {
+ if (new_msr & MSR_HVB) {
+ cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
+ "no HV support\n", excp);
+ }
+ if (srr0 == SPR_HSRR0) {
+ cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
+ "no HV support\n", excp);
+ }
+ }
+
+ /*
+ * Sort out endianness of interrupt, this differs depending on the
+ * CPU, the HV mode, etc...
+ */
+ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
+ new_msr |= (target_ulong)1 << MSR_LE;
+ }
+
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
+ /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
+ new_msr |= (target_ulong)1 << MSR_CM;
+ } else {
+ vector = (uint32_t)vector;
+ }
+ } else {
+ if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
+ vector = (uint32_t)vector;
+ } else {
+ new_msr |= (target_ulong)1 << MSR_SF;
+ }
+ }
+#endif
+
+ if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
+ /* Save PC */
+ env->spr[srr0] = env->nip;
+
+ /* Save MSR */
+ env->spr[srr1] = msr;
+ }
+
+ /* This can update new_msr and vector if AIL applies */
+ ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+
+ powerpc_set_excp_state(cpu, vector, new_msr);
+}
+
static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
@@ -1942,6 +2408,9 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_6xx:
powerpc_excp_6xx(cpu, excp);
break;
+ case POWERPC_EXCP_7xx:
+ powerpc_excp_7xx(cpu, excp);
+ break;
case POWERPC_EXCP_74xx:
powerpc_excp_74xx(cpu, excp);
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
2022-02-03 22:42 ` [PATCH 01/10] target/ppc: Merge 7x5 and 7x0 exception model IDs Fabiano Rosas
2022-02-03 22:42 ` [PATCH 02/10] target/ppc: Introduce powerpc_excp_7xx Fabiano Rosas
@ 2022-02-03 22:42 ` Fabiano Rosas
2022-02-04 13:05 ` BALATON Zoltan
2022-02-03 22:42 ` [PATCH 04/10] target/ppc: 7xx: Machine Check exception cleanup Fabiano Rosas
` (7 subsequent siblings)
10 siblings, 1 reply; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-03 22:42 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Alternate Interrupt Location.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_DECR
POWERPC_EXCP_DLTLB
POWERPC_EXCP_DSI
POWERPC_EXCP_DSTLB
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FPU
POWERPC_EXCP_IABR
POWERPC_EXCP_IFTLB
POWERPC_EXCP_ISI
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PERFM
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SMI
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_THERM
POWERPC_EXCP_TRACE
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 185 ++-------------------------------------
1 file changed, 9 insertions(+), 176 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index df96f620b2..358c3f6206 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -758,54 +758,26 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
excp, env->error_code);
/* new srr1 value excluding must-be-zero bits */
- if (excp_model == POWERPC_EXCP_BOOKE) {
- msr = env->msr;
- } else {
- msr = env->msr & ~0x783f0000ULL;
- }
+ msr = env->msr & ~0x783f0000ULL;
/*
- * new interrupt handler msr preserves existing HV and ME unless
+ * new interrupt handler msr preserves existing ME unless
* explicitly overriden
*/
- new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+ new_msr = env->msr & ((target_ulong)1 << MSR_ME);
/* target registers */
srr0 = SPR_SRR0;
srr1 = SPR_SRR1;
- /*
- * check for special resume at 0x100 from doze/nap/sleep/winkle on
- * P7/P8/P9
- */
- if (env->resume_as_sreset) {
- excp = powerpc_reset_wakeup(cs, env, excp, &msr);
- }
-
/*
* Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later. We also don't want to generate it if
- * we don't have HVB in msr_mask (PAPR mode).
+ * arch 2.05 server or later.
*/
- if (excp == POWERPC_EXCP_HV_EMU
-#if defined(TARGET_PPC64)
- && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
-#endif /* defined(TARGET_PPC64) */
-
- ) {
+ if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
-#ifdef TARGET_PPC64
- /*
- * SPEU and VPU share the same IVOR but they exist in different
- * processors. SPEU is e500v1/2 only and VPU is e6500 only.
- */
- if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
- excp = POWERPC_EXCP_SPEU;
- }
-#endif
-
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
cpu_abort(cs, "Raised an exception without defined vector %d\n",
@@ -815,22 +787,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
vector |= env->excp_prefix;
switch (excp) {
- case POWERPC_EXCP_CRITICAL: /* Critical input */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- case POWERPC_EXCP_6xx:
- break;
- default:
- goto excp_invalid;
- }
- break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
if (msr_me == 0) {
/*
@@ -994,63 +950,9 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)MSR_HVB;
}
break;
- case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
- lev = env->error_code;
- dump_syscall(env);
- env->nip += 4;
- new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-
- vector += lev * 0x20;
-
- env->lr = env->nip;
- env->ctr = msr;
- break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
- case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
case POWERPC_EXCP_DECR: /* Decrementer exception */
break;
- case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
- /* FIT on 4xx */
- trace_ppc_excp_print("FIT");
- break;
- case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
- trace_ppc_excp_print("WDT");
- switch (excp_model) {
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- default:
- break;
- }
- break;
- case POWERPC_EXCP_DTLB: /* Data TLB error */
- case POWERPC_EXCP_ITLB: /* Instruction TLB error */
- break;
- case POWERPC_EXCP_DEBUG: /* Debug interrupt */
- if (env->flags & POWERPC_FLAG_DE) {
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_DSRR0;
- srr1 = SPR_BOOKE_DSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
-
- /* DBSR already modified by caller */
- } else {
- cpu_abort(cs, "Debug exception triggered on unsupported model\n");
- }
- break;
- case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
- env->spr[SPR_BOOKE_ESR] = ESR_SPV;
- break;
- case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
- break;
- case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
case POWERPC_EXCP_RESET: /* System reset exception */
/* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
@@ -1071,44 +973,8 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
}
}
break;
- case POWERPC_EXCP_DSEG: /* Data segment exception */
- case POWERPC_EXCP_ISEG: /* Instruction segment exception */
case POWERPC_EXCP_TRACE: /* Trace exception */
break;
- case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
- msr |= env->error_code;
- /* fall through */
- case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
- case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
- case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
- case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
- case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
- case POWERPC_EXCP_HV_EMU:
- case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- break;
- case POWERPC_EXCP_VPU: /* Vector unavailable exception */
- case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
- case POWERPC_EXCP_FU: /* Facility unavailable exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
-#endif
- break;
- case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-#endif
- break;
- case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
- trace_ppc_excp_print("PIT");
- break;
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
@@ -1133,25 +999,14 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
break;
}
break;
- case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
- case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
- case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_FPA: /* Floating-point assist exception */
- case POWERPC_EXCP_DABR: /* Data address breakpoint */
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
case POWERPC_EXCP_SMI: /* System management interrupt */
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_VPUA: /* Vector assist exception */
- case POWERPC_EXCP_SOFTP: /* Soft patch exception */
- case POWERPC_EXCP_MAINT: /* Maintenance exception */
- case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
- case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
cpu_abort(cs, "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- excp_invalid:
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
break;
}
@@ -1176,33 +1031,11 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)1 << MSR_LE;
}
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_BOOKE) {
- if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
- /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
- new_msr |= (target_ulong)1 << MSR_CM;
- } else {
- vector = (uint32_t)vector;
- }
- } else {
- if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
- vector = (uint32_t)vector;
- } else {
- new_msr |= (target_ulong)1 << MSR_SF;
- }
- }
-#endif
+ /* Save PC */
+ env->spr[srr0] = env->nip;
- if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
- /* Save PC */
- env->spr[srr0] = env->nip;
-
- /* Save MSR */
- env->spr[srr1] = msr;
- }
-
- /* This can update new_msr and vector if AIL applies */
- ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+ /* Save MSR */
+ env->spr[srr1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx
2022-02-03 22:42 ` [PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx Fabiano Rosas
@ 2022-02-04 13:05 ` BALATON Zoltan
2022-02-04 16:10 ` Fabiano Rosas
0 siblings, 1 reply; 16+ messages in thread
From: BALATON Zoltan @ 2022-02-04 13:05 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, david, clg
On Thu, 3 Feb 2022, Fabiano Rosas wrote:
> Differences from the generic powerpc_excp code:
>
> - Not BookE, so some MSR bits are cleared at interrupt dispatch;
> - No MSR_HV;
> - No power saving states;
> - No Hypervisor Emulation Assistance;
The pegasos2 can run with -cpu G3 as the real hardware had a processor
card either with a G3 or a G4 so this will break VOF with that. I'm not
sure if it's worth keeping support for this though as long as the default
G4 works because most people would want to use a G4 anyway and those who
want a G3 for some reason could still use a firmware rom image instead but
I wonder if there's another better place where sc 1 could be handled so it
could work for these cpus without needing to change these excp helpers.
Regards,
BALATON Zoltan
> - Not 64 bits;
> - No System call vectored;
> - No Alternate Interrupt Location.
>
> Exceptions used:
>
> POWERPC_EXCP_ALIGN
> POWERPC_EXCP_DECR
> POWERPC_EXCP_DLTLB
> POWERPC_EXCP_DSI
> POWERPC_EXCP_DSTLB
> POWERPC_EXCP_EXTERNAL
> POWERPC_EXCP_FPU
> POWERPC_EXCP_IABR
> POWERPC_EXCP_IFTLB
> POWERPC_EXCP_ISI
> POWERPC_EXCP_MCHECK
> POWERPC_EXCP_PERFM
> POWERPC_EXCP_PROGRAM
> POWERPC_EXCP_RESET
> POWERPC_EXCP_SMI
> POWERPC_EXCP_SYSCALL
> POWERPC_EXCP_THERM
> POWERPC_EXCP_TRACE
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 185 ++-------------------------------------
> 1 file changed, 9 insertions(+), 176 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index df96f620b2..358c3f6206 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -758,54 +758,26 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
> excp, env->error_code);
>
> /* new srr1 value excluding must-be-zero bits */
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - msr = env->msr;
> - } else {
> - msr = env->msr & ~0x783f0000ULL;
> - }
> + msr = env->msr & ~0x783f0000ULL;
>
> /*
> - * new interrupt handler msr preserves existing HV and ME unless
> + * new interrupt handler msr preserves existing ME unless
> * explicitly overriden
> */
> - new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
> + new_msr = env->msr & ((target_ulong)1 << MSR_ME);
>
> /* target registers */
> srr0 = SPR_SRR0;
> srr1 = SPR_SRR1;
>
> - /*
> - * check for special resume at 0x100 from doze/nap/sleep/winkle on
> - * P7/P8/P9
> - */
> - if (env->resume_as_sreset) {
> - excp = powerpc_reset_wakeup(cs, env, excp, &msr);
> - }
> -
> /*
> * Hypervisor emulation assistance interrupt only exists on server
> - * arch 2.05 server or later. We also don't want to generate it if
> - * we don't have HVB in msr_mask (PAPR mode).
> + * arch 2.05 server or later.
> */
> - if (excp == POWERPC_EXCP_HV_EMU
> -#if defined(TARGET_PPC64)
> - && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
> -#endif /* defined(TARGET_PPC64) */
> -
> - ) {
> + if (excp == POWERPC_EXCP_HV_EMU) {
> excp = POWERPC_EXCP_PROGRAM;
> }
>
> -#ifdef TARGET_PPC64
> - /*
> - * SPEU and VPU share the same IVOR but they exist in different
> - * processors. SPEU is e500v1/2 only and VPU is e6500 only.
> - */
> - if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
> - excp = POWERPC_EXCP_SPEU;
> - }
> -#endif
> -
> vector = env->excp_vectors[excp];
> if (vector == (target_ulong)-1ULL) {
> cpu_abort(cs, "Raised an exception without defined vector %d\n",
> @@ -815,22 +787,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
> vector |= env->excp_prefix;
>
> switch (excp) {
> - case POWERPC_EXCP_CRITICAL: /* Critical input */
> - switch (excp_model) {
> - case POWERPC_EXCP_40x:
> - srr0 = SPR_40x_SRR2;
> - srr1 = SPR_40x_SRR3;
> - break;
> - case POWERPC_EXCP_BOOKE:
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - case POWERPC_EXCP_6xx:
> - break;
> - default:
> - goto excp_invalid;
> - }
> - break;
> case POWERPC_EXCP_MCHECK: /* Machine check exception */
> if (msr_me == 0) {
> /*
> @@ -994,63 +950,9 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
> new_msr |= (target_ulong)MSR_HVB;
> }
> break;
> - case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
> - lev = env->error_code;
> - dump_syscall(env);
> - env->nip += 4;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -
> - vector += lev * 0x20;
> -
> - env->lr = env->nip;
> - env->ctr = msr;
> - break;
> case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
> - case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
> case POWERPC_EXCP_DECR: /* Decrementer exception */
> break;
> - case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
> - /* FIT on 4xx */
> - trace_ppc_excp_print("FIT");
> - break;
> - case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
> - trace_ppc_excp_print("WDT");
> - switch (excp_model) {
> - case POWERPC_EXCP_BOOKE:
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - default:
> - break;
> - }
> - break;
> - case POWERPC_EXCP_DTLB: /* Data TLB error */
> - case POWERPC_EXCP_ITLB: /* Instruction TLB error */
> - break;
> - case POWERPC_EXCP_DEBUG: /* Debug interrupt */
> - if (env->flags & POWERPC_FLAG_DE) {
> - /* FIXME: choose one or the other based on CPU type */
> - srr0 = SPR_BOOKE_DSRR0;
> - srr1 = SPR_BOOKE_DSRR1;
> -
> - env->spr[SPR_BOOKE_CSRR0] = env->nip;
> - env->spr[SPR_BOOKE_CSRR1] = msr;
> -
> - /* DBSR already modified by caller */
> - } else {
> - cpu_abort(cs, "Debug exception triggered on unsupported model\n");
> - }
> - break;
> - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
> - env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> - break;
> - case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
> - break;
> - case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> case POWERPC_EXCP_RESET: /* System reset exception */
> /* A power-saving exception sets ME, otherwise it is unchanged */
> if (msr_pow) {
> @@ -1071,44 +973,8 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
> }
> }
> break;
> - case POWERPC_EXCP_DSEG: /* Data segment exception */
> - case POWERPC_EXCP_ISEG: /* Instruction segment exception */
> case POWERPC_EXCP_TRACE: /* Trace exception */
> break;
> - case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
> - msr |= env->error_code;
> - /* fall through */
> - case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
> - case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
> - case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
> - case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
> - case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
> - case POWERPC_EXCP_HV_EMU:
> - case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> - break;
> - case POWERPC_EXCP_VPU: /* Vector unavailable exception */
> - case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
> - case POWERPC_EXCP_FU: /* Facility unavailable exception */
> -#ifdef TARGET_PPC64
> - env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
> -#endif
> - break;
> - case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
> -#ifdef TARGET_PPC64
> - env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -#endif
> - break;
> - case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
> - trace_ppc_excp_print("PIT");
> - break;
> case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
> case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
> case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
> @@ -1133,25 +999,14 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
> break;
> }
> break;
> - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
> - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
> - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
> - case POWERPC_EXCP_FPA: /* Floating-point assist exception */
> - case POWERPC_EXCP_DABR: /* Data address breakpoint */
> case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
> case POWERPC_EXCP_SMI: /* System management interrupt */
> case POWERPC_EXCP_THERM: /* Thermal interrupt */
> case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
> - case POWERPC_EXCP_VPUA: /* Vector assist exception */
> - case POWERPC_EXCP_SOFTP: /* Soft patch exception */
> - case POWERPC_EXCP_MAINT: /* Maintenance exception */
> - case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
> - case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
> cpu_abort(cs, "%s exception not implemented\n",
> powerpc_excp_name(excp));
> break;
> default:
> - excp_invalid:
> cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> break;
> }
> @@ -1176,33 +1031,11 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
> new_msr |= (target_ulong)1 << MSR_LE;
> }
>
> -#if defined(TARGET_PPC64)
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
> - /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
> - new_msr |= (target_ulong)1 << MSR_CM;
> - } else {
> - vector = (uint32_t)vector;
> - }
> - } else {
> - if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
> - vector = (uint32_t)vector;
> - } else {
> - new_msr |= (target_ulong)1 << MSR_SF;
> - }
> - }
> -#endif
> + /* Save PC */
> + env->spr[srr0] = env->nip;
>
> - if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
> - /* Save PC */
> - env->spr[srr0] = env->nip;
> -
> - /* Save MSR */
> - env->spr[srr1] = msr;
> - }
> -
> - /* This can update new_msr and vector if AIL applies */
> - ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
> + /* Save MSR */
> + env->spr[srr1] = msr;
>
> powerpc_set_excp_state(cpu, vector, new_msr);
> }
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx
2022-02-04 13:05 ` BALATON Zoltan
@ 2022-02-04 16:10 ` Fabiano Rosas
2022-02-04 16:42 ` BALATON Zoltan
0 siblings, 1 reply; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-04 16:10 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: clg, danielhb413, qemu-ppc, qemu-devel, david
BALATON Zoltan <balaton@eik.bme.hu> writes:
> On Thu, 3 Feb 2022, Fabiano Rosas wrote:
>> Differences from the generic powerpc_excp code:
>>
>> - Not BookE, so some MSR bits are cleared at interrupt dispatch;
>> - No MSR_HV;
>> - No power saving states;
>> - No Hypervisor Emulation Assistance;
>
> The pegasos2 can run with -cpu G3 as the real hardware had a processor
> card either with a G3 or a G4 so this will break VOF with that. I'm not
> sure if it's worth keeping support for this though as long as the default
> G4 works because most people would want to use a G4 anyway and those who
> want a G3 for some reason could still use a firmware rom image instead but
I'll bring 'sc 1' back then. I shouldn't mix the refactoring with
dropping support of things.
If you think we can drop support for the pegasos2 on the G3 let me know
and I'll send a follow up patch. Or you can send one yourself if you'd
like.
> I wonder if there's another better place where sc 1 could be handled so it
> could work for these cpus without needing to change these excp helpers.
I spoke to Alexey and the way forward here is to have a MMIO address for
VOF to use and remove the sc 1 usage altogether. At least for the CPUs
that wouldn't support it otherwise. I created a GitLab issue to track
that: https://gitlab.com/qemu-project/qemu/-/issues/859
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx
2022-02-04 16:10 ` Fabiano Rosas
@ 2022-02-04 16:42 ` BALATON Zoltan
0 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2022-02-04 16:42 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, clg, david, qemu-devel
On Fri, 4 Feb 2022, Fabiano Rosas wrote:
> BALATON Zoltan <balaton@eik.bme.hu> writes:
>> On Thu, 3 Feb 2022, Fabiano Rosas wrote:
>>> Differences from the generic powerpc_excp code:
>>>
>>> - Not BookE, so some MSR bits are cleared at interrupt dispatch;
>>> - No MSR_HV;
>>> - No power saving states;
>>> - No Hypervisor Emulation Assistance;
>>
>> The pegasos2 can run with -cpu G3 as the real hardware had a processor
>> card either with a G3 or a G4 so this will break VOF with that. I'm not
>> sure if it's worth keeping support for this though as long as the default
>> G4 works because most people would want to use a G4 anyway and those who
>> want a G3 for some reason could still use a firmware rom image instead but
>
> I'll bring 'sc 1' back then. I shouldn't mix the refactoring with
> dropping support of things.
>
> If you think we can drop support for the pegasos2 on the G3 let me know
> and I'll send a follow up patch. Or you can send one yourself if you'd
> like.
I think the G3 is probably rarely used on pegasos2, G4 being the default
and preferred CPU so maybe only needed if somebody wants to test something
specifically with G3. That's why I said this is not critical, because
using a firmware rom image would still boot with -cpu G3 if sc 1 is
removed for G3 and older. We've made sure it still works with G4 so that's
fine. However leaving this around for now to keep previous behaviour until
VOF is changed to support a different hypercall method is nice to have if
it's not much trouble for you so I'm OK with any decision on this.
Regards,
BALATON Zoltan
>> I wonder if there's another better place where sc 1 could be handled so it
>> could work for these cpus without needing to change these excp helpers.
>
> I spoke to Alexey and the way forward here is to have a MMIO address for
> VOF to use and remove the sc 1 usage altogether. At least for the CPUs
> that wouldn't support it otherwise. I created a GitLab issue to track
> that: https://gitlab.com/qemu-project/qemu/-/issues/859
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 04/10] target/ppc: 7xx: Machine Check exception cleanup
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
` (2 preceding siblings ...)
2022-02-03 22:42 ` [PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx Fabiano Rosas
@ 2022-02-03 22:42 ` Fabiano Rosas
2022-02-03 22:42 ` [PATCH 05/10] target/ppc: 7xx: External interrupt cleanup Fabiano Rosas
` (6 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-03 22:42 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There's no MSR_HV in the 7xx.
Also remove 40x and BookE code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 358c3f6206..4996b96616 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -802,34 +802,10 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
cs->halted = 1;
cpu_interrupt_exittb(cs);
}
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR).
- */
- new_msr |= (target_ulong)MSR_HVB;
- }
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
- /* XXX: should also have something loaded in DAR / DSISR */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_MCSRR0;
- srr1 = SPR_BOOKE_MCSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
- break;
- default:
- break;
- }
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 05/10] target/ppc: 7xx: External interrupt cleanup
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
` (3 preceding siblings ...)
2022-02-03 22:42 ` [PATCH 04/10] target/ppc: 7xx: Machine Check exception cleanup Fabiano Rosas
@ 2022-02-03 22:42 ` Fabiano Rosas
2022-02-03 22:42 ` [PATCH 06/10] target/ppc: 7xx: Program exception cleanup Fabiano Rosas
` (5 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-03 22:42 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There is no MSR_HV in the 7xx so remove the LPES0 handling.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 37 -------------------------------------
1 file changed, 37 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 4996b96616..5e2c2aa544 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -815,44 +815,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
msr |= env->error_code;
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
- {
- bool lpes0;
-
- cs = CPU(cpu);
-
- /*
- * Exception targeting modifiers
- *
- * LPES0 is supported on POWER7/8/9
- * LPES1 is not supported (old iSeries mode)
- *
- * On anything else, we behave as if LPES0 is 1
- * (externals don't alter MSR:HV)
- */
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9 ||
- excp_model == POWERPC_EXCP_POWER10) {
- lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- lpes0 = true;
- }
-
- if (!lpes0) {
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- }
- if (env->mpic_proxy) {
- /* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
- }
break;
- }
case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Get rS/rD and rA from faulting opcode */
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 06/10] target/ppc: 7xx: Program exception cleanup
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
` (4 preceding siblings ...)
2022-02-03 22:42 ` [PATCH 05/10] target/ppc: 7xx: External interrupt cleanup Fabiano Rosas
@ 2022-02-03 22:42 ` Fabiano Rosas
2022-02-03 22:42 ` [PATCH 07/10] target/ppc: 7xx: System Call " Fabiano Rosas
` (4 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-03 22:42 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There's no ESR in the 7xx.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 5e2c2aa544..8f810f7de5 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -841,20 +841,16 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
* precise in the MSR.
*/
msr |= 0x00100000;
- env->spr[SPR_BOOKE_ESR] = ESR_FP;
break;
case POWERPC_EXCP_INVAL:
trace_ppc_excp_inval(env->nip);
msr |= 0x00080000;
- env->spr[SPR_BOOKE_ESR] = ESR_PIL;
break;
case POWERPC_EXCP_PRIV:
msr |= 0x00040000;
- env->spr[SPR_BOOKE_ESR] = ESR_PPR;
break;
case POWERPC_EXCP_TRAP:
msr |= 0x00020000;
- env->spr[SPR_BOOKE_ESR] = ESR_PTR;
break;
default:
/* Should never occur */
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 07/10] target/ppc: 7xx: System Call exception cleanup
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
` (5 preceding siblings ...)
2022-02-03 22:42 ` [PATCH 06/10] target/ppc: 7xx: Program exception cleanup Fabiano Rosas
@ 2022-02-03 22:42 ` Fabiano Rosas
2022-02-03 22:42 ` [PATCH 08/10] target/ppc: 7xx: System Reset cleanup Fabiano Rosas
` (3 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-03 22:42 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There is no Hypervisor mode in the 7xx, so no hypercalls.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 21 ++-------------------
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 8f810f7de5..0bb577b75d 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -747,7 +747,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
CPUPPCState *env = &cpu->env;
int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
- int srr0, srr1, lev = -1;
+ int srr0, srr1;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -860,30 +860,13 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
}
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
- lev = env->error_code;
-
- if ((lev == 1) && cpu->vhyp) {
- dump_hcall(env);
- } else {
- dump_syscall(env);
- }
+ dump_syscall(env);
/*
* We need to correct the NIP which in this case is supposed
* to point to the next instruction
*/
env->nip += 4;
-
- /* "PAPR mode" built-in hypercall emulation */
- if ((lev == 1) && cpu->vhyp) {
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
- vhc->hypercall(cpu->vhyp, cpu);
- return;
- }
- if (lev == 1) {
- new_msr |= (target_ulong)MSR_HVB;
- }
break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
case POWERPC_EXCP_DECR: /* Decrementer exception */
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 08/10] target/ppc: 7xx: System Reset cleanup
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
` (6 preceding siblings ...)
2022-02-03 22:42 ` [PATCH 07/10] target/ppc: 7xx: System Call " Fabiano Rosas
@ 2022-02-03 22:42 ` Fabiano Rosas
2022-02-03 22:42 ` [PATCH 09/10] target/ppc: 7xx: Software TLB cleanup Fabiano Rosas
` (2 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-03 22:42 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Thre is no HV support in the 7xx.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0bb577b75d..f29f2ecefb 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -872,23 +872,9 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_DECR: /* Decrementer exception */
break;
case POWERPC_EXCP_RESET: /* System reset exception */
- /* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
- /* indicate that we resumed from power save mode */
- msr |= 0x10000;
- new_msr |= ((target_ulong)1 << MSR_ME);
- }
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
- */
- new_msr |= (target_ulong)MSR_HVB;
- } else {
- if (msr_pow) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
- }
+ cpu_abort(cs, "Trying to deliver power-saving system reset "
+ "exception %d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 09/10] target/ppc: 7xx: Software TLB cleanup
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
` (7 preceding siblings ...)
2022-02-03 22:42 ` [PATCH 08/10] target/ppc: 7xx: System Reset cleanup Fabiano Rosas
@ 2022-02-03 22:42 ` Fabiano Rosas
2022-02-03 22:42 ` [PATCH 10/10] target/ppc: 7xx: Set SRRs directly in exception code Fabiano Rosas
2022-02-04 8:00 ` [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Cédric Le Goater
10 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-03 22:42 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
This code applies only to the 7xx CPUs, so we can remove the switch
statement.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 26 ++++++--------------------
1 file changed, 6 insertions(+), 20 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f29f2ecefb..3872f3b7ad 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -745,7 +745,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
int srr0, srr1;
@@ -882,26 +881,13 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
- switch (excp_model) {
- case POWERPC_EXCP_6xx:
- /* Swap temporary saved registers with GPRs */
- if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
- new_msr |= (target_ulong)1 << MSR_TGPR;
- hreg_swap_gpr_tgpr(env);
- }
- /* fall through */
- case POWERPC_EXCP_7xx:
- ppc_excp_debug_sw_tlb(env, excp);
+ ppc_excp_debug_sw_tlb(env, excp);
+
+ msr |= env->crf[0] << 28;
+ msr |= env->error_code; /* key, D/I, S/L bits */
+ /* Set way using a LRU mechanism */
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- msr |= env->crf[0] << 28;
- msr |= env->error_code; /* key, D/I, S/L bits */
- /* Set way using a LRU mechanism */
- msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- break;
- default:
- cpu_abort(cs, "Invalid TLB miss exception\n");
- break;
- }
break;
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
case POWERPC_EXCP_SMI: /* System management interrupt */
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 10/10] target/ppc: 7xx: Set SRRs directly in exception code
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
` (8 preceding siblings ...)
2022-02-03 22:42 ` [PATCH 09/10] target/ppc: 7xx: Software TLB cleanup Fabiano Rosas
@ 2022-02-03 22:42 ` Fabiano Rosas
2022-02-04 8:00 ` [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Cédric Le Goater
10 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-03 22:42 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The 7xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 3872f3b7ad..0050c8447f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -746,7 +746,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -765,10 +764,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
*/
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
/*
* Hypervisor emulation assistance interrupt only exists on server
* arch 2.05 server or later.
@@ -907,10 +902,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
"no HV support\n", excp);
}
- if (srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
- }
}
/*
@@ -922,10 +913,10 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
}
/* Save PC */
- env->spr[srr0] = env->nip;
+ env->spr[SPR_SRR0] = env->nip;
/* Save MSR */
- env->spr[srr1] = msr;
+ env->spr[SPR_SRR1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n)
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
` (9 preceding siblings ...)
2022-02-03 22:42 ` [PATCH 10/10] target/ppc: 7xx: Set SRRs directly in exception code Fabiano Rosas
@ 2022-02-04 8:00 ` Cédric Le Goater
2022-02-04 16:13 ` Fabiano Rosas
10 siblings, 1 reply; 16+ messages in thread
From: Cédric Le Goater @ 2022-02-04 8:00 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 2/3/22 23:42, Fabiano Rosas wrote:
> This series handles the 7xx family: 740, 745, 750, 750cl, 750cx,
> 750fx, 750gx and 755.
What about powerpc_excp_legacy() ? Can we remove it now ?
Thanks,
C.
> Fabiano Rosas (10):
> target/ppc: Merge 7x5 and 7x0 exception model IDs
> target/ppc: Introduce powerpc_excp_7xx
> target/ppc: Simplify powerpc_excp_7xx
> target/ppc: 7xx: Machine Check exception cleanup
> target/ppc: 7xx: External interrupt cleanup
> target/ppc: 7xx: Program exception cleanup
> target/ppc: 7xx: System Call exception cleanup
> target/ppc: 7xx: System Reset cleanup
> target/ppc: 7xx: Software TLB cleanup
> target/ppc: 7xx: Set SRRs directly in exception code
>
> target/ppc/cpu-qom.h | 6 +-
> target/ppc/cpu_init.c | 16 ++--
> target/ppc/excp_helper.c | 185 ++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 194 insertions(+), 13 deletions(-)
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n)
2022-02-04 8:00 ` [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Cédric Le Goater
@ 2022-02-04 16:13 ` Fabiano Rosas
0 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-02-04 16:13 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel; +Cc: danielhb413, qemu-ppc, david
Cédric Le Goater <clg@kaod.org> writes:
> On 2/3/22 23:42, Fabiano Rosas wrote:
>> This series handles the 7xx family: 740, 745, 750, 750cl, 750cx,
>> 750fx, 750gx and 755.
>
> What about powerpc_excp_legacy() ? Can we remove it now ?
Yes, I'm preparing one more series to wrap things up. There's the
removal of the function and some other adjustments like moving the
initial bounds check and message into powerpc_excp(). I also want to add
new flags for AIL support so we can remove 'excp_model' from the
powerpc_excp_books.
^ permalink raw reply [flat|nested] 16+ messages in thread