[PATCH 00/15] target: Use ArchCPU & CPUArchState as abstract interface to target CPU

[PATCH 00/15] target: Use ArchCPU & CPUArchState as abstract interface to target CPU

[Philippe Mathieu-Daudé via]

Hi Richard,

Kind of respin of the "exec: Move translation declarations to
'translate-all.h'" series, but without modifying translate-all.h :)
(same same but different).

Last patches are RFC, not sure worthwhile (at least for now).

Based-on: <20220207082756.82600-1-f4bug@amsat.org>
"exec: Remove 'qemu/log.h' from 'exec-all.h'"

Philippe Mathieu-Daudé (15):
  meson: Display libfdt as disabled when system emulation is disabled
  hw/m68k/mcf: Add missing 'exec/hwaddr.h' header
  hw/tricore: Remove unused and incorrect header
  exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition
  cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers
  target/i386/cpu: Ensure accelerators set CPU addressble physical bits
  target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header
  target: Include missing 'cpu.h'
  target: Use forward declared type instead of structure type
  target: Use CPUArchState as interface to target-specific CPU state
  target: Use ArchCPU as interface to target CPU
  hw/m68k: Restrict M68kCPU type to target/ code
  hw/mips: Restrict MIPSCPU type to target/ code
  hw/sparc: Restrict SPARCCPU type to target/ code
  hw/sh4: Restrict SuperHCPU type to target/ code

 cpu.c                                |  2 ++
 include/exec/cpu_ldst.h              |  1 +
 include/exec/poison.h                |  2 --
 include/hw/core/cpu.h                |  2 +-
 include/hw/m68k/mcf.h                |  4 ++--
 include/hw/mips/cpudevs.h            |  6 ++----
 include/hw/sh4/sh.h                  |  3 +--
 include/hw/sparc/sparc64.h           |  4 +---
 include/hw/tricore/triboard.h        |  1 -
 include/qemu/typedefs.h              |  2 ++
 meson.build                          |  4 +++-
 target/alpha/cpu-qom.h               |  4 +++-
 target/alpha/cpu.h                   | 11 +++--------
 target/arm/cpu-qom.h                 |  4 +++-
 target/arm/cpu.h                     |  5 +----
 target/arm/hvf_arm.h                 |  2 +-
 target/avr/cpu-qom.h                 |  4 +++-
 target/avr/cpu.h                     | 13 ++++---------
 target/cris/cpu-qom.h                |  4 +++-
 target/cris/cpu.h                    |  7 ++-----
 target/hexagon/cpu.h                 | 10 +++-------
 target/hppa/cpu-qom.h                |  4 +++-
 target/hppa/cpu.h                    | 12 +++---------
 target/i386/cpu-qom.h                |  4 +++-
 target/i386/cpu.c                    |  1 +
 target/i386/cpu.h                    |  7 ++-----
 target/i386/tcg/sysemu/excp_helper.c |  1 +
 target/i386/tcg/sysemu/misc_helper.c |  1 +
 target/m68k/cpu-qom.h                |  2 +-
 target/m68k/cpu.h                    |  9 +++------
 target/microblaze/cpu-qom.h          |  4 +++-
 target/microblaze/cpu.h              | 11 +++++------
 target/microblaze/mmu.h              |  2 ++
 target/mips/cpu-qom.h                |  2 +-
 target/mips/cpu.h                    | 12 ++++--------
 target/mips/internal.h               | 15 ++++++++-------
 target/nios2/cpu.h                   |  8 ++++----
 target/nios2/mmu.h                   |  2 ++
 target/openrisc/cpu.h                | 18 +++++++-----------
 target/ppc/cpu-qom.h                 |  6 ++++--
 target/ppc/cpu.h                     |  7 ++-----
 target/riscv/cpu.h                   | 10 ++++------
 target/riscv/pmp.h                   |  2 ++
 target/rx/cpu-qom.h                  |  6 +++---
 target/rx/cpu.h                      |  6 ++----
 target/s390x/cpu-qom.h               |  8 +++++---
 target/s390x/cpu.h                   |  7 ++-----
 target/sh4/cpu-qom.h                 |  2 +-
 target/sh4/cpu.h                     |  9 +++------
 target/sparc/cpu-qom.h               |  2 +-
 target/sparc/cpu.h                   | 11 ++++-------
 target/tricore/cpu-qom.h             |  4 +++-
 target/tricore/cpu.h                 | 10 +++-------
 target/xtensa/cpu-qom.h              |  4 +++-
 target/xtensa/cpu.h                  | 13 +++++--------
 55 files changed, 142 insertions(+), 175 deletions(-)

-- 
2.34.1

[PATCH 01/15] meson: Display libfdt as disabled when system emulation is disabled

[Philippe Mathieu-Daudé via]

When configuring QEMU with --disable-system, meson keeps showing
libfdt as "auto". Mark it as disabled instead.

Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 meson.build | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index 571af34b7d..3c274386bb 100644
--- a/meson.build
+++ b/meson.build
@@ -2271,8 +2271,8 @@ if get_option('cfi') and slirp_opt == 'system'
 endif
 
 fdt = not_found
-fdt_opt = get_option('fdt')
 if have_system
+  fdt_opt = get_option('fdt')
   if fdt_opt in ['enabled', 'auto', 'system']
     have_internal = fs.exists(meson.current_source_dir() / 'dtc/libfdt/Makefile.libfdt')
     fdt = cc.find_library('fdt', kwargs: static_kwargs,
@@ -2315,6 +2315,8 @@ if have_system
     fdt = declare_dependency(link_with: libfdt,
                              include_directories: fdt_inc)
   endif
+else
+  fdt_opt = 'disabled'
 endif
 if not fdt.found() and fdt_required.length() > 0
   error('fdt not available but required by targets ' + ', '.join(fdt_required))
-- 
2.34.1

[PATCH 02/15] hw/m68k/mcf: Add missing 'exec/hwaddr.h' header

[Philippe Mathieu-Daudé via]

hwaddr type is defined in "exec/hwaddr.h".

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/m68k/mcf.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h
index decf17ce42..8cbd587bbf 100644
--- a/include/hw/m68k/mcf.h
+++ b/include/hw/m68k/mcf.h
@@ -2,6 +2,7 @@
 #define HW_MCF_H
 /* Motorola ColdFire device prototypes.  */
 
+#include "exec/hwaddr.h"
 #include "target/m68k/cpu-qom.h"
 
 /* mcf_uart.c */
-- 
2.34.1

Re: [PATCH 02/15] hw/m68k/mcf: Add missing 'exec/hwaddr.h' header

[Richard Henderson]

On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
> hwaddr type is defined in "exec/hwaddr.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   include/hw/m68k/mcf.h | 1 +
>   1 file changed, 1 insertion(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 02/15] hw/m68k/mcf: Add missing 'exec/hwaddr.h' header

[Thomas Huth]

On 09/02/2022 22.54, Philippe Mathieu-Daudé wrote:
> hwaddr type is defined in "exec/hwaddr.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   include/hw/m68k/mcf.h | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h
> index decf17ce42..8cbd587bbf 100644
> --- a/include/hw/m68k/mcf.h
> +++ b/include/hw/m68k/mcf.h
> @@ -2,6 +2,7 @@
>   #define HW_MCF_H
>   /* Motorola ColdFire device prototypes.  */
>   
> +#include "exec/hwaddr.h"
>   #include "target/m68k/cpu-qom.h"
>   
>   /* mcf_uart.c */

Reviewed-by: Thomas Huth <thuth@redhat.com>

[PATCH 03/15] hw/tricore: Remove unused and incorrect header

[Philippe Mathieu-Daudé via]

TriCore boards certainly don't need the ARM loader API :)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/tricore/triboard.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h
index f3844be447..094c8bd563 100644
--- a/include/hw/tricore/triboard.h
+++ b/include/hw/tricore/triboard.h
@@ -21,7 +21,6 @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/boards.h"
-#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 #include "exec/address-spaces.h"
 #include "qom/object.h"
-- 
2.34.1

Re: [PATCH 03/15] hw/tricore: Remove unused and incorrect header

[Richard Henderson]

On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
> TriCore boards certainly don't need the ARM loader API :)
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   include/hw/tricore/triboard.h | 1 -
>   1 file changed, 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 03/15] hw/tricore: Remove unused and incorrect header

[Thomas Huth]

On 09/02/2022 22.54, Philippe Mathieu-Daudé wrote:
> TriCore boards certainly don't need the ARM loader API :)
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   include/hw/tricore/triboard.h | 1 -
>   1 file changed, 1 deletion(-)
> 
> diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h
> index f3844be447..094c8bd563 100644
> --- a/include/hw/tricore/triboard.h
> +++ b/include/hw/tricore/triboard.h
> @@ -21,7 +21,6 @@
>   #include "qemu/osdep.h"
>   #include "qapi/error.h"
>   #include "hw/boards.h"
> -#include "hw/arm/boot.h"
>   #include "sysemu/sysemu.h"
>   #include "exec/address-spaces.h"
>   #include "qom/object.h"

Reviewed-by: Thomas Huth <thuth@redhat.com>

[PATCH 04/15] exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition

[Philippe Mathieu-Daudé via]

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/exec/cpu_ldst.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index a878fd0105..5c999966de 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -64,6 +64,7 @@
 
 #include "exec/memopidx.h"
 #include "qemu/int128.h"
+#include "cpu.h"
 
 #if defined(CONFIG_USER_ONLY)
 /* sparc32plus has 64bit long but 32bit space address
-- 
2.34.1

[PATCH 05/15] cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers

[Philippe Mathieu-Daudé via]

cpu.c requires "exec/exec-all.h" to call tlb_flush() and
"qemu/accel.h" to call accel_cpu_realizefn().

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/cpu.c b/cpu.c
index 97d42b6b2a..6b4aa53775 100644
--- a/cpu.c
+++ b/cpu.c
@@ -35,10 +35,12 @@
 #include "sysemu/tcg.h"
 #include "sysemu/kvm.h"
 #include "sysemu/replay.h"
+#include "exec/exec-all.h"
 #include "exec/translate-all.h"
 #include "exec/log.h"
 #include "hw/core/accel-cpu.h"
 #include "trace/trace-root.h"
+#include "qemu/accel.h"
 
 uintptr_t qemu_host_page_size;
 intptr_t qemu_host_page_mask;
-- 
2.34.1

[PATCH 06/15] target/i386/cpu: Ensure accelerators set CPU addressble physical bits

[Philippe Mathieu-Daudé via]

The only accelerator allowed to use zero as default value is TCG.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/i386/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index aa9e636800..16523a78d9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6384,6 +6384,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
          * In this case, the default is the value used by TCG (40).
          */
         if (cpu->phys_bits == 0) {
+            assert(tcg_enabled());
             cpu->phys_bits = TCG_PHYS_ADDR_BITS;
         }
     } else {
-- 
2.34.1

[PATCH 07/15] target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header

[Philippe Mathieu-Daudé via]

excp_helper.c requires "exec/exec-all.h" for tlb_set_page_with_attrs()
and misc_helper.c for tlb_flush().

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/i386/tcg/sysemu/excp_helper.c | 1 +
 target/i386/tcg/sysemu/misc_helper.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c
index 5ba739fbed..5627772e7c 100644
--- a/target/i386/tcg/sysemu/excp_helper.c
+++ b/target/i386/tcg/sysemu/excp_helper.c
@@ -19,6 +19,7 @@
 
 #include "qemu/osdep.h"
 #include "cpu.h"
+#include "exec/exec-all.h"
 #include "tcg/helper-tcg.h"
 
 int get_pg_mode(CPUX86State *env)
diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c
index 9ccaa054c4..3715c1e262 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -23,6 +23,7 @@
 #include "exec/helper-proto.h"
 #include "exec/cpu_ldst.h"
 #include "exec/address-spaces.h"
+#include "exec/exec-all.h"
 #include "tcg/helper-tcg.h"
 
 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
-- 
2.34.1

[PATCH 08/15] target: Include missing 'cpu.h'

[Philippe Mathieu-Daudé via]

These target-specific files use the target-specific CPU state
but lack to include "cpu.h"; i.e.:

    ../target/riscv/pmp.h:61:23: error: unknown type name 'CPURISCVState'
    void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
                          ^
    ../target/nios2/mmu.h:43:18: error: unknown type name 'CPUNios2State'
    void mmu_flip_um(CPUNios2State *env, unsigned int um);
                     ^
    ../target/microblaze/mmu.h:88:19: error: unknown type name 'CPUMBState'; did you mean 'CPUState'?
    uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
                      ^~~~~~~~~~
                      CPUState

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/microblaze/mmu.h | 2 ++
 target/mips/internal.h  | 1 +
 target/nios2/mmu.h      | 2 ++
 target/riscv/pmp.h      | 2 ++
 4 files changed, 7 insertions(+)

diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index b6b4b9ad60..1068bd2d52 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -20,6 +20,8 @@
 #ifndef TARGET_MICROBLAZE_MMU_H
 #define TARGET_MICROBLAZE_MMU_H
 
+#include "cpu.h"
+
 #define MMU_R_PID    0
 #define MMU_R_ZPR    1
 #define MMU_R_TLBX   2
diff --git a/target/mips/internal.h b/target/mips/internal.h
index daddb05fd4..f705d6bfa6 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -12,6 +12,7 @@
 #ifdef CONFIG_TCG
 #include "tcg/tcg-internal.h"
 #endif
+#include "cpu.h"
 
 /*
  * MMU types, the first four entries have the same layout as the
diff --git a/target/nios2/mmu.h b/target/nios2/mmu.h
index 4f46fbb82e..d36b8cc86a 100644
--- a/target/nios2/mmu.h
+++ b/target/nios2/mmu.h
@@ -21,6 +21,8 @@
 #ifndef NIOS2_MMU_H
 #define NIOS2_MMU_H
 
+#include "cpu.h"
+
 typedef struct Nios2TLBEntry {
     target_ulong tag;
     target_ulong data;
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index a9a0b363a7..fcb6b7c467 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -22,6 +22,8 @@
 #ifndef RISCV_PMP_H
 #define RISCV_PMP_H
 
+#include "cpu.h"
+
 typedef enum {
     PMP_READ  = 1 << 0,
     PMP_WRITE = 1 << 1,
-- 
2.34.1

[PATCH 09/15] target: Use forward declared type instead of structure type

[Philippe Mathieu-Daudé via]

The CPU / CPU state are forward declared.

  $ git grep -E 'struct [A-Za-z]+CPU\ \*'
  target/arm/hvf_arm.h:16:void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu);
  target/openrisc/cpu.h:234:    int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
  target/openrisc/cpu.h:238:    int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,

  $ git grep -E 'struct CPU[A-Za-z]+State\ \*'
  target/mips/internal.h:137:    int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
  target/mips/internal.h:139:    void (*helper_tlbwi)(struct CPUMIPSState *env);
  target/mips/internal.h:140:    void (*helper_tlbwr)(struct CPUMIPSState *env);
  target/mips/internal.h:141:    void (*helper_tlbp)(struct CPUMIPSState *env);
  target/mips/internal.h:142:    void (*helper_tlbr)(struct CPUMIPSState *env);
  target/mips/internal.h:143:    void (*helper_tlbinv)(struct CPUMIPSState *env);
  target/mips/internal.h:144:    void (*helper_tlbinvf)(struct CPUMIPSState *env);
  target/xtensa/cpu.h:347:    struct CPUXtensaState *env;

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/arm/hvf_arm.h   |  2 +-
 target/mips/internal.h | 14 +++++++-------
 target/openrisc/cpu.h  |  4 ++--
 target/xtensa/cpu.h    |  2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h
index ea238cff83..9a9d1a0bf5 100644
--- a/target/arm/hvf_arm.h
+++ b/target/arm/hvf_arm.h
@@ -13,6 +13,6 @@
 
 #include "cpu.h"
 
-void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu);
+void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu);
 
 #endif
diff --git a/target/mips/internal.h b/target/mips/internal.h
index f705d6bfa6..ac6e03e2f2 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -134,14 +134,14 @@ struct r4k_tlb_t {
 struct CPUMIPSTLBContext {
     uint32_t nb_tlb;
     uint32_t tlb_in_use;
-    int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
+    int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot,
                        target_ulong address, MMUAccessType access_type);
-    void (*helper_tlbwi)(struct CPUMIPSState *env);
-    void (*helper_tlbwr)(struct CPUMIPSState *env);
-    void (*helper_tlbp)(struct CPUMIPSState *env);
-    void (*helper_tlbr)(struct CPUMIPSState *env);
-    void (*helper_tlbinv)(struct CPUMIPSState *env);
-    void (*helper_tlbinvf)(struct CPUMIPSState *env);
+    void (*helper_tlbwi)(CPUMIPSState *env);
+    void (*helper_tlbwr)(CPUMIPSState *env);
+    void (*helper_tlbp)(CPUMIPSState *env);
+    void (*helper_tlbr)(CPUMIPSState *env);
+    void (*helper_tlbinv)(CPUMIPSState *env);
+    void (*helper_tlbinvf)(CPUMIPSState *env);
     union {
         struct {
             r4k_tlb_t tlb[MIPS_TLB_MAX];
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index ee069b080c..5711591520 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -231,11 +231,11 @@ typedef struct CPUOpenRISCTLBContext {
     OpenRISCTLBEntry itlb[TLB_SIZE];
     OpenRISCTLBEntry dtlb[TLB_SIZE];
 
-    int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
+    int (*cpu_openrisc_map_address_code)(OpenRISCCPU *cpu,
                                          hwaddr *physical,
                                          int *prot,
                                          target_ulong address, int rw);
-    int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
+    int (*cpu_openrisc_map_address_data)(OpenRISCCPU *cpu,
                                          hwaddr *physical,
                                          int *prot,
                                          target_ulong address, int rw);
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 02143f2f77..f2165b17e2 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -344,7 +344,7 @@ typedef struct XtensaGdbRegmap {
 } XtensaGdbRegmap;
 
 typedef struct XtensaCcompareTimer {
-    struct CPUXtensaState *env;
+    CPUXtensaState *env;
     QEMUTimer *timer;
 } XtensaCcompareTimer;
 
-- 
2.34.1

[PATCH 10/15] target: Use CPUArchState as interface to target-specific CPU state

[Philippe Mathieu-Daudé via]

While CPUState is our interface with generic code, CPUArchState is
our interface with target-specific code. Use CPUArchState as an
abstract type, defined by each target.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/exec/poison.h   | 2 --
 include/hw/core/cpu.h   | 2 +-
 include/qemu/typedefs.h | 1 +
 target/alpha/cpu.h      | 7 ++-----
 target/arm/cpu.h        | 3 +--
 target/avr/cpu.h        | 7 ++-----
 target/cris/cpu.h       | 3 +--
 target/hexagon/cpu.h    | 8 ++------
 target/hppa/cpu.h       | 8 ++------
 target/i386/cpu.h       | 3 +--
 target/m68k/cpu.h       | 3 +--
 target/microblaze/cpu.h | 5 ++---
 target/mips/cpu.h       | 6 ++----
 target/nios2/cpu.h      | 4 ++--
 target/openrisc/cpu.h   | 3 +--
 target/ppc/cpu-qom.h    | 2 +-
 target/ppc/cpu.h        | 3 +--
 target/riscv/cpu.h      | 5 ++---
 target/rx/cpu-qom.h     | 2 --
 target/rx/cpu.h         | 2 +-
 target/s390x/cpu-qom.h  | 4 ++--
 target/s390x/cpu.h      | 3 +--
 target/sh4/cpu.h        | 3 +--
 target/sparc/cpu.h      | 5 ++---
 target/tricore/cpu.h    | 6 ++----
 target/xtensa/cpu.h     | 7 +++----
 26 files changed, 37 insertions(+), 70 deletions(-)

diff --git a/include/exec/poison.h b/include/exec/poison.h
index 7ad4ad18e8..7c5c02f03f 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -51,8 +51,6 @@
 #pragma GCC poison TARGET_PAGE_BITS
 #pragma GCC poison TARGET_PAGE_ALIGN
 
-#pragma GCC poison CPUArchState
-
 #pragma GCC poison CPU_INTERRUPT_HARD
 #pragma GCC poison CPU_INTERRUPT_EXITTB
 #pragma GCC poison CPU_INTERRUPT_HALT
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 3f2b681281..c9d41e4ece 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -340,7 +340,7 @@ struct CPUState {
     AddressSpace *as;
     MemoryRegion *memory;
 
-    void *env_ptr; /* CPUArchState */
+    CPUArchState *env_ptr;
     IcountDecr *icount_decr_ptr;
 
     /* Accessed in parallel; all accesses must be atomic */
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index ee60eb3de4..c6f692b0dd 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -39,6 +39,7 @@ typedef struct CompatProperty CompatProperty;
 typedef struct CoMutex CoMutex;
 typedef struct ConfidentialGuestSupport ConfidentialGuestSupport;
 typedef struct CPUAddressSpace CPUAddressSpace;
+typedef struct CPUArchState CPUArchState;
 typedef struct CPUState CPUState;
 typedef struct DeviceListener DeviceListener;
 typedef struct DeviceState DeviceState;
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index e819211503..cfd17fd265 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -197,9 +197,7 @@ enum {
 #define MMU_USER_IDX     1
 #define MMU_PHYS_IDX     2
 
-typedef struct CPUAlphaState CPUAlphaState;
-
-struct CPUAlphaState {
+typedef struct CPUArchState {
     uint64_t ir[31];
     float64 fir[31];
     uint64_t pc;
@@ -251,7 +249,7 @@ struct CPUAlphaState {
     uint32_t features;
     uint32_t amask;
     int implver;
-};
+} CPUAlphaState;
 
 /**
  * AlphaCPU:
@@ -285,7 +283,6 @@ int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 
 #define cpu_list alpha_cpu_list
 
-typedef CPUAlphaState CPUArchState;
 typedef AlphaCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c6a4d50e82..a95a070647 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -232,7 +232,7 @@ typedef struct CPUARMTBFlags {
     target_ulong flags2;
 } CPUARMTBFlags;
 
-typedef struct CPUARMState {
+typedef struct CPUArchState {
     /* Regs for current mode.  */
     uint32_t regs[16];
 
@@ -3410,7 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
     }
 }
 
-typedef CPUARMState CPUArchState;
 typedef ARMCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index dceacf3cd7..e4a990556b 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -108,9 +108,7 @@ typedef enum AVRFeature {
     AVR_FEATURE_RAMPZ,
 } AVRFeature;
 
-typedef struct CPUAVRState CPUAVRState;
-
-struct CPUAVRState {
+typedef struct CPUArchState {
     uint32_t pc_w; /* 0x003fffff up to 22 bits */
 
     uint32_t sregC; /* 0x00000001 1 bit */
@@ -137,7 +135,7 @@ struct CPUAVRState {
     bool fullacc; /* CPU/MEM if true MEM only otherwise */
 
     uint64_t features;
-};
+} CPUAVRState;
 
 /**
  *  AVRCPU:
@@ -247,7 +245,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool probe, uintptr_t retaddr);
 
-typedef CPUAVRState CPUArchState;
 typedef AVRCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index b445b194ea..763d4f882e 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -105,7 +105,7 @@ typedef struct {
     uint32_t lo;
 } TLBSet;
 
-typedef struct CPUCRISState {
+typedef struct CPUArchState {
 	uint32_t regs[16];
 	/* P0 - P15 are referred to as special registers in the docs.  */
 	uint32_t pregs[16];
@@ -265,7 +265,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
 #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 
-typedef CPUCRISState CPUArchState;
 typedef CRISCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 58a0d3870b..25c67e43a2 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -18,9 +18,6 @@
 #ifndef HEXAGON_CPU_H
 #define HEXAGON_CPU_H
 
-/* Forward declaration needed by some of the header files */
-typedef struct CPUHexagonState CPUHexagonState;
-
 #include "fpu/softfloat-types.h"
 
 #include "exec/cpu-defs.h"
@@ -75,7 +72,7 @@ typedef struct {
 /* Maximum number of vector temps in a packet */
 #define VECTOR_TEMPS_MAX            4
 
-struct CPUHexagonState {
+typedef struct CPUArchState {
     target_ulong gpr[TOTAL_PER_THREAD_REGS];
     target_ulong pred[NUM_PREGS];
     target_ulong branch_taken;
@@ -129,7 +126,7 @@ struct CPUHexagonState {
     target_ulong vstore_pending[VSTORES_MAX];
     bool vtcm_pending;
     VTCMStoreLog vtcm_log;
-};
+} CPUHexagonState;
 
 #define HEXAGON_CPU_CLASS(klass) \
     OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU)
@@ -180,7 +177,6 @@ static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
 #endif
 }
 
-typedef struct CPUHexagonState CPUArchState;
 typedef HexagonCPU ArchCPU;
 
 void hexagon_translate_init(void);
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 93c119532a..d36e5c170c 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -138,8 +138,6 @@
 #define CR_IPSW          22
 #define CR_EIRR          23
 
-typedef struct CPUHPPAState CPUHPPAState;
-
 #if TARGET_REGISTER_BITS == 32
 typedef uint32_t target_ureg;
 typedef int32_t  target_sreg;
@@ -168,7 +166,7 @@ typedef struct {
     unsigned access_id : 16;
 } hppa_tlb_entry;
 
-struct CPUHPPAState {
+typedef struct CPUArchState {
     target_ureg gr[32];
     uint64_t fr[32];
     uint64_t sr[8];          /* stored shifted into place for gva */
@@ -207,7 +205,7 @@ struct CPUHPPAState {
     /* ??? We should use a more intelligent data structure.  */
     hppa_tlb_entry tlb[HPPA_TLB_ENTRIES];
     uint32_t tlb_last;
-};
+} CPUHPPAState;
 
 /**
  * HPPACPU:
@@ -225,8 +223,6 @@ struct HPPACPU {
     QEMUTimer *alarm_timer;
 };
 
-
-typedef CPUHPPAState CPUArchState;
 typedef HPPACPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 9911d7c871..31ae748570 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1429,7 +1429,7 @@ typedef struct HVFX86LazyFlags {
     target_ulong auxbits;
 } HVFX86LazyFlags;
 
-typedef struct CPUX86State {
+typedef struct CPUArchState {
     /* standard registers */
     target_ulong regs[CPU_NB_REGS];
     target_ulong eip;
@@ -2072,7 +2072,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
 #define CC_SRC2 (env->cc_src2)
 #define CC_OP   (env->cc_op)
 
-typedef CPUX86State CPUArchState;
 typedef X86CPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index a3423729ef..0245398230 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -79,7 +79,7 @@
 
 typedef CPU_LDoubleU FPReg;
 
-typedef struct CPUM68KState {
+typedef struct CPUArchState {
     uint32_t dregs[8];
     uint32_t aregs[8];
     uint32_t pc;
@@ -574,7 +574,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
                                  int mmu_idx, MemTxAttrs attrs,
                                  MemTxResult response, uintptr_t retaddr);
 
-typedef CPUM68KState CPUArchState;
 typedef M68kCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e9cd0b88de..acfd35d3f7 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -24,7 +24,7 @@
 #include "exec/cpu-defs.h"
 #include "fpu/softfloat-types.h"
 
-typedef struct CPUMBState CPUMBState;
+typedef struct CPUArchState CPUMBState;
 #if !defined(CONFIG_USER_ONLY)
 #include "mmu.h"
 #endif
@@ -239,7 +239,7 @@ typedef struct CPUMBState CPUMBState;
 #define USE_NON_SECURE_M_AXI_DC_MASK 0x4
 #define USE_NON_SECURE_M_AXI_IC_MASK 0x8
 
-struct CPUMBState {
+struct CPUArchState {
     uint32_t bvalue;   /* TCG temporary, only valid during a TB */
     uint32_t btarget;  /* Full resolved branch destination */
 
@@ -394,7 +394,6 @@ void mb_tcg_init(void);
 #define MMU_USER_IDX    2
 /* See NB_MMU_MODES further up the file.  */
 
-typedef CPUMBState CPUArchState;
 typedef MicroBlazeCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 56b1cbd091..d4f5d7099a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -524,8 +524,7 @@ struct TCState {
 };
 
 struct MIPSITUState;
-typedef struct CPUMIPSState CPUMIPSState;
-struct CPUMIPSState {
+typedef struct CPUArchState {
     TCState active_tc;
     CPUMIPSFPUContext active_fpu;
 
@@ -1161,7 +1160,7 @@ struct CPUMIPSState {
     QEMUTimer *timer; /* Internal timer */
     target_ulong exception_base; /* ExceptionBase input to the core */
     uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */
-};
+} CPUMIPSState;
 
 /**
  * MIPSCPU:
@@ -1218,7 +1217,6 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
     return hflags_mmu_index(env->hflags);
 }
 
-typedef CPUMIPSState CPUArchState;
 typedef MIPSCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index d2ba0c5bbd..629b9e2301 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -25,7 +25,7 @@
 #include "hw/core/cpu.h"
 #include "qom/object.h"
 
-typedef struct CPUNios2State CPUNios2State;
+typedef struct CPUArchState CPUNios2State;
 #if !defined(CONFIG_USER_ONLY)
 #include "mmu.h"
 #endif
@@ -155,7 +155,7 @@ struct Nios2CPUClass {
 
 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 
-struct CPUNios2State {
+struct CPUArchState {
     uint32_t regs[NUM_CORE_REGS];
 
 #if !defined(CONFIG_USER_ONLY)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 5711591520..a218e49f0e 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -242,7 +242,7 @@ typedef struct CPUOpenRISCTLBContext {
 } CPUOpenRISCTLBContext;
 #endif
 
-typedef struct CPUOpenRISCState {
+typedef struct CPUArchState {
     target_ulong shadow_gpr[16][32]; /* Shadow registers */
 
     target_ulong pc;          /* Program counter */
@@ -348,7 +348,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
 #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
 
-typedef CPUOpenRISCState CPUArchState;
 typedef OpenRISCCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 99a6b509af..87ea91ef9c 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -32,7 +32,7 @@
 OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass,
                     POWERPC_CPU)
 
-typedef struct CPUPPCState CPUPPCState;
+typedef struct CPUArchState CPUPPCState;
 typedef struct ppc_tb_t ppc_tb_t;
 typedef struct ppc_dcr_t ppc_dcr_t;
 
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index dcd83b503c..55ae99e1b8 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1080,7 +1080,7 @@ struct ppc_radix_page_info {
 #define PPC_CPU_OPCODES_LEN          0x40
 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
 
-struct CPUPPCState {
+struct CPUArchState {
     /* Most commonly used resources during translated code execution first */
     target_ulong gpr[32];  /* general purpose registers */
     target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
@@ -1476,7 +1476,6 @@ void ppc_compat_add_property(Object *obj, const char *name,
                              uint32_t *compat_pvr, const char *basedesc);
 #endif /* defined(TARGET_PPC64) */
 
-typedef CPUPPCState CPUArchState;
 typedef PowerPCCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 55635d68d5..79144ddc24 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -97,7 +97,7 @@ enum {
 
 #define MAX_RISCV_PMPS (16)
 
-typedef struct CPURISCVState CPURISCVState;
+typedef struct CPUArchState CPURISCVState;
 
 #if !defined(CONFIG_USER_ONLY)
 #include "pmp.h"
@@ -112,7 +112,7 @@ FIELD(VTYPE, VMA, 7, 1)
 FIELD(VTYPE, VEDIV, 8, 2)
 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
 
-struct CPURISCVState {
+struct CPUArchState {
     target_ulong gpr[32];
     target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
     uint64_t fpr[32]; /* assume both F and D extensions */
@@ -430,7 +430,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS
 
-typedef CPURISCVState CPUArchState;
 typedef RISCVCPU ArchCPU;
 #include "exec/cpu-all.h"
 
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index 7310558e0c..f918c46b00 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -45,6 +45,4 @@ struct RXCPUClass {
     DeviceReset parent_reset;
 };
 
-#define CPUArchState struct CPURXState
-
 #endif
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 58adf9edf6..0f3d9d5bd9 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -65,7 +65,7 @@ enum {
     NUM_REGS = 16,
 };
 
-typedef struct CPURXState {
+typedef struct CPUArchState {
     /* CPU registers */
     uint32_t regs[NUM_REGS];    /* general registers */
     uint32_t psw_o;             /* O bit of status register */
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index 9f3a0d86c5..04d5b3012c 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -31,6 +31,8 @@ OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass,
 typedef struct S390CPUModel S390CPUModel;
 typedef struct S390CPUDef S390CPUDef;
 
+typedef struct CPUArchState CPUS390XState;
+
 typedef enum cpu_reset_type {
     S390_CPU_RESET_NORMAL,
     S390_CPU_RESET_INITIAL,
@@ -63,6 +65,4 @@ struct S390CPUClass {
     void (*reset)(CPUState *cpu, cpu_reset_type type);
 };
 
-typedef struct CPUS390XState CPUS390XState;
-
 #endif
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index a75e559134..b668c1b0c7 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -51,7 +51,7 @@ typedef struct PSW {
     uint64_t addr;
 } PSW;
 
-struct CPUS390XState {
+struct CPUArchState {
     uint64_t regs[16];     /* GP registers */
     /*
      * The floating point registers are part of the vector registers.
@@ -840,7 +840,6 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env);
 /* outside of target/s390x/ */
 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 
-typedef CPUS390XState CPUArchState;
 typedef S390CPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index fb9dd9db2f..9a89d2d038 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -130,7 +130,7 @@ typedef struct memory_content {
     struct memory_content *next;
 } memory_content;
 
-typedef struct CPUSH4State {
+typedef struct CPUArchState {
     uint32_t flags;		/* general execution flags */
     uint32_t gregs[24];		/* general registers */
     float32 fregs[32];		/* floating point registers */
@@ -264,7 +264,6 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
     }
 }
 
-typedef CPUSH4State CPUArchState;
 typedef SuperHCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 5a7f1ed5d6..938efb72bf 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -420,7 +420,7 @@ struct CPUTimer
 
 typedef struct CPUTimer CPUTimer;
 
-typedef struct CPUSPARCState CPUSPARCState;
+typedef struct CPUArchState CPUSPARCState;
 #if defined(TARGET_SPARC64)
 typedef union {
    uint64_t mmuregs[16];
@@ -439,7 +439,7 @@ typedef union {
    };
 } SparcV9MMU;
 #endif
-struct CPUSPARCState {
+struct CPUArchState {
     target_ulong gregs[8]; /* general registers */
     target_ulong *regwptr; /* pointer to current register window */
     target_ulong pc;       /* program counter */
@@ -743,7 +743,6 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
 #endif
 }
 
-typedef CPUSPARCState CPUArchState;
 typedef SPARCCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index c461387e71..398d5076be 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -28,8 +28,7 @@ struct tricore_boot_info;
 
 typedef struct tricore_def_t tricore_def_t;
 
-typedef struct CPUTriCoreState CPUTriCoreState;
-struct CPUTriCoreState {
+typedef struct CPUArchState {
     /* GPR Register */
     uint32_t gpr_a[16];
     uint32_t gpr_d[16];
@@ -189,7 +188,7 @@ struct CPUTriCoreState {
     const tricore_def_t *cpu_model;
     void *irq[8];
     struct QEMUTimer *timer; /* Internal timer */
-};
+} CPUTriCoreState;
 
 /**
  * TriCoreCPU:
@@ -369,7 +368,6 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
     return 0;
 }
 
-typedef CPUTriCoreState CPUArchState;
 typedef TriCoreCPU ArchCPU;
 
 #include "exec/cpu-all.h"
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index f2165b17e2..4496325970 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -306,7 +306,7 @@ typedef enum {
     INTTYPE_MAX
 } interrupt_type;
 
-struct CPUXtensaState;
+typedef struct CPUArchState CPUXtensaState;
 
 typedef struct xtensa_tlb_entry {
     uint32_t vaddr;
@@ -506,7 +506,7 @@ enum {
 };
 #endif
 
-typedef struct CPUXtensaState {
+struct CPUArchState {
     const XtensaConfig *config;
     uint32_t regs[16];
     uint32_t pc;
@@ -545,7 +545,7 @@ typedef struct CPUXtensaState {
 
     /* Watchpoints for DBREAK registers */
     struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
-} CPUXtensaState;
+};
 
 /**
  * XtensaCPU:
@@ -722,7 +722,6 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
 
-typedef CPUXtensaState CPUArchState;
 typedef XtensaCPU ArchCPU;
 
 #include "exec/cpu-all.h"
-- 
2.34.1

[PATCH 11/15] target: Use ArchCPU as interface to target CPU

[Philippe Mathieu-Daudé via]

ArchCPU is our interface with target-specific code. Use it as
a forward-declared opaque pointer (abstract type), having its
structure defined by each target.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/qemu/typedefs.h     |  1 +
 target/alpha/cpu-qom.h      |  4 +++-
 target/alpha/cpu.h          |  4 +---
 target/arm/cpu-qom.h        |  4 +++-
 target/arm/cpu.h            |  2 --
 target/avr/cpu-qom.h        |  4 +++-
 target/avr/cpu.h            |  6 ++----
 target/cris/cpu-qom.h       |  4 +++-
 target/cris/cpu.h           |  4 +---
 target/hexagon/cpu.h        |  2 +-
 target/hppa/cpu-qom.h       |  4 +++-
 target/hppa/cpu.h           |  4 +---
 target/i386/cpu-qom.h       |  4 +++-
 target/i386/cpu.h           |  4 +---
 target/m68k/cpu-qom.h       |  4 +++-
 target/m68k/cpu.h           |  4 +---
 target/microblaze/cpu-qom.h |  4 +++-
 target/microblaze/cpu.h     |  6 +++---
 target/mips/cpu-qom.h       |  4 +++-
 target/mips/cpu.h           |  4 +---
 target/nios2/cpu.h          |  4 ++--
 target/openrisc/cpu.h       | 11 ++++-------
 target/ppc/cpu-qom.h        |  4 +++-
 target/ppc/cpu.h            |  4 +---
 target/riscv/cpu.h          |  5 ++---
 target/rx/cpu-qom.h         |  4 +++-
 target/rx/cpu.h             |  4 +---
 target/s390x/cpu-qom.h      |  4 +++-
 target/s390x/cpu.h          |  4 +---
 target/sh4/cpu-qom.h        |  4 +++-
 target/sh4/cpu.h            |  4 +---
 target/sparc/cpu-qom.h      |  4 +++-
 target/sparc/cpu.h          |  4 +---
 target/tricore/cpu-qom.h    |  4 +++-
 target/tricore/cpu.h        |  4 +---
 target/xtensa/cpu-qom.h     |  4 +++-
 target/xtensa/cpu.h         |  4 +---
 37 files changed, 76 insertions(+), 77 deletions(-)

diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index c6f692b0dd..c564f54c11 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -26,6 +26,7 @@ typedef struct AddressSpace AddressSpace;
 typedef struct AioContext AioContext;
 typedef struct Aml Aml;
 typedef struct AnnounceTimer AnnounceTimer;
+typedef struct ArchCPU ArchCPU;
 typedef struct BdrvDirtyBitmap BdrvDirtyBitmap;
 typedef struct BdrvDirtyBitmapIter BdrvDirtyBitmapIter;
 typedef struct BlockBackend BlockBackend;
diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
index 7bb9173c57..6fd2dec1a7 100644
--- a/target/alpha/cpu-qom.h
+++ b/target/alpha/cpu-qom.h
@@ -25,7 +25,9 @@
 
 #define TYPE_ALPHA_CPU "alpha-cpu"
 
-OBJECT_DECLARE_TYPE(AlphaCPU, AlphaCPUClass,
+typedef struct ArchCPU AlphaCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, AlphaCPUClass,
                     ALPHA_CPU)
 
 /**
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index cfd17fd265..58f00b7814 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -257,7 +257,7 @@ typedef struct CPUArchState {
  *
  * An Alpha CPU.
  */
-struct AlphaCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -283,8 +283,6 @@ int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 
 #define cpu_list alpha_cpu_list
 
-typedef AlphaCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 enum {
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index a22bd506d0..b0a0724e8c 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -27,7 +27,9 @@ struct arm_boot_info;
 
 #define TYPE_ARM_CPU "arm-cpu"
 
-OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass,
+typedef struct ArchCPU ARMCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, ARMCPUClass,
                     ARM_CPU)
 
 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a95a070647..a137c564c4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3410,8 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
     }
 }
 
-typedef ARMCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 /*
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
index 14e5b3ce72..e212cac0b5 100644
--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@@ -26,7 +26,9 @@
 
 #define TYPE_AVR_CPU "avr-cpu"
 
-OBJECT_DECLARE_TYPE(AVRCPU, AVRCPUClass,
+typedef struct ArchCPU AVRCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, AVRCPUClass,
                     AVR_CPU)
 
 /**
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index e4a990556b..55497f851d 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -143,14 +143,14 @@ typedef struct CPUArchState {
  *
  *  A AVR CPU.
  */
-typedef struct AVRCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
 
     CPUNegativeOffsetState neg;
     CPUAVRState env;
-} AVRCPU;
+};
 
 extern const struct VMStateDescription vms_avr_cpu;
 
@@ -245,8 +245,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool probe, uintptr_t retaddr);
 
-typedef AVRCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 #endif /* !defined (QEMU_AVR_CPU_H) */
diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
index 2596edc7e3..89f1116020 100644
--- a/target/cris/cpu-qom.h
+++ b/target/cris/cpu-qom.h
@@ -25,7 +25,9 @@
 
 #define TYPE_CRIS_CPU "cris-cpu"
 
-OBJECT_DECLARE_TYPE(CRISCPU, CRISCPUClass,
+typedef struct ArchCPU CRISCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, CRISCPUClass,
                     CRIS_CPU)
 
 /**
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 763d4f882e..e6776f25b1 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -173,7 +173,7 @@ typedef struct CPUArchState {
  *
  * A CRIS CPU.
  */
-struct CRISCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -265,8 +265,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
 #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 
-typedef CRISCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 25c67e43a2..4dce40a360 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -143,7 +143,7 @@ typedef struct HexagonCPUClass {
     DeviceReset parent_reset;
 } HexagonCPUClass;
 
-typedef struct HexagonCPU {
+typedef struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
index d424f88370..c846c18304 100644
--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@@ -25,7 +25,9 @@
 
 #define TYPE_HPPA_CPU "hppa-cpu"
 
-OBJECT_DECLARE_TYPE(HPPACPU, HPPACPUClass,
+typedef struct ArchCPU HPPACPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, HPPACPUClass,
                     HPPA_CPU)
 
 /**
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index d36e5c170c..4cc936b6bf 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -213,7 +213,7 @@ typedef struct CPUArchState {
  *
  * An HPPA CPU.
  */
-struct HPPACPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -223,8 +223,6 @@ struct HPPACPU {
     QEMUTimer *alarm_timer;
 };
 
-typedef HPPACPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index f9923cee04..db33cf6762 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -30,7 +30,9 @@
 #define TYPE_X86_CPU "i386-cpu"
 #endif
 
-OBJECT_DECLARE_TYPE(X86CPU, X86CPUClass,
+typedef struct ArchCPU X86CPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, X86CPUClass,
                     X86_CPU)
 
 typedef struct X86CPUModel X86CPUModel;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 31ae748570..b5d1ff5956 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1705,7 +1705,7 @@ struct kvm_msrs;
  *
  * An x86 CPU.
  */
-struct X86CPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -2072,8 +2072,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
 #define CC_SRC2 (env->cc_src2)
 #define CC_OP   (env->cc_op)
 
-typedef X86CPU ArchCPU;
-
 #include "exec/cpu-all.h"
 #include "svm.h"
 
diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index 1ceb160ecb..c2c0736b3b 100644
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -25,7 +25,9 @@
 
 #define TYPE_M68K_CPU "m68k-cpu"
 
-OBJECT_DECLARE_TYPE(M68kCPU, M68kCPUClass,
+typedef struct ArchCPU M68kCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, M68kCPUClass,
                     M68K_CPU)
 
 /*
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 0245398230..872e8ce637 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -156,7 +156,7 @@ typedef struct CPUArchState {
  *
  * A Motorola 68k CPU.
  */
-struct M68kCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -574,8 +574,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
                                  int mmu_idx, MemTxAttrs attrs,
                                  MemTxResult response, uintptr_t retaddr);
 
-typedef M68kCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 /* TB flags */
diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
index e520eefb12..8f11fe4d73 100644
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@@ -25,7 +25,9 @@
 
 #define TYPE_MICROBLAZE_CPU "microblaze-cpu"
 
-OBJECT_DECLARE_TYPE(MicroBlazeCPU, MicroBlazeCPUClass,
+typedef struct ArchCPU MicroBlazeCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, MicroBlazeCPUClass,
                     MICROBLAZE_CPU)
 
 /**
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index acfd35d3f7..d511b6b877 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -25,6 +25,8 @@
 #include "fpu/softfloat-types.h"
 
 typedef struct CPUArchState CPUMBState;
+typedef struct ArchCPU MicroBlazeCPU;
+
 #if !defined(CONFIG_USER_ONLY)
 #include "mmu.h"
 #endif
@@ -339,7 +341,7 @@ typedef struct {
  *
  * A MicroBlaze CPU.
  */
-struct MicroBlazeCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
 
@@ -394,8 +396,6 @@ void mb_tcg_init(void);
 #define MMU_USER_IDX    2
 /* See NB_MMU_MODES further up the file.  */
 
-typedef MicroBlazeCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 /* Ensure there is no overlap between the two masks. */
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index dda0c911fa..41f3d01a80 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -29,7 +29,9 @@
 #define TYPE_MIPS_CPU "mips-cpu"
 #endif
 
-OBJECT_DECLARE_TYPE(MIPSCPU, MIPSCPUClass,
+typedef struct ArchCPU MIPSCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, MIPSCPUClass,
                     MIPS_CPU)
 
 /**
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d4f5d7099a..09e98f64de 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1171,7 +1171,7 @@ typedef struct CPUArchState {
  *
  * A MIPS CPU.
  */
-struct MIPSCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -1217,8 +1217,6 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
     return hflags_mmu_index(env->hflags);
 }
 
-typedef MIPSCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 /* Exceptions */
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 629b9e2301..05def159b1 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -32,7 +32,7 @@ typedef struct CPUArchState CPUNios2State;
 
 #define TYPE_NIOS2_CPU "nios2-cpu"
 
-OBJECT_DECLARE_TYPE(Nios2CPU, Nios2CPUClass,
+OBJECT_DECLARE_TYPE(ArchCPU, Nios2CPUClass,
                     NIOS2_CPU)
 
 /**
@@ -171,7 +171,7 @@ struct CPUArchState {
  *
  * A Nios2 CPU.
  */
-struct Nios2CPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index a218e49f0e..9111b050ad 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -24,12 +24,11 @@
 #include "hw/core/cpu.h"
 #include "qom/object.h"
 
-/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl.  */
-struct OpenRISCCPU;
-
 #define TYPE_OPENRISC_CPU "or1k-cpu"
 
-OBJECT_DECLARE_TYPE(OpenRISCCPU, OpenRISCCPUClass,
+typedef struct ArchCPU OpenRISCCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, OpenRISCCPUClass,
                     OPENRISC_CPU)
 
 /**
@@ -301,7 +300,7 @@ typedef struct CPUArchState {
  *
  * A OpenRISC CPU.
  */
-struct OpenRISCCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -348,8 +347,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
 #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
 
-typedef OpenRISCCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 #define TB_FLAGS_SM    SR_SM
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 87ea91ef9c..48671b13ac 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -29,7 +29,9 @@
 #define TYPE_POWERPC_CPU "powerpc-cpu"
 #endif
 
-OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass,
+typedef struct ArchCPU PowerPCCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, PowerPCCPUClass,
                     POWERPC_CPU)
 
 typedef struct CPUArchState CPUPPCState;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 55ae99e1b8..86f021c45d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1278,7 +1278,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
  *
  * A PowerPC CPU.
  */
-struct PowerPCCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -1476,8 +1476,6 @@ void ppc_compat_add_property(Object *obj, const char *name,
                              uint32_t *compat_pvr, const char *basedesc);
 #endif /* defined(TARGET_PPC64) */
 
-typedef PowerPCCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 /*****************************************************************************/
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 79144ddc24..5981be47d9 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -285,7 +285,7 @@ struct CPUArchState {
     uint64_t kvm_timer_frequency;
 };
 
-OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
+OBJECT_DECLARE_TYPE(ArchCPU, RISCVCPUClass,
                     RISCV_CPU)
 
 /**
@@ -309,7 +309,7 @@ struct RISCVCPUClass {
  *
  * A RISCV CPU.
  */
-struct RISCVCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -430,7 +430,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS
 
-typedef RISCVCPU ArchCPU;
 #include "exec/cpu-all.h"
 
 FIELD(TB_FLAGS, MEM_IDX, 0, 3)
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index f918c46b00..09b59f8e1d 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -26,7 +26,9 @@
 
 #define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n")
 
-OBJECT_DECLARE_TYPE(RXCPU, RXCPUClass,
+typedef struct ArchCPU RXCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, RXCPUClass,
                     RX_CPU)
 
 /*
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0f3d9d5bd9..b4abd90ccd 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -105,7 +105,7 @@ typedef struct CPUArchState {
  *
  * A RX CPU
  */
-struct RXCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -114,8 +114,6 @@ struct RXCPU {
     CPURXState env;
 };
 
-typedef RXCPU ArchCPU;
-
 #define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
 #define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_RX_CPU
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index 04d5b3012c..fe126e6b1d 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -25,7 +25,9 @@
 
 #define TYPE_S390_CPU "s390x-cpu"
 
-OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass,
+typedef struct ArchCPU S390CPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, S390CPUClass,
                     S390_CPU)
 
 typedef struct S390CPUModel S390CPUModel;
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index b668c1b0c7..c49c8466e7 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -163,7 +163,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
  *
  * An S/390 CPU.
  */
-struct S390CPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -840,8 +840,6 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env);
 /* outside of target/s390x/ */
 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 
-typedef S390CPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 #endif
diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index 8903b4b9c7..64be55a924 100644
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -29,7 +29,9 @@
 #define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r")
 #define TYPE_SH7785_CPU  SUPERH_CPU_TYPE_NAME("sh7785")
 
-OBJECT_DECLARE_TYPE(SuperHCPU, SuperHCPUClass,
+typedef struct ArchCPU SuperHCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, SuperHCPUClass,
                     SUPERH_CPU)
 
 /**
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 9a89d2d038..c72a30edfd 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -195,7 +195,7 @@ typedef struct CPUArchState {
  *
  * A SuperH CPU.
  */
-struct SuperHCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -264,8 +264,6 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
     }
 }
 
-typedef SuperHCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 /* MMU control register */
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index f33949aaee..d5f90cffd4 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -29,7 +29,9 @@
 #define TYPE_SPARC_CPU "sparc-cpu"
 #endif
 
-OBJECT_DECLARE_TYPE(SPARCCPU, SPARCCPUClass,
+typedef struct ArchCPU SPARCCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, SPARCCPUClass,
                     SPARC_CPU)
 
 typedef struct sparc_def_t sparc_def_t;
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 938efb72bf..abb38db674 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -556,7 +556,7 @@ struct CPUArchState {
  *
  * A SPARC CPU.
  */
-struct SPARCCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -743,8 +743,6 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
 #endif
 }
 
-typedef SPARCCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 #ifdef TARGET_SPARC64
diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
index 59bfd01bbc..8259595fe5 100644
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@@ -24,7 +24,9 @@
 
 #define TYPE_TRICORE_CPU "tricore-cpu"
 
-OBJECT_DECLARE_TYPE(TriCoreCPU, TriCoreCPUClass,
+typedef struct ArchCPU TriCoreCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, TriCoreCPUClass,
                     TRICORE_CPU)
 
 struct TriCoreCPUClass {
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 398d5076be..108d6b8288 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -196,7 +196,7 @@ typedef struct CPUArchState {
  *
  * A TriCore CPU.
  */
-struct TriCoreCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -368,8 +368,6 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
     return 0;
 }
 
-typedef TriCoreCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 void cpu_state_reset(CPUTriCoreState *s);
diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
index 41d9859673..c4ee073fc6 100644
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@@ -34,7 +34,9 @@
 
 #define TYPE_XTENSA_CPU "xtensa-cpu"
 
-OBJECT_DECLARE_TYPE(XtensaCPU, XtensaCPUClass,
+typedef struct ArchCPU XtensaCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, XtensaCPUClass,
                     XTENSA_CPU)
 
 typedef struct XtensaConfig XtensaConfig;
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 4496325970..4515f682aa 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -553,7 +553,7 @@ struct CPUArchState {
  *
  * An Xtensa CPU.
  */
-struct XtensaCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -722,8 +722,6 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
 
-typedef XtensaCPU ArchCPU;
-
 #include "exec/cpu-all.h"
 
 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
-- 
2.34.1

Re: [PATCH 11/15] target: Use ArchCPU as interface to target CPU

[Philippe Mathieu-Daudé via]

On 9/2/22 22:54, Philippe Mathieu-Daudé wrote:
> ArchCPU is our interface with target-specific code. Use it as
> a forward-declared opaque pointer (abstract type), having its
> structure defined by each target.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   include/qemu/typedefs.h     |  1 +
>   target/alpha/cpu-qom.h      |  4 +++-
>   target/alpha/cpu.h          |  4 +---
>   target/arm/cpu-qom.h        |  4 +++-
>   target/arm/cpu.h            |  2 --
>   target/avr/cpu-qom.h        |  4 +++-
>   target/avr/cpu.h            |  6 ++----
>   target/cris/cpu-qom.h       |  4 +++-
>   target/cris/cpu.h           |  4 +---
>   target/hexagon/cpu.h        |  2 +-
>   target/hppa/cpu-qom.h       |  4 +++-
>   target/hppa/cpu.h           |  4 +---
>   target/i386/cpu-qom.h       |  4 +++-
>   target/i386/cpu.h           |  4 +---
>   target/m68k/cpu-qom.h       |  4 +++-
>   target/m68k/cpu.h           |  4 +---
>   target/microblaze/cpu-qom.h |  4 +++-
>   target/microblaze/cpu.h     |  6 +++---
>   target/mips/cpu-qom.h       |  4 +++-
>   target/mips/cpu.h           |  4 +---
>   target/nios2/cpu.h          |  4 ++--
>   target/openrisc/cpu.h       | 11 ++++-------
>   target/ppc/cpu-qom.h        |  4 +++-
>   target/ppc/cpu.h            |  4 +---
>   target/riscv/cpu.h          |  5 ++---
>   target/rx/cpu-qom.h         |  4 +++-
>   target/rx/cpu.h             |  4 +---
>   target/s390x/cpu-qom.h      |  4 +++-
>   target/s390x/cpu.h          |  4 +---
>   target/sh4/cpu-qom.h        |  4 +++-
>   target/sh4/cpu.h            |  4 +---
>   target/sparc/cpu-qom.h      |  4 +++-
>   target/sparc/cpu.h          |  4 +---
>   target/tricore/cpu-qom.h    |  4 +++-
>   target/tricore/cpu.h        |  4 +---
>   target/xtensa/cpu-qom.h     |  4 +++-
>   target/xtensa/cpu.h         |  4 +---
>   37 files changed, 76 insertions(+), 77 deletions(-)
...

> diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
> index a22bd506d0..b0a0724e8c 100644
> --- a/target/arm/cpu-qom.h
> +++ b/target/arm/cpu-qom.h
> @@ -27,7 +27,9 @@ struct arm_boot_info;
>   
>   #define TYPE_ARM_CPU "arm-cpu"
>   
> -OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass,
> +typedef struct ArchCPU ARMCPU;
> +
> +OBJECT_DECLARE_TYPE(ArchCPU, ARMCPUClass,
>                       ARM_CPU)
>   
>   #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index a95a070647..a137c564c4 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -3410,8 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
>       }
>   }
>   
> -typedef ARMCPU ArchCPU;
> -
>   #include "exec/cpu-all.h"
>   
>   /*
...

> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 79144ddc24..5981be47d9 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -285,7 +285,7 @@ struct CPUArchState {
>       uint64_t kvm_timer_frequency;
>   };
>   
> -OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
> +OBJECT_DECLARE_TYPE(ArchCPU, RISCVCPUClass,
>                       RISCV_CPU)
>   
>   /**
> @@ -309,7 +309,7 @@ struct RISCVCPUClass {
>    *
>    * A RISCV CPU.
>    */
> -struct RISCVCPU {
> +struct ArchCPU {
>       /*< private >*/
>       CPUState parent_obj;
>       /*< public >*/
> @@ -430,7 +430,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>   #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
>   #define TB_FLAGS_MSTATUS_VS MSTATUS_VS
>   
> -typedef RISCVCPU ArchCPU;
>   #include "exec/cpu-all.h"
>   
>   FIELD(TB_FLAGS, MEM_IDX, 0, 3)

Sorry I messed while rebasing, this hunk is missing:

-- >8 --
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a137c564c4..a4bbca1812 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -774,7 +774,7 @@ typedef struct ARMISARegisters ARMISARegisters;
   *
   * An ARM CPU core.
   */
-struct ARMCPU {
+struct ArchCPU {
      /*< private >*/
      CPUState parent_obj;
      /*< public >*/
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 05def159b1..6a243cfc06 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -171,7 +171,7 @@ struct CPUArchState {
   *
   * A Nios2 CPU.
   */
-struct ArchCPU {
+typedef struct ArchCPU {
      /*< private >*/
      CPUState parent_obj;
      /*< public >*/
@@ -188,7 +188,7 @@ struct ArchCPU {
      uint32_t reset_addr;
      uint32_t exception_addr;
      uint32_t fast_tlb_miss_addr;
-};
+} Nios2CPU;


  void nios2_tcg_init(void);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5981be47d9..d8fefcbc4e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -309,7 +309,7 @@ struct RISCVCPUClass {
   *
   * A RISCV CPU.
   */
-struct ArchCPU {
+typedef struct ArchCPU {
      /*< private >*/
      CPUState parent_obj;
      /*< public >*/
@@ -357,7 +357,7 @@ struct ArchCPU {
          bool epmp;
          uint64_t resetvec;
      } cfg;
-};
+} RISCVCPU;

  static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
  {
---

Re: [PATCH 11/15] target: Use ArchCPU as interface to target CPU

[Richard Henderson]

On 2/10/22 09:33, Philippe Mathieu-Daudé wrote:
> -struct ArchCPU {
> +typedef struct ArchCPU {
>       /*< private >*/
>       CPUState parent_obj;
>       /*< public >*/
> @@ -188,7 +188,7 @@ struct ArchCPU {
>       uint32_t reset_addr;
>       uint32_t exception_addr;
>       uint32_t fast_tlb_miss_addr;
> -};
> +} Nios2CPU;

I think keeping the typedef separate, as you have done for the other targets, is easier to 
read.


r~

Re: [PATCH 11/15] target: Use ArchCPU as interface to target CPU

[Richard Henderson]

On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index 25c67e43a2..4dce40a360 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -143,7 +143,7 @@ typedef struct HexagonCPUClass {
>       DeviceReset parent_reset;
>   } HexagonCPUClass;
>   
> -typedef struct HexagonCPU {
> +typedef struct ArchCPU {
>       /*< private >*/
>       CPUState parent_obj;
>       /*< public >*/

There's still the typedef of ArchCPU below, which ought to be redundant now.
It may or may not be less confusing to separate out the typedef for HexagonCPU.
It definitely would be worthwhile to convert hexagon to OBJECT_DECLARE_TYPE (cc Taylor).

> diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
> index e520eefb12..8f11fe4d73 100644
> --- a/target/microblaze/cpu-qom.h
> +++ b/target/microblaze/cpu-qom.h
> @@ -25,7 +25,9 @@
>   
>   #define TYPE_MICROBLAZE_CPU "microblaze-cpu"
>   
> -OBJECT_DECLARE_TYPE(MicroBlazeCPU, MicroBlazeCPUClass,
> +typedef struct ArchCPU MicroBlazeCPU;
> +
> +OBJECT_DECLARE_TYPE(ArchCPU, MicroBlazeCPUClass,
>                       MICROBLAZE_CPU)
>   
>   /**
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index acfd35d3f7..d511b6b877 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -25,6 +25,8 @@
>   #include "fpu/softfloat-types.h"
>   
>   typedef struct CPUArchState CPUMBState;
> +typedef struct ArchCPU MicroBlazeCPU;

Duplicate typedef.

> diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
> index 629b9e2301..05def159b1 100644
> --- a/target/nios2/cpu.h
> +++ b/target/nios2/cpu.h
> @@ -32,7 +32,7 @@ typedef struct CPUArchState CPUNios2State;
>   
>   #define TYPE_NIOS2_CPU "nios2-cpu"
>   
> -OBJECT_DECLARE_TYPE(Nios2CPU, Nios2CPUClass,
> +OBJECT_DECLARE_TYPE(ArchCPU, Nios2CPUClass,
>                       NIOS2_CPU)
>   
>   /**
> @@ -171,7 +171,7 @@ struct CPUArchState {
>    *
>    * A Nios2 CPU.
>    */
> -struct Nios2CPU {
> +struct ArchCPU {
>       /*< private >*/
>       CPUState parent_obj;
>       /*< public >*/

Missing Nios2CPU typedef.
Still have the 'typedef Nios2CPU ArchCPU' below.

> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 79144ddc24..5981be47d9 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -285,7 +285,7 @@ struct CPUArchState {
>       uint64_t kvm_timer_frequency;
>   };
>   
> -OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
> +OBJECT_DECLARE_TYPE(ArchCPU, RISCVCPUClass,
>                       RISCV_CPU)
>   
>   /**
> @@ -309,7 +309,7 @@ struct RISCVCPUClass {
>    *
>    * A RISCV CPU.
>    */
> -struct RISCVCPU {
> +struct ArchCPU {
>       /*< private >*/
>       CPUState parent_obj;
>       /*< public >*/
> @@ -430,7 +430,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>   #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
>   #define TB_FLAGS_MSTATUS_VS MSTATUS_VS
>   
> -typedef RISCVCPU ArchCPU;
>   #include "exec/cpu-all.h"
>   
>   FIELD(TB_FLAGS, MEM_IDX, 0, 3)

Missing RISCVCPU typedef.


r~

RE: [PATCH 11/15] target: Use ArchCPU as interface to target CPU

[Taylor Simpson]

> -----Original Message-----
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Wednesday, February 9, 2022 4:48 PM
> To: Philippe Mathieu-Daudé <f4bug@amsat.org>; qemu-devel@nongnu.org
> Cc: Paolo Bonzini <pbonzini@redhat.com>; Thomas Huth
> <thuth@redhat.com>; Taylor Simpson <tsimpson@quicinc.com>
> Subject: Re: [PATCH 11/15] target: Use ArchCPU as interface to target CPU
> 
> On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
> > diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index
> > 25c67e43a2..4dce40a360 100644
> > --- a/target/hexagon/cpu.h
> > +++ b/target/hexagon/cpu.h
> > @@ -143,7 +143,7 @@ typedef struct HexagonCPUClass {
> >       DeviceReset parent_reset;
> >   } HexagonCPUClass;
> >
> > -typedef struct HexagonCPU {
> > +typedef struct ArchCPU {
> >       /*< private >*/
> >       CPUState parent_obj;
> >       /*< public >*/
> 
> There's still the typedef of ArchCPU below, which ought to be redundant
> now.
> It may or may not be less confusing to separate out the typedef for
> HexagonCPU.
> It definitely would be worthwhile to convert hexagon to
> OBJECT_DECLARE_TYPE (cc Taylor).

IIUC, the change to convert to OBJECT_DECLARE_TYPE would be
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index c068e219f1..3b636595a3 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -131,12 +131,7 @@ struct CPUHexagonState {
     VTCMStoreLog vtcm_log;
 };
 
-#define HEXAGON_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU)
-#define HEXAGON_CPU(obj) \
-    OBJECT_CHECK(HexagonCPU, (obj), TYPE_HEXAGON_CPU)
-#define HEXAGON_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(HexagonCPUClass, (obj), TYPE_HEXAGON_CPU)
+OBJECT_DECLARE_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
 
 typedef struct HexagonCPUClass {
     /*< private >*/

If that's correct, the typedef struct HexagonCPUClass should NOT change to typedef struct ArchCPU, and the typdef of ArchCPU below would stay.


So, If I submit the above as a standalone patch, then Philippe wouldn't need to modify target/hexagon/cpu.h.  Correct?

Thanks,
Taylor

Re: [PATCH 11/15] target: Use ArchCPU as interface to target CPU

[Richard Henderson]

On 2/11/22 04:35, Taylor Simpson wrote:
> -#define HEXAGON_CPU_CLASS(klass) \
> -    OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU)
> -#define HEXAGON_CPU(obj) \
> -    OBJECT_CHECK(HexagonCPU, (obj), TYPE_HEXAGON_CPU)
> -#define HEXAGON_CPU_GET_CLASS(obj) \
> -    OBJECT_GET_CLASS(HexagonCPUClass, (obj), TYPE_HEXAGON_CPU)
> +OBJECT_DECLARE_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
>   
>   typedef struct HexagonCPUClass {
>       /*< private >*/
> 
> If that's correct, the typedef struct HexagonCPUClass should NOT change to typedef struct ArchCPU, and the typdef of ArchCPU below would stay.


This is the change you'd make with the current state of the world, yes.


> So, If I submit the above as a standalone patch, then Philippe wouldn't need to modify target/hexagon/cpu.h.  Correct?

But no, Phil would need a change, because he introduces

typedef struct ArchCPU ArchCPU;

as a generic typedef very early.  You cannot then redefine

typedef struct HexagonCPU ArchCPU;

which means that we still have to rearrange the direction of to

typedef ArchCPU HexagonCPU;

etc.  But it's definitely a smaller change (and matches all of the other targets).

I do think that the conversion to OBJECT_DECLARE_TYPE should happen first, via whichever 
tree you choose.


r~

RE: [PATCH 11/15] target: Use ArchCPU as interface to target CPU

[Taylor Simpson]

> -----Original Message-----
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Thursday, February 10, 2022 7:22 PM
> To: Taylor Simpson <tsimpson@quicinc.com>; Philippe Mathieu-Daudé
> <f4bug@amsat.org>; qemu-devel@nongnu.org
> Cc: Paolo Bonzini <pbonzini@redhat.com>; Thomas Huth
> <thuth@redhat.com>
> Subject: Re: [PATCH 11/15] target: Use ArchCPU as interface to target CPU
> 
> On 2/11/22 04:35, Taylor Simpson wrote:
> > -#define HEXAGON_CPU_CLASS(klass) \
> > -    OBJECT_CLASS_CHECK(HexagonCPUClass, (klass),
> TYPE_HEXAGON_CPU)
> > -#define HEXAGON_CPU(obj) \
> > -    OBJECT_CHECK(HexagonCPU, (obj), TYPE_HEXAGON_CPU)
> > -#define HEXAGON_CPU_GET_CLASS(obj) \
> > -    OBJECT_GET_CLASS(HexagonCPUClass, (obj), TYPE_HEXAGON_CPU)
> > +OBJECT_DECLARE_TYPE(HexagonCPU, HexagonCPUClass,
> HEXAGON_CPU)
> >
> >   typedef struct HexagonCPUClass {
> >       /*< private >*/
> >
  But it's definitely a smaller change (and matches all of the other targets).
> 
> I do think that the conversion to OBJECT_DECLARE_TYPE should happen first,
> via whichever tree you choose.

OK, I'll send a patch.  Then, submit a pull request along with the other changes you just looked at.

Taylor

[RFC PATCH 12/15] hw/m68k: Restrict M68kCPU type to target/ code

[Philippe Mathieu-Daudé via]

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/m68k/mcf.h | 3 +--
 target/m68k/cpu-qom.h | 2 --
 target/m68k/cpu.h     | 4 ++--
 3 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h
index 8cbd587bbf..e84fcfb4ca 100644
--- a/include/hw/m68k/mcf.h
+++ b/include/hw/m68k/mcf.h
@@ -3,7 +3,6 @@
 /* Motorola ColdFire device prototypes.  */
 
 #include "exec/hwaddr.h"
-#include "target/m68k/cpu-qom.h"
 
 /* mcf_uart.c */
 uint64_t mcf_uart_read(void *opaque, hwaddr addr,
@@ -16,7 +15,7 @@ void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chr);
 /* mcf_intc.c */
 qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
                         hwaddr base,
-                        M68kCPU *cpu);
+                        ArchCPU *cpu);
 
 /* mcf5206.c */
 #define TYPE_MCF5206_MBAR "mcf5206-mbar"
diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index c2c0736b3b..ec75adad69 100644
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -25,8 +25,6 @@
 
 #define TYPE_M68K_CPU "m68k-cpu"
 
-typedef struct ArchCPU M68kCPU;
-
 OBJECT_DECLARE_TYPE(ArchCPU, M68kCPUClass,
                     M68K_CPU)
 
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 872e8ce637..90be69e714 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -156,14 +156,14 @@ typedef struct CPUArchState {
  *
  * A Motorola 68k CPU.
  */
-struct ArchCPU {
+typedef struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
 
     CPUNegativeOffsetState neg;
     CPUM68KState env;
-};
+} M68kCPU;
 
 
 #ifndef CONFIG_USER_ONLY
-- 
2.34.1

Re: [RFC PATCH 12/15] hw/m68k: Restrict M68kCPU type to target/ code

[Richard Henderson]

On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   include/hw/m68k/mcf.h | 3 +--
>   target/m68k/cpu-qom.h | 2 --
>   target/m68k/cpu.h     | 4 ++--
>   3 files changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h
> index 8cbd587bbf..e84fcfb4ca 100644
> --- a/include/hw/m68k/mcf.h
> +++ b/include/hw/m68k/mcf.h
> @@ -3,7 +3,6 @@
>   /* Motorola ColdFire device prototypes.  */
>   
>   #include "exec/hwaddr.h"
> -#include "target/m68k/cpu-qom.h"
>   
>   /* mcf_uart.c */
>   uint64_t mcf_uart_read(void *opaque, hwaddr addr,
> @@ -16,7 +15,7 @@ void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chr);
>   /* mcf_intc.c */
>   qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
>                           hwaddr base,
> -                        M68kCPU *cpu);
> +                        ArchCPU *cpu);
>   
>   /* mcf5206.c */
>   #define TYPE_MCF5206_MBAR "mcf5206-mbar"

This part is ok.

> diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
> index c2c0736b3b..ec75adad69 100644
> --- a/target/m68k/cpu-qom.h
> +++ b/target/m68k/cpu-qom.h
> @@ -25,8 +25,6 @@
>   
>   #define TYPE_M68K_CPU "m68k-cpu"
>   
> -typedef struct ArchCPU M68kCPU;
> -
>   OBJECT_DECLARE_TYPE(ArchCPU, M68kCPUClass,
>                       M68K_CPU)
>   
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index 872e8ce637..90be69e714 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -156,14 +156,14 @@ typedef struct CPUArchState {
>    *
>    * A Motorola 68k CPU.
>    */
> -struct ArchCPU {
> +typedef struct ArchCPU {
>       /*< private >*/
>       CPUState parent_obj;
>       /*< public >*/
>   
>       CPUNegativeOffsetState neg;
>       CPUM68KState env;
> -};
> +} M68kCPU;

I don't like these.  Rationale?


r~

Re: [RFC PATCH 12/15] hw/m68k: Restrict M68kCPU type to target/ code

[Philippe Mathieu-Daudé via]

On 9/2/22 23:50, Richard Henderson wrote:
> On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>>   include/hw/m68k/mcf.h | 3 +--
>>   target/m68k/cpu-qom.h | 2 --
>>   target/m68k/cpu.h     | 4 ++--
>>   3 files changed, 3 insertions(+), 6 deletions(-)
>>
>> diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h
>> index 8cbd587bbf..e84fcfb4ca 100644
>> --- a/include/hw/m68k/mcf.h
>> +++ b/include/hw/m68k/mcf.h
>> @@ -3,7 +3,6 @@
>>   /* Motorola ColdFire device prototypes.  */
>>   #include "exec/hwaddr.h"
>> -#include "target/m68k/cpu-qom.h"
>>   /* mcf_uart.c */
>>   uint64_t mcf_uart_read(void *opaque, hwaddr addr,
>> @@ -16,7 +15,7 @@ void mcf_uart_mm_init(hwaddr base, qemu_irq irq, 
>> Chardev *chr);
>>   /* mcf_intc.c */
>>   qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
>>                           hwaddr base,
>> -                        M68kCPU *cpu);
>> +                        ArchCPU *cpu);
>>   /* mcf5206.c */
>>   #define TYPE_MCF5206_MBAR "mcf5206-mbar"
> 
> This part is ok.
> 
>> diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
>> index c2c0736b3b..ec75adad69 100644
>> --- a/target/m68k/cpu-qom.h
>> +++ b/target/m68k/cpu-qom.h
>> @@ -25,8 +25,6 @@
>>   #define TYPE_M68K_CPU "m68k-cpu"
>> -typedef struct ArchCPU M68kCPU;
>> -
>>   OBJECT_DECLARE_TYPE(ArchCPU, M68kCPUClass,
>>                       M68K_CPU)
>> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
>> index 872e8ce637..90be69e714 100644
>> --- a/target/m68k/cpu.h
>> +++ b/target/m68k/cpu.h
>> @@ -156,14 +156,14 @@ typedef struct CPUArchState {
>>    *
>>    * A Motorola 68k CPU.
>>    */
>> -struct ArchCPU {
>> +typedef struct ArchCPU {
>>       /*< private >*/
>>       CPUState parent_obj;
>>       /*< public >*/
>>       CPUNegativeOffsetState neg;
>>       CPUM68KState env;
>> -};
>> +} M68kCPU;
> 
> I don't like these.  Rationale?

Short-term idea: hw/ models only have access to cpu-qom.h declarations
and opaque pointers to generic CPU objects.

hw/ should not include cpu.h at all. By restricting FooCPU to target/
code, hw/ files fail to compile if using FooCPU and not ArchCPU.


Long-term idea, each target/ is built as a module, exposing an uniform
arch-API.

I'm still prototyping to see how to disentangle arch-specific hw which
access CPU internals (such ARM NVIC or MIPS ITU).

Re: [RFC PATCH 12/15] hw/m68k: Restrict M68kCPU type to target/ code

[Richard Henderson]

On 2/10/22 10:09, Philippe Mathieu-Daudé wrote:
> On 9/2/22 23:50, Richard Henderson wrote:
>> On 2/10/22 08:54, Philippe Mathieu-Daudé wrote:
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>> ---
>>>   include/hw/m68k/mcf.h | 3 +--
>>>   target/m68k/cpu-qom.h | 2 --
>>>   target/m68k/cpu.h     | 4 ++--
>>>   3 files changed, 3 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h
>>> index 8cbd587bbf..e84fcfb4ca 100644
>>> --- a/include/hw/m68k/mcf.h
>>> +++ b/include/hw/m68k/mcf.h
>>> @@ -3,7 +3,6 @@
>>>   /* Motorola ColdFire device prototypes.  */
>>>   #include "exec/hwaddr.h"
>>> -#include "target/m68k/cpu-qom.h"
>>>   /* mcf_uart.c */
>>>   uint64_t mcf_uart_read(void *opaque, hwaddr addr,
>>> @@ -16,7 +15,7 @@ void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chr);
>>>   /* mcf_intc.c */
>>>   qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
>>>                           hwaddr base,
>>> -                        M68kCPU *cpu);
>>> +                        ArchCPU *cpu);
>>>   /* mcf5206.c */
>>>   #define TYPE_MCF5206_MBAR "mcf5206-mbar"
>>
>> This part is ok.
>>
>>> diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
>>> index c2c0736b3b..ec75adad69 100644
>>> --- a/target/m68k/cpu-qom.h
>>> +++ b/target/m68k/cpu-qom.h
>>> @@ -25,8 +25,6 @@
>>>   #define TYPE_M68K_CPU "m68k-cpu"
>>> -typedef struct ArchCPU M68kCPU;
>>> -
>>>   OBJECT_DECLARE_TYPE(ArchCPU, M68kCPUClass,
>>>                       M68K_CPU)
>>> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
>>> index 872e8ce637..90be69e714 100644
>>> --- a/target/m68k/cpu.h
>>> +++ b/target/m68k/cpu.h
>>> @@ -156,14 +156,14 @@ typedef struct CPUArchState {
>>>    *
>>>    * A Motorola 68k CPU.
>>>    */
>>> -struct ArchCPU {
>>> +typedef struct ArchCPU {
>>>       /*< private >*/
>>>       CPUState parent_obj;
>>>       /*< public >*/
>>>       CPUNegativeOffsetState neg;
>>>       CPUM68KState env;
>>> -};
>>> +} M68kCPU;
>>
>> I don't like these.  Rationale?
> 
> Short-term idea: hw/ models only have access to cpu-qom.h declarations
> and opaque pointers to generic CPU objects.
> 
> hw/ should not include cpu.h at all. By restricting FooCPU to target/
> code, hw/ files fail to compile if using FooCPU and not ArchCPU.

Yes, that would be ideal.  If you do want to bring the typedef into cpu.h, please keep it 
separate; it's easier to read.  Especially since one normally expects

typedef struct Foo {
   ...
} Foo;

and that's not what's happening here.

> Long-term idea, each target/ is built as a module, exposing an uniform
> arch-API.

That would be awesome, yes.

> I'm still prototyping to see how to disentangle arch-specific hw which
> access CPU internals (such ARM NVIC or MIPS ITU).

Complicated, yes.  If it comes to it, I would not be opposed to having these tightly 
coupled devices live in target/, but let's see if you can avoid it.


r~

[RFC PATCH 13/15] hw/mips: Restrict MIPSCPU type to target/ code

[Philippe Mathieu-Daudé via]

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/mips/cpudevs.h | 6 ++----
 target/mips/cpu-qom.h     | 2 --
 target/mips/cpu.h         | 4 ++--
 3 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h
index f7c9728fa9..6065932b0e 100644
--- a/include/hw/mips/cpudevs.h
+++ b/include/hw/mips/cpudevs.h
@@ -1,14 +1,12 @@
 #ifndef HW_MIPS_CPUDEVS_H
 #define HW_MIPS_CPUDEVS_H
 
-#include "target/mips/cpu-qom.h"
-
 /* Definitions for MIPS CPU internal devices.  */
 
 /* mips_int.c */
-void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
+void cpu_mips_irq_init_cpu(ArchCPU *cpu);
 
 /* mips_timer.c */
-void cpu_mips_clock_init(MIPSCPU *cpu);
+void cpu_mips_clock_init(ArchCPU *cpu);
 
 #endif
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 41f3d01a80..666084b09e 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -29,8 +29,6 @@
 #define TYPE_MIPS_CPU "mips-cpu"
 #endif
 
-typedef struct ArchCPU MIPSCPU;
-
 OBJECT_DECLARE_TYPE(ArchCPU, MIPSCPUClass,
                     MIPS_CPU)
 
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 09e98f64de..4aa95d0ce1 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1171,7 +1171,7 @@ typedef struct CPUArchState {
  *
  * A MIPS CPU.
  */
-struct ArchCPU {
+typedef struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -1187,7 +1187,7 @@ struct ArchCPU {
      * pipeline clock of the processor, not the issue width of the processor.
      */
     unsigned cp0_count_rate;
-};
+} MIPSCPU;
 
 
 void mips_cpu_list(void);
-- 
2.34.1

[RFC PATCH 14/15] hw/sparc: Restrict SPARCCPU type to target/ code

[Philippe Mathieu-Daudé via]

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/sparc/sparc64.h | 4 +---
 target/sparc/cpu-qom.h     | 2 --
 target/sparc/cpu.h         | 4 ++--
 3 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/include/hw/sparc/sparc64.h b/include/hw/sparc/sparc64.h
index 4ced36fb5a..605ae4448c 100644
--- a/include/hw/sparc/sparc64.h
+++ b/include/hw/sparc/sparc64.h
@@ -1,11 +1,9 @@
 #ifndef HW_SPARC_SPARC64_H
 #define HW_SPARC_SPARC64_H
 
-#include "target/sparc/cpu-qom.h"
-
 #define IVEC_MAX             0x40
 
-SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr);
+ArchCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr);
 
 void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level);
 
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index d5f90cffd4..36ffffcadd 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -29,8 +29,6 @@
 #define TYPE_SPARC_CPU "sparc-cpu"
 #endif
 
-typedef struct ArchCPU SPARCCPU;
-
 OBJECT_DECLARE_TYPE(ArchCPU, SPARCCPUClass,
                     SPARC_CPU)
 
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index abb38db674..8452a62ea8 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -556,14 +556,14 @@ struct CPUArchState {
  *
  * A SPARC CPU.
  */
-struct ArchCPU {
+typedef struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
 
     CPUNegativeOffsetState neg;
     CPUSPARCState env;
-};
+} SPARCCPU;
 
 
 #ifndef CONFIG_USER_ONLY
-- 
2.34.1

[RFC PATCH 15/15] hw/sh4: Restrict SuperHCPU type to target/ code

[Philippe Mathieu-Daudé via]

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/sh4/sh.h  | 3 +--
 target/sh4/cpu-qom.h | 2 --
 target/sh4/cpu.h     | 4 ++--
 3 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h
index ec716cdd45..a4245399d5 100644
--- a/include/hw/sh4/sh.h
+++ b/include/hw/sh4/sh.h
@@ -28,7 +28,6 @@
 #define QEMU_HW_SH_H
 
 #include "hw/sh4/sh_intc.h"
-#include "target/sh4/cpu-qom.h"
 
 #define A7ADDR(x) ((x) & 0x1fffffff)
 #define P4ADDR(x) ((x) | 0xe0000000)
@@ -36,7 +35,7 @@
 /* sh7750.c */
 struct SH7750State;
 
-struct SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem);
+struct SH7750State *sh7750_init(ArchCPU *cpu, MemoryRegion *sysmem);
 
 typedef struct {
     /* The callback will be triggered if any of the designated lines change */
diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index 64be55a924..d186ad40fa 100644
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -29,8 +29,6 @@
 #define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r")
 #define TYPE_SH7785_CPU  SUPERH_CPU_TYPE_NAME("sh7785")
 
-typedef struct ArchCPU SuperHCPU;
-
 OBJECT_DECLARE_TYPE(ArchCPU, SuperHCPUClass,
                     SUPERH_CPU)
 
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index c72a30edfd..8e49163fb3 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -195,14 +195,14 @@ typedef struct CPUArchState {
  *
  * A SuperH CPU.
  */
-struct ArchCPU {
+typedef struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
 
     CPUNegativeOffsetState neg;
     CPUSH4State env;
-};
+} SuperHCPU;
 
 
 void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
-- 
2.34.1