From: "Marek Behún" <kabel@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <helgaas@kernel.org> Cc: "Krzysztof Wilczyński" <kw@linux.com>, "Marc Zyngier" <maz@kernel.org>, pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Gregory CLEMENT" <gregory.clement@bootlin.com>, "Russell King" <rmk+kernel@armlinux.org.uk>, "Marek Behún" <kabel@kernel.org> Subject: [PATCH 01/18] PCI: pci-bridge-emul: Re-arrange register tests Date: Sun, 20 Feb 2022 20:33:29 +0100 [thread overview] Message-ID: <20220220193346.23789-2-kabel@kernel.org> (raw) In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> From: Russell King <rmk+kernel@armlinux.org.uk> Re-arrange the tests for which sets of registers are being accessed so that it is easier to add further regions later. No functional change. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> [pali: Fix reading old value in pci_bridge_emul_conf_write] Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/pci/pci-bridge-emul.c | 61 ++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 30 deletions(-) diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c index a16f9e30099e..a956408834d6 100644 --- a/drivers/pci/pci-bridge-emul.c +++ b/drivers/pci/pci-bridge-emul.c @@ -422,25 +422,25 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, __le32 *cfgspace; const struct pci_bridge_reg_behavior *behavior; - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) { - *value = 0; - return PCIBIOS_SUCCESSFUL; - } - - if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) { + if (reg < PCI_BRIDGE_CONF_END) { + /* Emulated PCI space */ + read_op = bridge->ops->read_base; + cfgspace = (__le32 *) &bridge->conf; + behavior = bridge->pci_regs_behavior; + } else if (!bridge->has_pcie) { + /* PCIe space is not implemented, and no PCI capabilities */ *value = 0; return PCIBIOS_SUCCESSFUL; - } - - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { + } else if (reg < PCI_CAP_PCIE_END) { + /* Our emulated PCIe capability */ reg -= PCI_CAP_PCIE_START; read_op = bridge->ops->read_pcie; cfgspace = (__le32 *) &bridge->pcie_conf; behavior = bridge->pcie_cap_regs_behavior; } else { - read_op = bridge->ops->read_base; - cfgspace = (__le32 *) &bridge->conf; - behavior = bridge->pci_regs_behavior; + /* Beyond our PCIe space */ + *value = 0; + return PCIBIOS_SUCCESSFUL; } if (read_op) @@ -484,11 +484,27 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, __le32 *cfgspace; const struct pci_bridge_reg_behavior *behavior; - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) - return PCIBIOS_SUCCESSFUL; + ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; - if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) + if (reg < PCI_BRIDGE_CONF_END) { + /* Emulated PCI space */ + write_op = bridge->ops->write_base; + cfgspace = (__le32 *) &bridge->conf; + behavior = bridge->pci_regs_behavior; + } else if (!bridge->has_pcie) { + /* PCIe space is not implemented, and no PCI capabilities */ return PCIBIOS_SUCCESSFUL; + } else if (reg < PCI_CAP_PCIE_END) { + /* Our emulated PCIe capability */ + reg -= PCI_CAP_PCIE_START; + write_op = bridge->ops->write_pcie; + cfgspace = (__le32 *) &bridge->pcie_conf; + behavior = bridge->pcie_cap_regs_behavior; + } else { + return PCIBIOS_SUCCESSFUL; + } shift = (where & 0x3) * 8; @@ -501,21 +517,6 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, else return PCIBIOS_BAD_REGISTER_NUMBER; - ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); - if (ret != PCIBIOS_SUCCESSFUL) - return ret; - - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { - reg -= PCI_CAP_PCIE_START; - write_op = bridge->ops->write_pcie; - cfgspace = (__le32 *) &bridge->pcie_conf; - behavior = bridge->pcie_cap_regs_behavior; - } else { - write_op = bridge->ops->write_base; - cfgspace = (__le32 *) &bridge->conf; - behavior = bridge->pci_regs_behavior; - } - /* Keep all bits, except the RW bits */ new = old & (~mask | ~behavior[reg / 4].rw); -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: "Marek Behún" <kabel@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <helgaas@kernel.org> Cc: "Krzysztof Wilczyński" <kw@linux.com>, "Marc Zyngier" <maz@kernel.org>, pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Gregory CLEMENT" <gregory.clement@bootlin.com>, "Russell King" <rmk+kernel@armlinux.org.uk>, "Marek Behún" <kabel@kernel.org> Subject: [PATCH 01/18] PCI: pci-bridge-emul: Re-arrange register tests Date: Sun, 20 Feb 2022 20:33:29 +0100 [thread overview] Message-ID: <20220220193346.23789-2-kabel@kernel.org> (raw) In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> From: Russell King <rmk+kernel@armlinux.org.uk> Re-arrange the tests for which sets of registers are being accessed so that it is easier to add further regions later. No functional change. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> [pali: Fix reading old value in pci_bridge_emul_conf_write] Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/pci/pci-bridge-emul.c | 61 ++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 30 deletions(-) diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c index a16f9e30099e..a956408834d6 100644 --- a/drivers/pci/pci-bridge-emul.c +++ b/drivers/pci/pci-bridge-emul.c @@ -422,25 +422,25 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, __le32 *cfgspace; const struct pci_bridge_reg_behavior *behavior; - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) { - *value = 0; - return PCIBIOS_SUCCESSFUL; - } - - if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) { + if (reg < PCI_BRIDGE_CONF_END) { + /* Emulated PCI space */ + read_op = bridge->ops->read_base; + cfgspace = (__le32 *) &bridge->conf; + behavior = bridge->pci_regs_behavior; + } else if (!bridge->has_pcie) { + /* PCIe space is not implemented, and no PCI capabilities */ *value = 0; return PCIBIOS_SUCCESSFUL; - } - - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { + } else if (reg < PCI_CAP_PCIE_END) { + /* Our emulated PCIe capability */ reg -= PCI_CAP_PCIE_START; read_op = bridge->ops->read_pcie; cfgspace = (__le32 *) &bridge->pcie_conf; behavior = bridge->pcie_cap_regs_behavior; } else { - read_op = bridge->ops->read_base; - cfgspace = (__le32 *) &bridge->conf; - behavior = bridge->pci_regs_behavior; + /* Beyond our PCIe space */ + *value = 0; + return PCIBIOS_SUCCESSFUL; } if (read_op) @@ -484,11 +484,27 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, __le32 *cfgspace; const struct pci_bridge_reg_behavior *behavior; - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) - return PCIBIOS_SUCCESSFUL; + ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; - if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) + if (reg < PCI_BRIDGE_CONF_END) { + /* Emulated PCI space */ + write_op = bridge->ops->write_base; + cfgspace = (__le32 *) &bridge->conf; + behavior = bridge->pci_regs_behavior; + } else if (!bridge->has_pcie) { + /* PCIe space is not implemented, and no PCI capabilities */ return PCIBIOS_SUCCESSFUL; + } else if (reg < PCI_CAP_PCIE_END) { + /* Our emulated PCIe capability */ + reg -= PCI_CAP_PCIE_START; + write_op = bridge->ops->write_pcie; + cfgspace = (__le32 *) &bridge->pcie_conf; + behavior = bridge->pcie_cap_regs_behavior; + } else { + return PCIBIOS_SUCCESSFUL; + } shift = (where & 0x3) * 8; @@ -501,21 +517,6 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, else return PCIBIOS_BAD_REGISTER_NUMBER; - ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); - if (ret != PCIBIOS_SUCCESSFUL) - return ret; - - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { - reg -= PCI_CAP_PCIE_START; - write_op = bridge->ops->write_pcie; - cfgspace = (__le32 *) &bridge->pcie_conf; - behavior = bridge->pcie_cap_regs_behavior; - } else { - write_op = bridge->ops->write_base; - cfgspace = (__le32 *) &bridge->conf; - behavior = bridge->pci_regs_behavior; - } - /* Keep all bits, except the RW bits */ new = old & (~mask | ~behavior[reg / 4].rw); -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-02-20 19:33 UTC|newest] Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-20 19:33 [PATCH 00/18] PCI: aardvark controller changes BATCH 5 Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` Marek Behún [this message] 2022-02-20 19:33 ` [PATCH 01/18] PCI: pci-bridge-emul: Re-arrange register tests Marek Behún 2022-02-20 19:33 ` [PATCH 02/18] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 03/18] PCI: aardvark: Add support for AER registers on emulated bridge Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 04/18] PCI: Add PCI_EXP_SLTCAP_*_SHIFT macros Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-28 11:09 ` Lorenzo Pieralisi 2022-04-28 11:09 ` Lorenzo Pieralisi 2022-04-28 11:16 ` Pali Rohár 2022-04-28 11:16 ` Pali Rohár 2022-05-18 19:23 ` Bjorn Helgaas 2022-05-18 19:23 ` Bjorn Helgaas 2022-05-18 19:26 ` Pali Rohár 2022-05-18 19:26 ` Pali Rohár 2022-05-18 20:05 ` Marek Behún 2022-05-18 20:05 ` Marek Behún 2022-05-18 20:27 ` Bjorn Helgaas 2022-05-18 20:27 ` Bjorn Helgaas 2022-02-20 19:33 ` [PATCH 05/18] PCI: aardvark: Fix reporting Slot capabilities on emulated bridge Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 06/18] PCI: pciehp: Enable DLLSC interrupt only if supported Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-05-09 3:42 ` Lukas Wunner 2022-05-13 16:57 ` Pali Rohár 2022-05-13 16:57 ` Pali Rohár 2022-05-14 9:14 ` Lukas Wunner 2022-08-18 12:22 ` Marek Behún 2022-08-18 12:22 ` Marek Behún 2022-02-20 19:33 ` [PATCH 07/18] PCI: pciehp: Enable Command Completed Interrupt " Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-05-09 4:01 ` Lukas Wunner 2022-05-13 16:59 ` Pali Rohár 2022-05-13 16:59 ` Pali Rohár 2022-02-20 19:33 ` [PATCH 08/18] PCI: aardvark: Add support for DLLSC and hotplug interrupt Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 09/18] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 10/18] PCI: Add function for parsing `slot-power-limit-milliwatt` DT property Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 11/18] dt-bindings: PCI: aardvark: Describe slot-power-limit-milliwatt Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 12/18] PCI: aardvark: Send Set_Slot_Power_Limit message Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 13/18] arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 14/18] PCI: aardvark: Add clock support Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 15/18] arm64: dts: marvell: armada-37xx: Add clock to PCIe node Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-28 15:52 ` Gregory CLEMENT 2022-02-28 15:52 ` Gregory CLEMENT 2022-02-20 19:33 ` [PATCH 16/18] PCI: aardvark: Add suspend to RAM support Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-12 11:14 ` Lorenzo Pieralisi 2022-04-12 11:14 ` Lorenzo Pieralisi 2022-02-20 19:33 ` [PATCH 17/18] PCI: aardvark: Run link training in separate worker Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-12 15:25 ` Lorenzo Pieralisi 2022-04-12 15:25 ` Lorenzo Pieralisi 2022-04-12 17:55 ` Pali Rohár 2022-04-12 17:55 ` Pali Rohár 2022-04-13 9:16 ` Lorenzo Pieralisi 2022-04-13 9:16 ` Lorenzo Pieralisi 2022-05-04 14:02 ` Marek Behún 2022-05-04 14:02 ` Marek Behún 2022-02-20 19:33 ` [PATCH 18/18] PCI: aardvark: Optimize PCIe card reset via GPIO Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-11 15:36 ` [PATCH 00/18] PCI: aardvark controller changes BATCH 5 Lorenzo Pieralisi 2022-04-11 15:36 ` Lorenzo Pieralisi 2022-04-11 16:53 ` Pali Rohár 2022-04-11 16:53 ` Pali Rohár 2022-05-13 10:33 ` Lorenzo Pieralisi 2022-05-13 10:33 ` Lorenzo Pieralisi 2022-05-13 16:48 ` Pali Rohár 2022-05-13 16:48 ` Pali Rohár 2022-05-18 15:54 ` (subset) " Lorenzo Pieralisi 2022-05-18 15:54 ` Lorenzo Pieralisi 2022-08-16 16:25 ` Lorenzo Pieralisi 2022-08-16 16:25 ` Lorenzo Pieralisi 2022-08-18 13:56 ` Marek Behún 2022-08-18 13:56 ` Marek Behún
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