From: "Marek Behún" <kabel@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <helgaas@kernel.org> Cc: "Krzysztof Wilczyński" <kw@linux.com>, "Marc Zyngier" <maz@kernel.org>, pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Gregory CLEMENT" <gregory.clement@bootlin.com>, "Marek Behún" <kabel@kernel.org> Subject: [PATCH 08/18] PCI: aardvark: Add support for DLLSC and hotplug interrupt Date: Sun, 20 Feb 2022 20:33:36 +0100 [thread overview] Message-ID: <20220220193346.23789-9-kabel@kernel.org> (raw) In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> From: Pali Rohár <pali@kernel.org> Add support for Data Link Layer State Change in the emulated slot registers and hotplug interrupt via the emulated root bridge. Link down state change can be implemented because Aardvark supports Link Down event interrupt. Use it for signaling that Data Link Layer Link is not active anymore via Hot-Plug Interrupt on emulated root bridge. Link up interrupt is not available on Aardvark, but we check for whether link is up in the advk_pcie_link_up() function. By triggering Hot-Plug Interrupt from this function we achieve Link up event, so long as the function is called (which it is after probe and when rescanning). Although it is not ideal, it is better than nothing. Since advk_pcie_link_up() is not called from interrupt handler, we cannot call generic_handle_domain_irq() from it directly. Instead create a TIMER_IRQSAFE timer and trigger it from advk_pcie_link_up(). (We haven't been able to find any documentation for a Link Up interrupt on Aardvark, but it is possible there is one, in some undocumented register. If we manage to find this information, this can be rewritten.) Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/pci/controller/pci-aardvark.c | 100 ++++++++++++++++++++++++-- 1 file changed, 96 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index c80c78505bfa..62bb0308b9f7 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -24,6 +24,7 @@ #include <linux/of_address.h> #include <linux/of_gpio.h> #include <linux/of_pci.h> +#include <linux/timer.h> #include "../pci.h" #include "../pci-bridge-emul.h" @@ -99,6 +100,7 @@ #define PCIE_MSG_PM_PME_MASK BIT(7) #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) #define PCIE_ISR0_MSI_INT_PENDING BIT(24) +#define PCIE_ISR0_LINK_DOWN BIT(1) #define PCIE_ISR0_CORR_ERR BIT(11) #define PCIE_ISR0_NFAT_ERR BIT(12) #define PCIE_ISR0_FAT_ERR BIT(13) @@ -284,6 +286,8 @@ struct advk_pcie { DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; int link_gen; + bool link_was_up; + struct timer_list link_irq_timer; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; struct phy *phy; @@ -313,7 +317,24 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) { /* check if LTSSM is in normal operation - some L* state */ u8 ltssm_state = advk_pcie_ltssm_state(pcie); - return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; + bool link_is_up; + u16 slotsta; + + link_is_up = ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; + + if (link_is_up && !pcie->link_was_up) { + dev_info(&pcie->pdev->dev, "link up\n"); + + pcie->link_was_up = true; + + slotsta = le16_to_cpu(pcie->bridge.pcie_conf.slotsta); + slotsta |= PCI_EXP_SLTSTA_DLLSC; + pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); + + mod_timer(&pcie->link_irq_timer, jiffies + 1); + } + + return link_is_up; } static inline bool advk_pcie_link_active(struct advk_pcie *pcie) @@ -442,8 +463,6 @@ static void advk_pcie_train_link(struct advk_pcie *pcie) ret = advk_pcie_wait_for_link(pcie); if (ret < 0) dev_err(dev, "link never came up\n"); - else - dev_info(dev, "link up\n"); } /* @@ -592,6 +611,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg &= ~PCIE_ISR0_MSI_INT_PENDING; advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); + /* Unmask Link Down interrupt */ + reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); + reg &= ~PCIE_ISR0_LINK_DOWN; + advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); + /* Unmask PME interrupt for processing of PME requester */ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); reg &= ~PCIE_MSG_PM_PME_MASK; @@ -918,6 +942,14 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, advk_pcie_wait_for_retrain(pcie); break; + case PCI_EXP_SLTCTL: { + u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); + /* Only emulation of HPIE and DLLSCE bits is provided */ + slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; + bridge->pcie_conf.slotctl = cpu_to_le16(slotctl); + break; + } + case PCI_EXP_RTCTL: { u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); /* Only emulation of PMEIE and CRSSVE bits is provided */ @@ -1033,6 +1065,7 @@ static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) { struct pci_bridge_emul *bridge = &pcie->bridge; + u32 slotcap; bridge->conf.vendor = cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); @@ -1059,6 +1092,13 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT); /* + * Mark bridge as Hot Plug Capable since this is the way how to enable + * delivering of Data Link Layer State Change interrupts. + * + * Set No Command Completed Support because bridge does not support + * Command Completed Interrupt. Every command is executed immediately + * without any delay. + * * Set Presence Detect State bit permanently since there is no support * for unplugging the card nor detecting whether it is plugged. (If a * platform exists in the future that supports it, via a GPIO for @@ -1068,7 +1108,9 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) * value is reserved for ports within the same silicon as Root Port * which is not our case. */ - bridge->pcie_conf.slotcap = cpu_to_le32(1 << PCI_EXP_SLTCAP_PSN_SHIFT); + slotcap = PCI_EXP_SLTCAP_NCCS | PCI_EXP_SLTCAP_HPC | + (1 << PCI_EXP_SLTCAP_PSN_SHIFT); + bridge->pcie_conf.slotcap = cpu_to_le32(slotcap); bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); /* Indicates supports for Completion Retry Status */ @@ -1565,6 +1607,24 @@ static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie) irq_domain_remove(pcie->rp_irq_domain); } +static void advk_pcie_link_irq_handler(struct timer_list *timer) +{ + struct advk_pcie *pcie = from_timer(pcie, timer, link_irq_timer); + u16 slotctl; + + slotctl = le16_to_cpu(pcie->bridge.pcie_conf.slotctl); + if (!(slotctl & PCI_EXP_SLTCTL_DLLSCE) || + !(slotctl & PCI_EXP_SLTCTL_HPIE)) + return; + + /* + * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe + * interrupt 0 + */ + if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) + dev_err_ratelimited(&pcie->pdev->dev, "unhandled HP IRQ\n"); +} + static void advk_pcie_handle_pme(struct advk_pcie *pcie) { u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; @@ -1616,6 +1676,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) { u32 isr0_val, isr0_mask, isr0_status; u32 isr1_val, isr1_mask, isr1_status; + u16 slotsta; int i; isr0_val = advk_readl(pcie, PCIE_ISR0_REG); @@ -1642,6 +1703,26 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); } + /* Process Link Down interrupt as HP IRQ */ + if (isr0_status & PCIE_ISR0_LINK_DOWN) { + advk_writel(pcie, PCIE_ISR0_LINK_DOWN, PCIE_ISR0_REG); + + dev_info(&pcie->pdev->dev, "link down\n"); + + pcie->link_was_up = false; + + slotsta = le16_to_cpu(pcie->bridge.pcie_conf.slotsta); + slotsta |= PCI_EXP_SLTSTA_DLLSC; + pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); + + /* + * Deactivate timer and call advk_pcie_link_irq_handler() + * function directly as we are in the interrupt context. + */ + del_timer_sync(&pcie->link_irq_timer); + advk_pcie_link_irq_handler(&pcie->link_irq_timer); + } + /* Process MSI interrupts */ if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) advk_pcie_handle_msi(pcie); @@ -1877,6 +1958,14 @@ static int advk_pcie_probe(struct platform_device *pdev) if (ret) return ret; + /* + * generic_handle_domain_irq() expects local IRQs to be disabled since + * normally it is called from interrupt context, so use TIMER_IRQSAFE + * flag for this link_irq_timer. + */ + timer_setup(&pcie->link_irq_timer, advk_pcie_link_irq_handler, + TIMER_IRQSAFE); + advk_pcie_setup_hw(pcie); ret = advk_sw_pci_bridge_init(pcie); @@ -1971,6 +2060,9 @@ static int advk_pcie_remove(struct platform_device *pdev) advk_pcie_remove_msi_irq_domain(pcie); advk_pcie_remove_irq_domain(pcie); + /* Deactivate link event timer */ + del_timer_sync(&pcie->link_irq_timer); + /* Free config space for emulated root bridge */ pci_bridge_emul_cleanup(&pcie->bridge); -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: "Marek Behún" <kabel@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <helgaas@kernel.org> Cc: "Krzysztof Wilczyński" <kw@linux.com>, "Marc Zyngier" <maz@kernel.org>, pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Gregory CLEMENT" <gregory.clement@bootlin.com>, "Marek Behún" <kabel@kernel.org> Subject: [PATCH 08/18] PCI: aardvark: Add support for DLLSC and hotplug interrupt Date: Sun, 20 Feb 2022 20:33:36 +0100 [thread overview] Message-ID: <20220220193346.23789-9-kabel@kernel.org> (raw) In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> From: Pali Rohár <pali@kernel.org> Add support for Data Link Layer State Change in the emulated slot registers and hotplug interrupt via the emulated root bridge. Link down state change can be implemented because Aardvark supports Link Down event interrupt. Use it for signaling that Data Link Layer Link is not active anymore via Hot-Plug Interrupt on emulated root bridge. Link up interrupt is not available on Aardvark, but we check for whether link is up in the advk_pcie_link_up() function. By triggering Hot-Plug Interrupt from this function we achieve Link up event, so long as the function is called (which it is after probe and when rescanning). Although it is not ideal, it is better than nothing. Since advk_pcie_link_up() is not called from interrupt handler, we cannot call generic_handle_domain_irq() from it directly. Instead create a TIMER_IRQSAFE timer and trigger it from advk_pcie_link_up(). (We haven't been able to find any documentation for a Link Up interrupt on Aardvark, but it is possible there is one, in some undocumented register. If we manage to find this information, this can be rewritten.) Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/pci/controller/pci-aardvark.c | 100 ++++++++++++++++++++++++-- 1 file changed, 96 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index c80c78505bfa..62bb0308b9f7 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -24,6 +24,7 @@ #include <linux/of_address.h> #include <linux/of_gpio.h> #include <linux/of_pci.h> +#include <linux/timer.h> #include "../pci.h" #include "../pci-bridge-emul.h" @@ -99,6 +100,7 @@ #define PCIE_MSG_PM_PME_MASK BIT(7) #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) #define PCIE_ISR0_MSI_INT_PENDING BIT(24) +#define PCIE_ISR0_LINK_DOWN BIT(1) #define PCIE_ISR0_CORR_ERR BIT(11) #define PCIE_ISR0_NFAT_ERR BIT(12) #define PCIE_ISR0_FAT_ERR BIT(13) @@ -284,6 +286,8 @@ struct advk_pcie { DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; int link_gen; + bool link_was_up; + struct timer_list link_irq_timer; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; struct phy *phy; @@ -313,7 +317,24 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) { /* check if LTSSM is in normal operation - some L* state */ u8 ltssm_state = advk_pcie_ltssm_state(pcie); - return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; + bool link_is_up; + u16 slotsta; + + link_is_up = ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; + + if (link_is_up && !pcie->link_was_up) { + dev_info(&pcie->pdev->dev, "link up\n"); + + pcie->link_was_up = true; + + slotsta = le16_to_cpu(pcie->bridge.pcie_conf.slotsta); + slotsta |= PCI_EXP_SLTSTA_DLLSC; + pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); + + mod_timer(&pcie->link_irq_timer, jiffies + 1); + } + + return link_is_up; } static inline bool advk_pcie_link_active(struct advk_pcie *pcie) @@ -442,8 +463,6 @@ static void advk_pcie_train_link(struct advk_pcie *pcie) ret = advk_pcie_wait_for_link(pcie); if (ret < 0) dev_err(dev, "link never came up\n"); - else - dev_info(dev, "link up\n"); } /* @@ -592,6 +611,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg &= ~PCIE_ISR0_MSI_INT_PENDING; advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); + /* Unmask Link Down interrupt */ + reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); + reg &= ~PCIE_ISR0_LINK_DOWN; + advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); + /* Unmask PME interrupt for processing of PME requester */ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); reg &= ~PCIE_MSG_PM_PME_MASK; @@ -918,6 +942,14 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, advk_pcie_wait_for_retrain(pcie); break; + case PCI_EXP_SLTCTL: { + u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); + /* Only emulation of HPIE and DLLSCE bits is provided */ + slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; + bridge->pcie_conf.slotctl = cpu_to_le16(slotctl); + break; + } + case PCI_EXP_RTCTL: { u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); /* Only emulation of PMEIE and CRSSVE bits is provided */ @@ -1033,6 +1065,7 @@ static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) { struct pci_bridge_emul *bridge = &pcie->bridge; + u32 slotcap; bridge->conf.vendor = cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); @@ -1059,6 +1092,13 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT); /* + * Mark bridge as Hot Plug Capable since this is the way how to enable + * delivering of Data Link Layer State Change interrupts. + * + * Set No Command Completed Support because bridge does not support + * Command Completed Interrupt. Every command is executed immediately + * without any delay. + * * Set Presence Detect State bit permanently since there is no support * for unplugging the card nor detecting whether it is plugged. (If a * platform exists in the future that supports it, via a GPIO for @@ -1068,7 +1108,9 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) * value is reserved for ports within the same silicon as Root Port * which is not our case. */ - bridge->pcie_conf.slotcap = cpu_to_le32(1 << PCI_EXP_SLTCAP_PSN_SHIFT); + slotcap = PCI_EXP_SLTCAP_NCCS | PCI_EXP_SLTCAP_HPC | + (1 << PCI_EXP_SLTCAP_PSN_SHIFT); + bridge->pcie_conf.slotcap = cpu_to_le32(slotcap); bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); /* Indicates supports for Completion Retry Status */ @@ -1565,6 +1607,24 @@ static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie) irq_domain_remove(pcie->rp_irq_domain); } +static void advk_pcie_link_irq_handler(struct timer_list *timer) +{ + struct advk_pcie *pcie = from_timer(pcie, timer, link_irq_timer); + u16 slotctl; + + slotctl = le16_to_cpu(pcie->bridge.pcie_conf.slotctl); + if (!(slotctl & PCI_EXP_SLTCTL_DLLSCE) || + !(slotctl & PCI_EXP_SLTCTL_HPIE)) + return; + + /* + * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe + * interrupt 0 + */ + if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) + dev_err_ratelimited(&pcie->pdev->dev, "unhandled HP IRQ\n"); +} + static void advk_pcie_handle_pme(struct advk_pcie *pcie) { u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; @@ -1616,6 +1676,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) { u32 isr0_val, isr0_mask, isr0_status; u32 isr1_val, isr1_mask, isr1_status; + u16 slotsta; int i; isr0_val = advk_readl(pcie, PCIE_ISR0_REG); @@ -1642,6 +1703,26 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); } + /* Process Link Down interrupt as HP IRQ */ + if (isr0_status & PCIE_ISR0_LINK_DOWN) { + advk_writel(pcie, PCIE_ISR0_LINK_DOWN, PCIE_ISR0_REG); + + dev_info(&pcie->pdev->dev, "link down\n"); + + pcie->link_was_up = false; + + slotsta = le16_to_cpu(pcie->bridge.pcie_conf.slotsta); + slotsta |= PCI_EXP_SLTSTA_DLLSC; + pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); + + /* + * Deactivate timer and call advk_pcie_link_irq_handler() + * function directly as we are in the interrupt context. + */ + del_timer_sync(&pcie->link_irq_timer); + advk_pcie_link_irq_handler(&pcie->link_irq_timer); + } + /* Process MSI interrupts */ if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) advk_pcie_handle_msi(pcie); @@ -1877,6 +1958,14 @@ static int advk_pcie_probe(struct platform_device *pdev) if (ret) return ret; + /* + * generic_handle_domain_irq() expects local IRQs to be disabled since + * normally it is called from interrupt context, so use TIMER_IRQSAFE + * flag for this link_irq_timer. + */ + timer_setup(&pcie->link_irq_timer, advk_pcie_link_irq_handler, + TIMER_IRQSAFE); + advk_pcie_setup_hw(pcie); ret = advk_sw_pci_bridge_init(pcie); @@ -1971,6 +2060,9 @@ static int advk_pcie_remove(struct platform_device *pdev) advk_pcie_remove_msi_irq_domain(pcie); advk_pcie_remove_irq_domain(pcie); + /* Deactivate link event timer */ + del_timer_sync(&pcie->link_irq_timer); + /* Free config space for emulated root bridge */ pci_bridge_emul_cleanup(&pcie->bridge); -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-02-20 19:34 UTC|newest] Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-20 19:33 [PATCH 00/18] PCI: aardvark controller changes BATCH 5 Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 01/18] PCI: pci-bridge-emul: Re-arrange register tests Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 02/18] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 03/18] PCI: aardvark: Add support for AER registers on emulated bridge Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 04/18] PCI: Add PCI_EXP_SLTCAP_*_SHIFT macros Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-28 11:09 ` Lorenzo Pieralisi 2022-04-28 11:09 ` Lorenzo Pieralisi 2022-04-28 11:16 ` Pali Rohár 2022-04-28 11:16 ` Pali Rohár 2022-05-18 19:23 ` Bjorn Helgaas 2022-05-18 19:23 ` Bjorn Helgaas 2022-05-18 19:26 ` Pali Rohár 2022-05-18 19:26 ` Pali Rohár 2022-05-18 20:05 ` Marek Behún 2022-05-18 20:05 ` Marek Behún 2022-05-18 20:27 ` Bjorn Helgaas 2022-05-18 20:27 ` Bjorn Helgaas 2022-02-20 19:33 ` [PATCH 05/18] PCI: aardvark: Fix reporting Slot capabilities on emulated bridge Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 06/18] PCI: pciehp: Enable DLLSC interrupt only if supported Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-05-09 3:42 ` Lukas Wunner 2022-05-13 16:57 ` Pali Rohár 2022-05-13 16:57 ` Pali Rohár 2022-05-14 9:14 ` Lukas Wunner 2022-08-18 12:22 ` Marek Behún 2022-08-18 12:22 ` Marek Behún 2022-02-20 19:33 ` [PATCH 07/18] PCI: pciehp: Enable Command Completed Interrupt " Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-05-09 4:01 ` Lukas Wunner 2022-05-13 16:59 ` Pali Rohár 2022-05-13 16:59 ` Pali Rohár 2022-02-20 19:33 ` Marek Behún [this message] 2022-02-20 19:33 ` [PATCH 08/18] PCI: aardvark: Add support for DLLSC and hotplug interrupt Marek Behún 2022-02-20 19:33 ` [PATCH 09/18] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 10/18] PCI: Add function for parsing `slot-power-limit-milliwatt` DT property Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 11/18] dt-bindings: PCI: aardvark: Describe slot-power-limit-milliwatt Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 12/18] PCI: aardvark: Send Set_Slot_Power_Limit message Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 13/18] arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 14/18] PCI: aardvark: Add clock support Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 15/18] arm64: dts: marvell: armada-37xx: Add clock to PCIe node Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-28 15:52 ` Gregory CLEMENT 2022-02-28 15:52 ` Gregory CLEMENT 2022-02-20 19:33 ` [PATCH 16/18] PCI: aardvark: Add suspend to RAM support Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-12 11:14 ` Lorenzo Pieralisi 2022-04-12 11:14 ` Lorenzo Pieralisi 2022-02-20 19:33 ` [PATCH 17/18] PCI: aardvark: Run link training in separate worker Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-12 15:25 ` Lorenzo Pieralisi 2022-04-12 15:25 ` Lorenzo Pieralisi 2022-04-12 17:55 ` Pali Rohár 2022-04-12 17:55 ` Pali Rohár 2022-04-13 9:16 ` Lorenzo Pieralisi 2022-04-13 9:16 ` Lorenzo Pieralisi 2022-05-04 14:02 ` Marek Behún 2022-05-04 14:02 ` Marek Behún 2022-02-20 19:33 ` [PATCH 18/18] PCI: aardvark: Optimize PCIe card reset via GPIO Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-11 15:36 ` [PATCH 00/18] PCI: aardvark controller changes BATCH 5 Lorenzo Pieralisi 2022-04-11 15:36 ` Lorenzo Pieralisi 2022-04-11 16:53 ` Pali Rohár 2022-04-11 16:53 ` Pali Rohár 2022-05-13 10:33 ` Lorenzo Pieralisi 2022-05-13 10:33 ` Lorenzo Pieralisi 2022-05-13 16:48 ` Pali Rohár 2022-05-13 16:48 ` Pali Rohár 2022-05-18 15:54 ` (subset) " Lorenzo Pieralisi 2022-05-18 15:54 ` Lorenzo Pieralisi 2022-08-16 16:25 ` Lorenzo Pieralisi 2022-08-16 16:25 ` Lorenzo Pieralisi 2022-08-18 13:56 ` Marek Behún 2022-08-18 13:56 ` Marek Behún
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