From: "Marek Behún" <kabel@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <helgaas@kernel.org> Cc: "Krzysztof Wilczyński" <kw@linux.com>, "Marc Zyngier" <maz@kernel.org>, pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Gregory CLEMENT" <gregory.clement@bootlin.com>, "Marek Behún" <kabel@kernel.org> Subject: [PATCH 03/18] PCI: aardvark: Add support for AER registers on emulated bridge Date: Sun, 20 Feb 2022 20:33:31 +0100 [thread overview] Message-ID: <20220220193346.23789-4-kabel@kernel.org> (raw) In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> From: Pali Rohár <pali@kernel.org> Aardvark controller supports Advanced Error Reporting configuration registers. Export these registers on the emulated root bridge via the new .read_ext and .write_ext methods. Note that in the Advanced Error Reporting Capability header the offset to the next Extended Capability header is set, but it is not documented in Armada 3700 Functional Specification. Since this change adds support only for Advanced Error Reporting, explicitly clear PCI_EXT_CAP_NEXT bits in AER capability header. Now the pcieport driver correctly detects AER support and allows PCIe AER driver to start receiving ERR interrupts. Kernel log now says: [ 4.358401] pcieport 0000:00:00.0: AER: enabled with IRQ 52 Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/pci/controller/pci-aardvark.c | 77 +++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 7621c9344a2b..01dd530e1b5f 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -33,6 +33,7 @@ #define PCIE_CORE_CMD_STATUS_REG 0x4 #define PCIE_CORE_DEV_REV_REG 0x8 #define PCIE_CORE_PCIEXP_CAP 0xc0 +#define PCIE_CORE_PCIERR_CAP 0x100 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) @@ -945,11 +946,87 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, } } +static pci_bridge_emul_read_status_t +advk_pci_bridge_emul_ext_conf_read(struct pci_bridge_emul *bridge, + int reg, u32 *value) +{ + struct advk_pcie *pcie = bridge->data; + + switch (reg) { + case 0: + *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); + /* + * PCI_EXT_CAP_NEXT bits are set to offset 0x150, but Armada + * 3700 Functional Specification does not document registers + * at those addresses. + * Thus we clear PCI_EXT_CAP_NEXT bits to make Advanced Error + * Reporting Capability header the last of Extended + * Capabilities. (If we obtain documentation for those + * registers in the future, this can be changed.) + */ + *value &= 0x000fffff; + return PCI_BRIDGE_EMUL_HANDLED; + + case PCI_ERR_UNCOR_STATUS: + case PCI_ERR_UNCOR_MASK: + case PCI_ERR_UNCOR_SEVER: + case PCI_ERR_COR_STATUS: + case PCI_ERR_COR_MASK: + case PCI_ERR_CAP: + case PCI_ERR_HEADER_LOG + 0: + case PCI_ERR_HEADER_LOG + 4: + case PCI_ERR_HEADER_LOG + 8: + case PCI_ERR_HEADER_LOG + 12: + case PCI_ERR_ROOT_COMMAND: + case PCI_ERR_ROOT_STATUS: + case PCI_ERR_ROOT_ERR_SRC: + *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); + return PCI_BRIDGE_EMUL_HANDLED; + + default: + return PCI_BRIDGE_EMUL_NOT_HANDLED; + } +} + +static void +advk_pci_bridge_emul_ext_conf_write(struct pci_bridge_emul *bridge, + int reg, u32 old, u32 new, u32 mask) +{ + struct advk_pcie *pcie = bridge->data; + + switch (reg) { + /* These are W1C registers, so clear other bits */ + case PCI_ERR_UNCOR_STATUS: + case PCI_ERR_COR_STATUS: + case PCI_ERR_ROOT_STATUS: + new &= mask; + fallthrough; + + case PCI_ERR_UNCOR_MASK: + case PCI_ERR_UNCOR_SEVER: + case PCI_ERR_COR_MASK: + case PCI_ERR_CAP: + case PCI_ERR_HEADER_LOG + 0: + case PCI_ERR_HEADER_LOG + 4: + case PCI_ERR_HEADER_LOG + 8: + case PCI_ERR_HEADER_LOG + 12: + case PCI_ERR_ROOT_COMMAND: + case PCI_ERR_ROOT_ERR_SRC: + advk_writel(pcie, new, PCIE_CORE_PCIERR_CAP + reg); + break; + + default: + break; + } +} + static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { .read_base = advk_pci_bridge_emul_base_conf_read, .write_base = advk_pci_bridge_emul_base_conf_write, .read_pcie = advk_pci_bridge_emul_pcie_conf_read, .write_pcie = advk_pci_bridge_emul_pcie_conf_write, + .read_ext = advk_pci_bridge_emul_ext_conf_read, + .write_ext = advk_pci_bridge_emul_ext_conf_write, }; /* -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: "Marek Behún" <kabel@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <helgaas@kernel.org> Cc: "Krzysztof Wilczyński" <kw@linux.com>, "Marc Zyngier" <maz@kernel.org>, pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Gregory CLEMENT" <gregory.clement@bootlin.com>, "Marek Behún" <kabel@kernel.org> Subject: [PATCH 03/18] PCI: aardvark: Add support for AER registers on emulated bridge Date: Sun, 20 Feb 2022 20:33:31 +0100 [thread overview] Message-ID: <20220220193346.23789-4-kabel@kernel.org> (raw) In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> From: Pali Rohár <pali@kernel.org> Aardvark controller supports Advanced Error Reporting configuration registers. Export these registers on the emulated root bridge via the new .read_ext and .write_ext methods. Note that in the Advanced Error Reporting Capability header the offset to the next Extended Capability header is set, but it is not documented in Armada 3700 Functional Specification. Since this change adds support only for Advanced Error Reporting, explicitly clear PCI_EXT_CAP_NEXT bits in AER capability header. Now the pcieport driver correctly detects AER support and allows PCIe AER driver to start receiving ERR interrupts. Kernel log now says: [ 4.358401] pcieport 0000:00:00.0: AER: enabled with IRQ 52 Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/pci/controller/pci-aardvark.c | 77 +++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 7621c9344a2b..01dd530e1b5f 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -33,6 +33,7 @@ #define PCIE_CORE_CMD_STATUS_REG 0x4 #define PCIE_CORE_DEV_REV_REG 0x8 #define PCIE_CORE_PCIEXP_CAP 0xc0 +#define PCIE_CORE_PCIERR_CAP 0x100 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) @@ -945,11 +946,87 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, } } +static pci_bridge_emul_read_status_t +advk_pci_bridge_emul_ext_conf_read(struct pci_bridge_emul *bridge, + int reg, u32 *value) +{ + struct advk_pcie *pcie = bridge->data; + + switch (reg) { + case 0: + *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); + /* + * PCI_EXT_CAP_NEXT bits are set to offset 0x150, but Armada + * 3700 Functional Specification does not document registers + * at those addresses. + * Thus we clear PCI_EXT_CAP_NEXT bits to make Advanced Error + * Reporting Capability header the last of Extended + * Capabilities. (If we obtain documentation for those + * registers in the future, this can be changed.) + */ + *value &= 0x000fffff; + return PCI_BRIDGE_EMUL_HANDLED; + + case PCI_ERR_UNCOR_STATUS: + case PCI_ERR_UNCOR_MASK: + case PCI_ERR_UNCOR_SEVER: + case PCI_ERR_COR_STATUS: + case PCI_ERR_COR_MASK: + case PCI_ERR_CAP: + case PCI_ERR_HEADER_LOG + 0: + case PCI_ERR_HEADER_LOG + 4: + case PCI_ERR_HEADER_LOG + 8: + case PCI_ERR_HEADER_LOG + 12: + case PCI_ERR_ROOT_COMMAND: + case PCI_ERR_ROOT_STATUS: + case PCI_ERR_ROOT_ERR_SRC: + *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); + return PCI_BRIDGE_EMUL_HANDLED; + + default: + return PCI_BRIDGE_EMUL_NOT_HANDLED; + } +} + +static void +advk_pci_bridge_emul_ext_conf_write(struct pci_bridge_emul *bridge, + int reg, u32 old, u32 new, u32 mask) +{ + struct advk_pcie *pcie = bridge->data; + + switch (reg) { + /* These are W1C registers, so clear other bits */ + case PCI_ERR_UNCOR_STATUS: + case PCI_ERR_COR_STATUS: + case PCI_ERR_ROOT_STATUS: + new &= mask; + fallthrough; + + case PCI_ERR_UNCOR_MASK: + case PCI_ERR_UNCOR_SEVER: + case PCI_ERR_COR_MASK: + case PCI_ERR_CAP: + case PCI_ERR_HEADER_LOG + 0: + case PCI_ERR_HEADER_LOG + 4: + case PCI_ERR_HEADER_LOG + 8: + case PCI_ERR_HEADER_LOG + 12: + case PCI_ERR_ROOT_COMMAND: + case PCI_ERR_ROOT_ERR_SRC: + advk_writel(pcie, new, PCIE_CORE_PCIERR_CAP + reg); + break; + + default: + break; + } +} + static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { .read_base = advk_pci_bridge_emul_base_conf_read, .write_base = advk_pci_bridge_emul_base_conf_write, .read_pcie = advk_pci_bridge_emul_pcie_conf_read, .write_pcie = advk_pci_bridge_emul_pcie_conf_write, + .read_ext = advk_pci_bridge_emul_ext_conf_read, + .write_ext = advk_pci_bridge_emul_ext_conf_write, }; /* -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-02-20 19:34 UTC|newest] Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-20 19:33 [PATCH 00/18] PCI: aardvark controller changes BATCH 5 Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 01/18] PCI: pci-bridge-emul: Re-arrange register tests Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 02/18] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` Marek Behún [this message] 2022-02-20 19:33 ` [PATCH 03/18] PCI: aardvark: Add support for AER registers on emulated bridge Marek Behún 2022-02-20 19:33 ` [PATCH 04/18] PCI: Add PCI_EXP_SLTCAP_*_SHIFT macros Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-28 11:09 ` Lorenzo Pieralisi 2022-04-28 11:09 ` Lorenzo Pieralisi 2022-04-28 11:16 ` Pali Rohár 2022-04-28 11:16 ` Pali Rohár 2022-05-18 19:23 ` Bjorn Helgaas 2022-05-18 19:23 ` Bjorn Helgaas 2022-05-18 19:26 ` Pali Rohár 2022-05-18 19:26 ` Pali Rohár 2022-05-18 20:05 ` Marek Behún 2022-05-18 20:05 ` Marek Behún 2022-05-18 20:27 ` Bjorn Helgaas 2022-05-18 20:27 ` Bjorn Helgaas 2022-02-20 19:33 ` [PATCH 05/18] PCI: aardvark: Fix reporting Slot capabilities on emulated bridge Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 06/18] PCI: pciehp: Enable DLLSC interrupt only if supported Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-05-09 3:42 ` Lukas Wunner 2022-05-13 16:57 ` Pali Rohár 2022-05-13 16:57 ` Pali Rohár 2022-05-14 9:14 ` Lukas Wunner 2022-08-18 12:22 ` Marek Behún 2022-08-18 12:22 ` Marek Behún 2022-02-20 19:33 ` [PATCH 07/18] PCI: pciehp: Enable Command Completed Interrupt " Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-05-09 4:01 ` Lukas Wunner 2022-05-13 16:59 ` Pali Rohár 2022-05-13 16:59 ` Pali Rohár 2022-02-20 19:33 ` [PATCH 08/18] PCI: aardvark: Add support for DLLSC and hotplug interrupt Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 09/18] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 10/18] PCI: Add function for parsing `slot-power-limit-milliwatt` DT property Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 11/18] dt-bindings: PCI: aardvark: Describe slot-power-limit-milliwatt Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 12/18] PCI: aardvark: Send Set_Slot_Power_Limit message Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 13/18] arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 14/18] PCI: aardvark: Add clock support Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-20 19:33 ` [PATCH 15/18] arm64: dts: marvell: armada-37xx: Add clock to PCIe node Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-02-28 15:52 ` Gregory CLEMENT 2022-02-28 15:52 ` Gregory CLEMENT 2022-02-20 19:33 ` [PATCH 16/18] PCI: aardvark: Add suspend to RAM support Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-12 11:14 ` Lorenzo Pieralisi 2022-04-12 11:14 ` Lorenzo Pieralisi 2022-02-20 19:33 ` [PATCH 17/18] PCI: aardvark: Run link training in separate worker Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-12 15:25 ` Lorenzo Pieralisi 2022-04-12 15:25 ` Lorenzo Pieralisi 2022-04-12 17:55 ` Pali Rohár 2022-04-12 17:55 ` Pali Rohár 2022-04-13 9:16 ` Lorenzo Pieralisi 2022-04-13 9:16 ` Lorenzo Pieralisi 2022-05-04 14:02 ` Marek Behún 2022-05-04 14:02 ` Marek Behún 2022-02-20 19:33 ` [PATCH 18/18] PCI: aardvark: Optimize PCIe card reset via GPIO Marek Behún 2022-02-20 19:33 ` Marek Behún 2022-04-11 15:36 ` [PATCH 00/18] PCI: aardvark controller changes BATCH 5 Lorenzo Pieralisi 2022-04-11 15:36 ` Lorenzo Pieralisi 2022-04-11 16:53 ` Pali Rohár 2022-04-11 16:53 ` Pali Rohár 2022-05-13 10:33 ` Lorenzo Pieralisi 2022-05-13 10:33 ` Lorenzo Pieralisi 2022-05-13 16:48 ` Pali Rohár 2022-05-13 16:48 ` Pali Rohár 2022-05-18 15:54 ` (subset) " Lorenzo Pieralisi 2022-05-18 15:54 ` Lorenzo Pieralisi 2022-08-16 16:25 ` Lorenzo Pieralisi 2022-08-16 16:25 ` Lorenzo Pieralisi 2022-08-18 13:56 ` Marek Behún 2022-08-18 13:56 ` Marek Behún
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220220193346.23789-4-kabel@kernel.org \ --to=kabel@kernel.org \ --cc=gregory.clement@bootlin.com \ --cc=helgaas@kernel.org \ --cc=kw@linux.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-pci@vger.kernel.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=maz@kernel.org \ --cc=pali@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.