[PATCH] ARM: dts: lan966x: fix sys_clk frequency

[PATCH] ARM: dts: lan966x: fix sys_clk frequency

[Michael Walle]

The sys_clk frequency is 165.625MHz. The register reference of the
Generic Clock controller lists the CPU clock as 600MHz, the DDR clock as
300MHz and the SYS clock as 162.5MHz. This is wrong. It was first
noticed during the fan driver development and it was measured and
verified via the CLK_MON output of the SoC which can be configured to
output sys_clk/64.

The core PLL settings (which drives the SYS clock) seems to be as
follows:
  DIVF = 52
  DIVQ = 3
  DIVR = 1

With a refernce clock of 25MHz, this means we have a post divider clock
  Fpfd = Fref / (DIVR + 1) = 25MHz / (1 + 1) = 12.5MHz

The resulting VCO frequency is then
  Fvco = Fpfd * (DIVF + 1) * 2 = 12.5MHz * (52 + 1) * 2 = 1325MHz

And the output frequency is
  Fout = Fvco / 2^DIVQ = 1325MHz / 2^3 = 165.625Mhz

This all adds up to the constrains of the PLL:
    10MHz <= Fpfd <= 200MHz
    20MHz <= Fout <= 1000MHz
  1000MHz <= Fvco <= 2000MHz

Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291")
Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/boot/dts/lan966x.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 14c9cb3c0f3b..03045ec4aca4 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -38,7 +38,7 @@ clocks {
 		sys_clk: sys_clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <162500000>;
+			clock-frequency = <165625000>;
 		};
 
 		cpu_clk: cpu_clk {
-- 
2.30.2

Re: [PATCH] ARM: dts: lan966x: fix sys_clk frequency

[Michael Walle]

Am 2022-03-26 20:40, schrieb Michael Walle:
> The sys_clk frequency is 165.625MHz. The register reference of the
> Generic Clock controller lists the CPU clock as 600MHz, the DDR clock 
> as
> 300MHz and the SYS clock as 162.5MHz. This is wrong. It was first
> noticed during the fan driver development and it was measured and
> verified via the CLK_MON output of the SoC which can be configured to
> output sys_clk/64.
> 
> The core PLL settings (which drives the SYS clock) seems to be as
> follows:
>   DIVF = 52
>   DIVQ = 3
>   DIVR = 1
> 
> With a refernce clock of 25MHz, this means we have a post divider clock
>   Fpfd = Fref / (DIVR + 1) = 25MHz / (1 + 1) = 12.5MHz
> 
> The resulting VCO frequency is then
>   Fvco = Fpfd * (DIVF + 1) * 2 = 12.5MHz * (52 + 1) * 2 = 1325MHz
> 
> And the output frequency is
>   Fout = Fvco / 2^DIVQ = 1325MHz / 2^3 = 165.625Mhz
> 
> This all adds up to the constrains of the PLL:
>     10MHz <= Fpfd <= 200MHz
>     20MHz <= Fout <= 1000MHz
>   1000MHz <= Fvco <= 2000MHz
> 
> Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board 
> pcb8291")
> Signed-off-by: Michael Walle <michael@walle.cc>

Ping :)

Btw. this is also true for the new B0 silicon. I just verified it
with the CLK_MON output.

-michael

Re: [PATCH] ARM: dts: lan966x: fix sys_clk frequency

[Michael Walle]

Am 2022-04-28 10:49, schrieb Michael Walle:
> Am 2022-03-26 20:40, schrieb Michael Walle:
>> The sys_clk frequency is 165.625MHz. The register reference of the
>> Generic Clock controller lists the CPU clock as 600MHz, the DDR clock 
>> as
>> 300MHz and the SYS clock as 162.5MHz. This is wrong. It was first
>> noticed during the fan driver development and it was measured and
>> verified via the CLK_MON output of the SoC which can be configured to
>> output sys_clk/64.
>> 
>> The core PLL settings (which drives the SYS clock) seems to be as
>> follows:
>>   DIVF = 52
>>   DIVQ = 3
>>   DIVR = 1
>> 
>> With a refernce clock of 25MHz, this means we have a post divider 
>> clock
>>   Fpfd = Fref / (DIVR + 1) = 25MHz / (1 + 1) = 12.5MHz
>> 
>> The resulting VCO frequency is then
>>   Fvco = Fpfd * (DIVF + 1) * 2 = 12.5MHz * (52 + 1) * 2 = 1325MHz
>> 
>> And the output frequency is
>>   Fout = Fvco / 2^DIVQ = 1325MHz / 2^3 = 165.625Mhz
>> 
>> This all adds up to the constrains of the PLL:
>>     10MHz <= Fpfd <= 200MHz
>>     20MHz <= Fout <= 1000MHz
>>   1000MHz <= Fvco <= 2000MHz
>> 
>> Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board 
>> pcb8291")
>> Signed-off-by: Michael Walle <michael@walle.cc>
> 
> Ping :)
> 
> Btw. this is also true for the new B0 silicon. I just verified it
> with the CLK_MON output.

Ping #2.

Could this please be picked up because most drivers use this property
to calculate output frequencies and so on, e.g. the PWM driver.

-michael

RE: [PATCH] ARM: dts: lan966x: fix sys_clk frequency

[Kavyasree.Kotagiri]

> The sys_clk frequency is 165.625MHz. The register reference of the
> Generic Clock controller lists the CPU clock as 600MHz, the DDR clock as
> 300MHz and the SYS clock as 162.5MHz. This is wrong. It was first
> noticed during the fan driver development and it was measured and
> verified via the CLK_MON output of the SoC which can be configured to
> output sys_clk/64.
> 
> The core PLL settings (which drives the SYS clock) seems to be as
> follows:
>   DIVF = 52
>   DIVQ = 3
>   DIVR = 1
> 
> With a refernce clock of 25MHz, this means we have a post divider clock
>   Fpfd = Fref / (DIVR + 1) = 25MHz / (1 + 1) = 12.5MHz
> 
> The resulting VCO frequency is then
>   Fvco = Fpfd * (DIVF + 1) * 2 = 12.5MHz * (52 + 1) * 2 = 1325MHz
> 
> And the output frequency is
>   Fout = Fvco / 2^DIVQ = 1325MHz / 2^3 = 165.625Mhz
> 
> This all adds up to the constrains of the PLL:
>     10MHz <= Fpfd <= 200MHz
>     20MHz <= Fout <= 1000MHz
>   1000MHz <= Fvco <= 2000MHz
> 
> Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board
> pcb8291")
> Signed-off-by: Michael Walle <michael@walle.cc>

Reviewed-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>

> ---
>  arch/arm/boot/dts/lan966x.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/lan966x.dtsi
> b/arch/arm/boot/dts/lan966x.dtsi
> index 14c9cb3c0f3b..03045ec4aca4 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -38,7 +38,7 @@ clocks {
>                 sys_clk: sys_clk {
>                         compatible = "fixed-clock";
>                         #clock-cells = <0>;
> -                       clock-frequency = <162500000>;
> +                       clock-frequency = <165625000>;
>                 };
> 
>                 cpu_clk: cpu_clk {
> --
> 2.30.2

Re: [PATCH] ARM: dts: lan966x: fix sys_clk frequency

[Michael Walle]

[+ Claudiu as he seems to pick patches for at91, too]

Am 2022-06-22 13:51, schrieb Michael Walle:
> Am 2022-04-28 10:49, schrieb Michael Walle:
>> Am 2022-03-26 20:40, schrieb Michael Walle:
>>> The sys_clk frequency is 165.625MHz. The register reference of the
>>> Generic Clock controller lists the CPU clock as 600MHz, the DDR clock 
>>> as
>>> 300MHz and the SYS clock as 162.5MHz. This is wrong. It was first
>>> noticed during the fan driver development and it was measured and
>>> verified via the CLK_MON output of the SoC which can be configured to
>>> output sys_clk/64.
>>> 
>>> The core PLL settings (which drives the SYS clock) seems to be as
>>> follows:
>>>   DIVF = 52
>>>   DIVQ = 3
>>>   DIVR = 1
>>> 
>>> With a refernce clock of 25MHz, this means we have a post divider 
>>> clock
>>>   Fpfd = Fref / (DIVR + 1) = 25MHz / (1 + 1) = 12.5MHz
>>> 
>>> The resulting VCO frequency is then
>>>   Fvco = Fpfd * (DIVF + 1) * 2 = 12.5MHz * (52 + 1) * 2 = 1325MHz
>>> 
>>> And the output frequency is
>>>   Fout = Fvco / 2^DIVQ = 1325MHz / 2^3 = 165.625Mhz
>>> 
>>> This all adds up to the constrains of the PLL:
>>>     10MHz <= Fpfd <= 200MHz
>>>     20MHz <= Fout <= 1000MHz
>>>   1000MHz <= Fvco <= 2000MHz
>>> 
>>> Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port 
>>> board pcb8291")
>>> Signed-off-by: Michael Walle <michael@walle.cc>
>> 
>> Ping :)
>> 
>> Btw. this is also true for the new B0 silicon. I just verified it
>> with the CLK_MON output.
> 
> Ping #2.
> 
> Could this please be picked up because most drivers use this property
> to calculate output frequencies and so on, e.g. the PWM driver.

Ping #3. Now it even got a Reviewed-by.

-michael

Re: [PATCH] ARM: dts: lan966x: fix sys_clk frequency

[Claudiu.Beznea]

On 15.07.2022 21:41, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
> 
> [+ Claudiu as he seems to pick patches for at91, too]
> 
> Am 2022-06-22 13:51, schrieb Michael Walle:
>> Am 2022-04-28 10:49, schrieb Michael Walle:
>>> Am 2022-03-26 20:40, schrieb Michael Walle:
>>>> The sys_clk frequency is 165.625MHz. The register reference of the
>>>> Generic Clock controller lists the CPU clock as 600MHz, the DDR clock
>>>> as
>>>> 300MHz and the SYS clock as 162.5MHz. This is wrong. It was first
>>>> noticed during the fan driver development and it was measured and
>>>> verified via the CLK_MON output of the SoC which can be configured to
>>>> output sys_clk/64.
>>>>
>>>> The core PLL settings (which drives the SYS clock) seems to be as
>>>> follows:
>>>>   DIVF = 52
>>>>   DIVQ = 3
>>>>   DIVR = 1
>>>>
>>>> With a refernce clock of 25MHz, this means we have a post divider
>>>> clock
>>>>   Fpfd = Fref / (DIVR + 1) = 25MHz / (1 + 1) = 12.5MHz
>>>>
>>>> The resulting VCO frequency is then
>>>>   Fvco = Fpfd * (DIVF + 1) * 2 = 12.5MHz * (52 + 1) * 2 = 1325MHz
>>>>
>>>> And the output frequency is
>>>>   Fout = Fvco / 2^DIVQ = 1325MHz / 2^3 = 165.625Mhz
>>>>
>>>> This all adds up to the constrains of the PLL:
>>>>     10MHz <= Fpfd <= 200MHz
>>>>     20MHz <= Fout <= 1000MHz
>>>>   1000MHz <= Fvco <= 2000MHz
>>>>
>>>> Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port
>>>> board pcb8291")
>>>> Signed-off-by: Michael Walle <michael@walle.cc>

Applied to at91-fixes, thanks!

>>>
>>> Ping :)
>>>
>>> Btw. this is also true for the new B0 silicon. I just verified it
>>> with the CLK_MON output.
>>
>> Ping #2.
>>
>> Could this please be picked up because most drivers use this property
>> to calculate output frequencies and so on, e.g. the PWM driver.
> 
> Ping #3. Now it even got a Reviewed-by.
> 
> -michael