From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Sagar Kadam <sagar.kadam@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: Geert Uytterhoeven <geert+renesas@glider.be>, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC Date: Sun, 26 Jun 2022 01:43:25 +0100 [thread overview] Message-ID: <20220626004326.8548-2-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw) In-Reply-To: <20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Document Renesas RZ/Five (R9A07G043) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- v1->v2: * Fixed binding doc * Fixed review comments pointed by Krzysztof. RFC->v1: * Fixed Review comments pointed by Geert and Rob --- .../sifive,plic-1.0.0.yaml | 44 +++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 27092c6a86c4..59df367d1e44 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -28,7 +28,10 @@ description: While the PLIC supports both edge-triggered and level-triggered interrupts, interrupt handlers are oblivious to this distinction and therefore it is not - specified in the PLIC device-tree binding. + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's), + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need + to specify the interrupt type as the flow for EDGE interrupts is different + compared to LEVEL interrupts. While the RISC-V ISA doesn't specify a memory layout for the PLIC, the "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that @@ -57,6 +60,7 @@ properties: - enum: - allwinner,sun20i-d1-plic - const: thead,c900-plic + - const: renesas,r9a07g043-plic reg: maxItems: 1 @@ -64,8 +68,7 @@ properties: '#address-cells': const: 0 - '#interrupt-cells': - const: 1 + '#interrupt-cells': true interrupt-controller: true @@ -82,6 +85,12 @@ properties: description: Specifies how many external interrupts are supported by this controller. + clocks: true + + power-domains: true + + resets: true + required: - compatible - '#address-cells' @@ -91,6 +100,35 @@ required: - interrupts-extended - riscv,ndev +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a07g043-plic + then: + properties: + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + '#interrupt-cells': + const: 2 + + required: + - clocks + - resets + - power-domains + else: + properties: + '#interrupt-cells': + const: 1 + additionalProperties: false examples: -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Sagar Kadam <sagar.kadam@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: Geert Uytterhoeven <geert+renesas@glider.be>, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC Date: Sun, 26 Jun 2022 01:43:25 +0100 [thread overview] Message-ID: <20220626004326.8548-2-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw) In-Reply-To: <20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Document Renesas RZ/Five (R9A07G043) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- v1->v2: * Fixed binding doc * Fixed review comments pointed by Krzysztof. RFC->v1: * Fixed Review comments pointed by Geert and Rob --- .../sifive,plic-1.0.0.yaml | 44 +++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 27092c6a86c4..59df367d1e44 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -28,7 +28,10 @@ description: While the PLIC supports both edge-triggered and level-triggered interrupts, interrupt handlers are oblivious to this distinction and therefore it is not - specified in the PLIC device-tree binding. + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's), + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need + to specify the interrupt type as the flow for EDGE interrupts is different + compared to LEVEL interrupts. While the RISC-V ISA doesn't specify a memory layout for the PLIC, the "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that @@ -57,6 +60,7 @@ properties: - enum: - allwinner,sun20i-d1-plic - const: thead,c900-plic + - const: renesas,r9a07g043-plic reg: maxItems: 1 @@ -64,8 +68,7 @@ properties: '#address-cells': const: 0 - '#interrupt-cells': - const: 1 + '#interrupt-cells': true interrupt-controller: true @@ -82,6 +85,12 @@ properties: description: Specifies how many external interrupts are supported by this controller. + clocks: true + + power-domains: true + + resets: true + required: - compatible - '#address-cells' @@ -91,6 +100,35 @@ required: - interrupts-extended - riscv,ndev +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a07g043-plic + then: + properties: + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + '#interrupt-cells': + const: 2 + + required: + - clocks + - resets + - power-domains + else: + properties: + '#interrupt-cells': + const: 1 + additionalProperties: false examples: -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-06-26 0:44 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-26 0:43 [PATCH v2 0/2] Add PLIC support for Renesas RZ/Five SoC Lad Prabhakar 2022-06-26 0:43 ` Lad Prabhakar 2022-06-26 0:43 ` Lad Prabhakar [this message] 2022-06-26 0:43 ` [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document " Lad Prabhakar 2022-06-26 12:35 ` Marc Zyngier 2022-06-26 12:35 ` Marc Zyngier 2022-06-27 12:27 ` Lad, Prabhakar 2022-06-27 12:27 ` Lad, Prabhakar 2022-06-27 14:22 ` Marc Zyngier 2022-06-27 14:22 ` Marc Zyngier 2022-06-27 14:29 ` Lad, Prabhakar 2022-06-27 14:29 ` Lad, Prabhakar 2022-06-26 0:43 ` [PATCH v2 2/2] irqchip/sifive-plic: Add support for " Lad Prabhakar 2022-06-26 0:43 ` Lad Prabhakar 2022-06-26 8:57 ` Marc Zyngier 2022-06-26 8:57 ` Marc Zyngier 2022-06-26 9:38 ` Lad, Prabhakar 2022-06-26 9:38 ` Lad, Prabhakar 2022-06-26 12:19 ` Marc Zyngier 2022-06-26 12:19 ` Marc Zyngier 2022-06-27 8:53 ` Geert Uytterhoeven 2022-06-27 8:53 ` Geert Uytterhoeven 2022-06-27 10:11 ` Marc Zyngier 2022-06-27 10:11 ` Marc Zyngier 2022-06-27 13:06 ` Lad, Prabhakar 2022-06-27 13:06 ` Lad, Prabhakar 2022-06-27 13:12 ` Geert Uytterhoeven 2022-06-27 13:12 ` Geert Uytterhoeven 2022-06-27 13:53 ` Marc Zyngier 2022-06-27 13:53 ` Marc Zyngier 2022-06-27 14:16 ` Lad, Prabhakar 2022-06-27 14:16 ` Lad, Prabhakar 2022-06-29 13:41 ` Pavel Machek 2022-06-29 13:41 ` Pavel Machek 2022-06-29 15:00 ` Marc Zyngier 2022-06-29 15:00 ` Marc Zyngier 2022-06-27 4:55 ` Samuel Holland 2022-06-27 4:55 ` Samuel Holland
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