From: Marc Zyngier <maz@kernel.org> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Sagar Kadam <sagar.kadam@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, linux-riscv <linux-riscv@lists.infradead.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Date: Mon, 27 Jun 2022 11:11:21 +0100 [thread overview] Message-ID: <87a69y2z7a.wl-maz@kernel.org> (raw) In-Reply-To: <CAMuHMdVt9FjCtvMgJcCh=g2b+8b-fgabGbOLDcXNrrPMpC+3jQ@mail.gmail.com> On Mon, 27 Jun 2022 09:53:13 +0100, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Marc, > > On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote: > > On Sun, 26 Jun 2022 10:38:18 +0100, > > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote: > > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote: > > > > On Sun, 26 Jun 2022 01:43:26 +0100, > > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The > > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In > > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt > > > > > edge until the previous completion message has been received and > > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the > > > > > interrupts if not acknowledged in time. > > > > > > > > > > So the workaround for edge-triggered interrupts to be handled correctly > > > > > and without losing is that it needs to be acknowledged first and then > > > > > handler must be run so that we don't miss on the next edge-triggered > > > > > interrupt. > > > > > > > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds > > > > > support to change interrupt flow based on the interrupt type. It also > > > > > implements irq_ack and irq_set_type callbacks. > > > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > + if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) { > > > > > + priv->of_data = RENESAS_R9A07G043_PLIC; > > > > > + plic_chip.name = "Renesas RZ/Five PLIC"; > > > > > > > > NAK. The irq_chip structure isn't the place for platform marketing. > > > > This is way too long anyway (and same for the edge version), and you > > > > even sent me a patch to make that structure const... > > > > > > > My bad will drop this. > > > > And why you're at it, please turn this rather random 'of_data' into > > something like: > > > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > > index bb87e4c3b88e..cd1683b77caf 100644 > > --- a/drivers/irqchip/irq-sifive-plic.c > > +++ b/drivers/irqchip/irq-sifive-plic.c > > @@ -64,6 +64,10 @@ struct plic_priv { > > struct cpumask lmask; > > struct irq_domain *irqdomain; > > void __iomem *regs; > > + enum { > > + VANILLA_PLIC, > > + RENESAS_R9A07G043_PLIC, > > + } flavour; > > }; > > > > struct plic_handler { > > > > to give some structure to the whole thing, because I'm pretty sure > > we'll see more braindead implementations as time goes by. > > What about using a feature flag (e.g. had_edge_irqs) instead? Sure. Then make this an unsigned long, and have a set of quirk bits, because I expect this to grow quickly. > > > It almost feels like I've written this whole patch. Oh wait... > > > Without deviation from the norm, progress is not possible. > > How applicable ;-) I'm not sure there is any sign of progress here, and evolution through random mutation has a pretty massive failure rate. Thanks, M. -- Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Sagar Kadam <sagar.kadam@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, linux-riscv <linux-riscv@lists.infradead.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Date: Mon, 27 Jun 2022 11:11:21 +0100 [thread overview] Message-ID: <87a69y2z7a.wl-maz@kernel.org> (raw) In-Reply-To: <CAMuHMdVt9FjCtvMgJcCh=g2b+8b-fgabGbOLDcXNrrPMpC+3jQ@mail.gmail.com> On Mon, 27 Jun 2022 09:53:13 +0100, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Marc, > > On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote: > > On Sun, 26 Jun 2022 10:38:18 +0100, > > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote: > > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote: > > > > On Sun, 26 Jun 2022 01:43:26 +0100, > > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The > > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In > > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt > > > > > edge until the previous completion message has been received and > > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the > > > > > interrupts if not acknowledged in time. > > > > > > > > > > So the workaround for edge-triggered interrupts to be handled correctly > > > > > and without losing is that it needs to be acknowledged first and then > > > > > handler must be run so that we don't miss on the next edge-triggered > > > > > interrupt. > > > > > > > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds > > > > > support to change interrupt flow based on the interrupt type. It also > > > > > implements irq_ack and irq_set_type callbacks. > > > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > + if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) { > > > > > + priv->of_data = RENESAS_R9A07G043_PLIC; > > > > > + plic_chip.name = "Renesas RZ/Five PLIC"; > > > > > > > > NAK. The irq_chip structure isn't the place for platform marketing. > > > > This is way too long anyway (and same for the edge version), and you > > > > even sent me a patch to make that structure const... > > > > > > > My bad will drop this. > > > > And why you're at it, please turn this rather random 'of_data' into > > something like: > > > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > > index bb87e4c3b88e..cd1683b77caf 100644 > > --- a/drivers/irqchip/irq-sifive-plic.c > > +++ b/drivers/irqchip/irq-sifive-plic.c > > @@ -64,6 +64,10 @@ struct plic_priv { > > struct cpumask lmask; > > struct irq_domain *irqdomain; > > void __iomem *regs; > > + enum { > > + VANILLA_PLIC, > > + RENESAS_R9A07G043_PLIC, > > + } flavour; > > }; > > > > struct plic_handler { > > > > to give some structure to the whole thing, because I'm pretty sure > > we'll see more braindead implementations as time goes by. > > What about using a feature flag (e.g. had_edge_irqs) instead? Sure. Then make this an unsigned long, and have a set of quirk bits, because I expect this to grow quickly. > > > It almost feels like I've written this whole patch. Oh wait... > > > Without deviation from the norm, progress is not possible. > > How applicable ;-) I'm not sure there is any sign of progress here, and evolution through random mutation has a pretty massive failure rate. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-06-27 10:11 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-26 0:43 [PATCH v2 0/2] Add PLIC support for Renesas RZ/Five SoC Lad Prabhakar 2022-06-26 0:43 ` Lad Prabhakar 2022-06-26 0:43 ` [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document " Lad Prabhakar 2022-06-26 0:43 ` Lad Prabhakar 2022-06-26 12:35 ` Marc Zyngier 2022-06-26 12:35 ` Marc Zyngier 2022-06-27 12:27 ` Lad, Prabhakar 2022-06-27 12:27 ` Lad, Prabhakar 2022-06-27 14:22 ` Marc Zyngier 2022-06-27 14:22 ` Marc Zyngier 2022-06-27 14:29 ` Lad, Prabhakar 2022-06-27 14:29 ` Lad, Prabhakar 2022-06-26 0:43 ` [PATCH v2 2/2] irqchip/sifive-plic: Add support for " Lad Prabhakar 2022-06-26 0:43 ` Lad Prabhakar 2022-06-26 8:57 ` Marc Zyngier 2022-06-26 8:57 ` Marc Zyngier 2022-06-26 9:38 ` Lad, Prabhakar 2022-06-26 9:38 ` Lad, Prabhakar 2022-06-26 12:19 ` Marc Zyngier 2022-06-26 12:19 ` Marc Zyngier 2022-06-27 8:53 ` Geert Uytterhoeven 2022-06-27 8:53 ` Geert Uytterhoeven 2022-06-27 10:11 ` Marc Zyngier [this message] 2022-06-27 10:11 ` Marc Zyngier 2022-06-27 13:06 ` Lad, Prabhakar 2022-06-27 13:06 ` Lad, Prabhakar 2022-06-27 13:12 ` Geert Uytterhoeven 2022-06-27 13:12 ` Geert Uytterhoeven 2022-06-27 13:53 ` Marc Zyngier 2022-06-27 13:53 ` Marc Zyngier 2022-06-27 14:16 ` Lad, Prabhakar 2022-06-27 14:16 ` Lad, Prabhakar 2022-06-29 13:41 ` Pavel Machek 2022-06-29 13:41 ` Pavel Machek 2022-06-29 15:00 ` Marc Zyngier 2022-06-29 15:00 ` Marc Zyngier 2022-06-27 4:55 ` Samuel Holland 2022-06-27 4:55 ` Samuel Holland
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