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From: Marc Zyngier <maz@kernel.org>
To: Pavel Machek <pavel@ucw.cz>
Cc: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Sagar Kadam <sagar.kadam@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
Date: Wed, 29 Jun 2022 16:00:22 +0100	[thread overview]
Message-ID: <632a70d4d9b434cb126cecb015c69797@kernel.org> (raw)
In-Reply-To: <20220629134147.GA16868@duo.ucw.cz>

On 2022-06-29 14:41, Pavel Machek wrote:
> Hi!
> 
>> > >> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
>> > >>
>> > >>  struct plic_priv {
>> > >>         struct cpumask lmask;
>> > >>         struct irq_domain *irqdomain;
>> > >>         void __iomem *regs;
>> > >> +       u32 plic_quirks;
>> > >>  };
>> > >>
>> > >> What about something like above?
>> > >
>> > > LGTM.
>> > >
>> > > Marc suggested to make this unsigned long, but TBH, that won't make
>> > > much of a difference.  PLICs are present on RV32 SoCs, too, so you
>> > > cannot rely on having more than 32 bits anyway.
>> >
>> > But it will make a difference on a 64bit platform, as we want to
>> > use test_bit() and co to check for features.
>> >
>> Ok will change that to unsigned long and use the test_bit/set_bit 
>> instead.
> 
> Is there good enough reason for that? test_bit/... are when you need
> atomicity, and that's not the case here. Plain old & ... should be
> enough.

On any save architecture, '&' and test_bit() are the same thing.
Only RMW operations require atomicity.

'unsigned long' is is.

         M.
-- 
Jazz is not dead. It just smells funny...

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Pavel Machek <pavel@ucw.cz>
Cc: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Sagar Kadam <sagar.kadam@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
Date: Wed, 29 Jun 2022 16:00:22 +0100	[thread overview]
Message-ID: <632a70d4d9b434cb126cecb015c69797@kernel.org> (raw)
In-Reply-To: <20220629134147.GA16868@duo.ucw.cz>

On 2022-06-29 14:41, Pavel Machek wrote:
> Hi!
> 
>> > >> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
>> > >>
>> > >>  struct plic_priv {
>> > >>         struct cpumask lmask;
>> > >>         struct irq_domain *irqdomain;
>> > >>         void __iomem *regs;
>> > >> +       u32 plic_quirks;
>> > >>  };
>> > >>
>> > >> What about something like above?
>> > >
>> > > LGTM.
>> > >
>> > > Marc suggested to make this unsigned long, but TBH, that won't make
>> > > much of a difference.  PLICs are present on RV32 SoCs, too, so you
>> > > cannot rely on having more than 32 bits anyway.
>> >
>> > But it will make a difference on a 64bit platform, as we want to
>> > use test_bit() and co to check for features.
>> >
>> Ok will change that to unsigned long and use the test_bit/set_bit 
>> instead.
> 
> Is there good enough reason for that? test_bit/... are when you need
> atomicity, and that's not the case here. Plain old & ... should be
> enough.

On any save architecture, '&' and test_bit() are the same thing.
Only RMW operations require atomicity.

'unsigned long' is is.

         M.
-- 
Jazz is not dead. It just smells funny...

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-06-29 15:00 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-26  0:43 [PATCH v2 0/2] Add PLIC support for Renesas RZ/Five SoC Lad Prabhakar
2022-06-26  0:43 ` Lad Prabhakar
2022-06-26  0:43 ` [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document " Lad Prabhakar
2022-06-26  0:43   ` Lad Prabhakar
2022-06-26 12:35   ` Marc Zyngier
2022-06-26 12:35     ` Marc Zyngier
2022-06-27 12:27     ` Lad, Prabhakar
2022-06-27 12:27       ` Lad, Prabhakar
2022-06-27 14:22       ` Marc Zyngier
2022-06-27 14:22         ` Marc Zyngier
2022-06-27 14:29         ` Lad, Prabhakar
2022-06-27 14:29           ` Lad, Prabhakar
2022-06-26  0:43 ` [PATCH v2 2/2] irqchip/sifive-plic: Add support for " Lad Prabhakar
2022-06-26  0:43   ` Lad Prabhakar
2022-06-26  8:57   ` Marc Zyngier
2022-06-26  8:57     ` Marc Zyngier
2022-06-26  9:38     ` Lad, Prabhakar
2022-06-26  9:38       ` Lad, Prabhakar
2022-06-26 12:19       ` Marc Zyngier
2022-06-26 12:19         ` Marc Zyngier
2022-06-27  8:53         ` Geert Uytterhoeven
2022-06-27  8:53           ` Geert Uytterhoeven
2022-06-27 10:11           ` Marc Zyngier
2022-06-27 10:11             ` Marc Zyngier
2022-06-27 13:06           ` Lad, Prabhakar
2022-06-27 13:06             ` Lad, Prabhakar
2022-06-27 13:12             ` Geert Uytterhoeven
2022-06-27 13:12               ` Geert Uytterhoeven
2022-06-27 13:53               ` Marc Zyngier
2022-06-27 13:53                 ` Marc Zyngier
2022-06-27 14:16                 ` Lad, Prabhakar
2022-06-27 14:16                   ` Lad, Prabhakar
2022-06-29 13:41                   ` Pavel Machek
2022-06-29 13:41                     ` Pavel Machek
2022-06-29 15:00                     ` Marc Zyngier [this message]
2022-06-29 15:00                       ` Marc Zyngier
2022-06-27  4:55   ` Samuel Holland
2022-06-27  4:55     ` Samuel Holland

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