[PATCH 0/5] Complete driver nodes for MT8192 SoC

[PATCH 0/5] Complete driver nodes for MT8192 SoC

[Allen-KH Cheng]

This series are based on matthias.bgg/linux.git, for-next

Also need to reference below PATCH for dsi in chunkuang.hu/linux.git
dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml

Allen-KH Cheng (5):
  arm64: dts: mt8192: Add pwm node
  arm64: dts: mt8192: Add mipi_tx node
  arm64: dts: mt8192: Add display nodes
  arm64: dts: mt8192: Add dsi node
  arm64: dts: mt8192: Add vcodec lat and core nodes

 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 235 +++++++++++++++++++++++
 1 file changed, 235 insertions(+)

-- 
2.18.0

[PATCH 0/5] Complete driver nodes for MT8192 SoC

[Allen-KH Cheng]

This series are based on matthias.bgg/linux.git, for-next

Also need to reference below PATCH for dsi in chunkuang.hu/linux.git
dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml

Allen-KH Cheng (5):
  arm64: dts: mt8192: Add pwm node
  arm64: dts: mt8192: Add mipi_tx node
  arm64: dts: mt8192: Add display nodes
  arm64: dts: mt8192: Add dsi node
  arm64: dts: mt8192: Add vcodec lat and core nodes

 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 235 +++++++++++++++++++++++
 1 file changed, 235 insertions(+)

-- 
2.18.0


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[PATCH 1/5] arm64: dts: mt8192: Add pwm node

[Allen-KH Cheng]

Add pwm node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index cbae5a5ee4a0..731bdc665b94 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -599,6 +599,17 @@
 			status = "disabled";
 		};
 
+		pwm0: pwm@1100e000 {
+			compatible = "mediatek,mt8183-disp-pwm";
+			reg = <0 0x1100e000 0 0x1000>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
+			#pwm-cells = <2>;
+			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
+				 <&infracfg CLK_INFRA_DISP_PWM>;
+			clock-names = "main", "mm";
+			status = "disabled";
+		};
+
 		spi1: spi@11010000 {
 			compatible = "mediatek,mt8192-spi",
 				     "mediatek,mt6765-spi";
-- 
2.18.0

[PATCH 1/5] arm64: dts: mt8192: Add pwm node

[Allen-KH Cheng]

Add pwm node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index cbae5a5ee4a0..731bdc665b94 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -599,6 +599,17 @@
 			status = "disabled";
 		};
 
+		pwm0: pwm@1100e000 {
+			compatible = "mediatek,mt8183-disp-pwm";
+			reg = <0 0x1100e000 0 0x1000>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
+			#pwm-cells = <2>;
+			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
+				 <&infracfg CLK_INFRA_DISP_PWM>;
+			clock-names = "main", "mm";
+			status = "disabled";
+		};
+
 		spi1: spi@11010000 {
 			compatible = "mediatek,mt8192-spi",
 				     "mediatek,mt6765-spi";
-- 
2.18.0


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[PATCH 2/5] arm64: dts: mt8192: Add mipi_tx node

[Allen-KH Cheng]

Add mipi_tx node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 731bdc665b94..a07edc82d403 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1095,6 +1095,16 @@
 			};
 		};
 
+		mipi_tx0: dsi-dphy@11e50000 {
+			compatible = "mediatek,mt8183-mipi-tx";
+			reg = <0 0x11e50000 0 0x1000>;
+			clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+			clock-output-names = "mipi_tx0_pll";
+			status = "disabled";
+		};
+
 		i2c0: i2c@11f00000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11f00000 0 0x1000>,
-- 
2.18.0

[PATCH 2/5] arm64: dts: mt8192: Add mipi_tx node

[Allen-KH Cheng]

Add mipi_tx node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 731bdc665b94..a07edc82d403 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1095,6 +1095,16 @@
 			};
 		};
 
+		mipi_tx0: dsi-dphy@11e50000 {
+			compatible = "mediatek,mt8183-mipi-tx";
+			reg = <0 0x11e50000 0 0x1000>;
+			clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+			clock-output-names = "mipi_tx0_pll";
+			status = "disabled";
+		};
+
 		i2c0: i2c@11f00000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11f00000 0 0x1000>,
-- 
2.18.0


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/5] arm64: dts: mt8192: Add display nodes

[Allen-KH Cheng]

Add display nodes and gce info for mt8192 SoC.

GCE (Global Command Engine) properties to the display nodes in order to
enable the usage of the CMDQ (Command Queue), which is required for
operating the display.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136 +++++++++++++++++++++++
 1 file changed, 136 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a07edc82d403..26d01544b4ea 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/memory/mt8192-larb-port.h>
@@ -553,6 +554,15 @@
 			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
 		};
 
+		gce: mailbox@10228000 {
+			compatible = "mediatek,mt8192-gce";
+			reg = <0 0x10228000 0 0x4000>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <2>;
+			clocks = <&infracfg CLK_INFRA_GCE>;
+			clock-names = "gce";
+		};
+
 		scp_adsp: clock-controller@10720000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
@@ -1186,9 +1196,21 @@
 		mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8192-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		mutex: mutex@14001000 {
+			compatible = "mediatek,mt8192-disp-mutex";
+			reg = <0 0x14001000 0 0x1000>;
+			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
+		};
+
 		smi_common: smi@14002000 {
 			compatible = "mediatek,mt8192-smi-common";
 			reg = <0 0x14002000 0 0x1000>;
@@ -1220,6 +1242,120 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 		};
 
+		ovl0: ovl@14005000 {
+			compatible = "mediatek,mt8192-disp-ovl";
+			reg = <0 0x14005000 0 0x1000>;
+			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+		};
+
+		ovl_2l0: ovl@14006000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14006000 0 0x1000>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+		};
+
+		rdma0: rdma@14007000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14007000 0 0x1000>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,larb = <&larb0>;
+			mediatek,rdma-fifo-size = <5120>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
+		};
+
+		color0: color@14009000 {
+			compatible = "mediatek,mt8192-disp-color",
+				     "mediatek,mt8173-disp-color";
+			reg = <0 0x14009000 0 0x1000>;
+			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+		};
+
+		ccorr0: ccorr@1400a000 {
+			compatible = "mediatek,mt8192-disp-ccorr";
+			reg = <0 0x1400a000 0 0x1000>;
+			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
+		};
+
+		aal0: aal@1400b000 {
+			compatible = "mediatek,mt8192-disp-aal",
+				     "mediatek,mt8183-disp-aal";
+			reg = <0 0x1400b000 0 0x1000>;
+			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
+		};
+
+		gamma0: gamma@1400c000 {
+			compatible = "mediatek,mt8192-disp-gamma",
+				     "mediatek,mt8183-disp-gamma";
+			reg = <0 0x1400c000 0 0x1000>;
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+		};
+
+		postmask0: postmask@1400d000 {
+			compatible = "mediatek,mt8192-disp-postmask";
+			reg = <0 0x1400d000 0 0x1000>;
+			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+		};
+
+		dither0: dither@1400e000 {
+			compatible = "mediatek,mt8192-disp-dither",
+				     "mediatek,mt8183-disp-dither";
+			reg = <0 0x1400e000 0 0x1000>;
+			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+		};
+
+		ovl_2l2: ovl@14014000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14014000 0 0x1000>;
+			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
+		};
+
+		rdma4: rdma@14015000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14015000 0 0x1000>;
+			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+			mediatek,rdma-fifo-size = <2048>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+		};
+
 		dpi0: dpi@14016000 {
 			compatible = "mediatek,mt8192-dpi";
 			reg = <0 0x14016000 0 0x1000>;
-- 
2.18.0

[PATCH 3/5] arm64: dts: mt8192: Add display nodes

[Allen-KH Cheng]

Add display nodes and gce info for mt8192 SoC.

GCE (Global Command Engine) properties to the display nodes in order to
enable the usage of the CMDQ (Command Queue), which is required for
operating the display.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136 +++++++++++++++++++++++
 1 file changed, 136 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a07edc82d403..26d01544b4ea 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/memory/mt8192-larb-port.h>
@@ -553,6 +554,15 @@
 			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
 		};
 
+		gce: mailbox@10228000 {
+			compatible = "mediatek,mt8192-gce";
+			reg = <0 0x10228000 0 0x4000>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <2>;
+			clocks = <&infracfg CLK_INFRA_GCE>;
+			clock-names = "gce";
+		};
+
 		scp_adsp: clock-controller@10720000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
@@ -1186,9 +1196,21 @@
 		mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8192-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		mutex: mutex@14001000 {
+			compatible = "mediatek,mt8192-disp-mutex";
+			reg = <0 0x14001000 0 0x1000>;
+			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
+		};
+
 		smi_common: smi@14002000 {
 			compatible = "mediatek,mt8192-smi-common";
 			reg = <0 0x14002000 0 0x1000>;
@@ -1220,6 +1242,120 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 		};
 
+		ovl0: ovl@14005000 {
+			compatible = "mediatek,mt8192-disp-ovl";
+			reg = <0 0x14005000 0 0x1000>;
+			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+		};
+
+		ovl_2l0: ovl@14006000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14006000 0 0x1000>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+		};
+
+		rdma0: rdma@14007000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14007000 0 0x1000>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,larb = <&larb0>;
+			mediatek,rdma-fifo-size = <5120>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
+		};
+
+		color0: color@14009000 {
+			compatible = "mediatek,mt8192-disp-color",
+				     "mediatek,mt8173-disp-color";
+			reg = <0 0x14009000 0 0x1000>;
+			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+		};
+
+		ccorr0: ccorr@1400a000 {
+			compatible = "mediatek,mt8192-disp-ccorr";
+			reg = <0 0x1400a000 0 0x1000>;
+			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
+		};
+
+		aal0: aal@1400b000 {
+			compatible = "mediatek,mt8192-disp-aal",
+				     "mediatek,mt8183-disp-aal";
+			reg = <0 0x1400b000 0 0x1000>;
+			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
+		};
+
+		gamma0: gamma@1400c000 {
+			compatible = "mediatek,mt8192-disp-gamma",
+				     "mediatek,mt8183-disp-gamma";
+			reg = <0 0x1400c000 0 0x1000>;
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+		};
+
+		postmask0: postmask@1400d000 {
+			compatible = "mediatek,mt8192-disp-postmask";
+			reg = <0 0x1400d000 0 0x1000>;
+			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+		};
+
+		dither0: dither@1400e000 {
+			compatible = "mediatek,mt8192-disp-dither",
+				     "mediatek,mt8183-disp-dither";
+			reg = <0 0x1400e000 0 0x1000>;
+			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+		};
+
+		ovl_2l2: ovl@14014000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14014000 0 0x1000>;
+			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
+		};
+
+		rdma4: rdma@14015000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14015000 0 0x1000>;
+			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+			mediatek,rdma-fifo-size = <2048>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+		};
+
 		dpi0: dpi@14016000 {
 			compatible = "mediatek,mt8192-dpi";
 			reg = <0 0x14016000 0 0x1000>;
-- 
2.18.0


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[PATCH 4/5] arm64: dts: mt8192: Add dsi node

[Allen-KH Cheng]

Add dsi ndoe for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 26d01544b4ea..72af328126de 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1334,6 +1334,24 @@
 			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
 		};
 
+		dsi0: dsi@14010000 {
+			compatible = "mediatek,mt8183-dsi";
+			reg = <0 0x14010000 0 0x1000>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,syscon-dsi = <&mmsys 0x140>;
+			clocks = <&mmsys CLK_MM_DSI0>,
+				 <&mmsys CLK_MM_DSI_DSI0>,
+				 <&mipi_tx0>;
+			clock-names = "engine", "digital", "hs";
+			phys = <&mipi_tx0>;
+			phy-names = "dphy";
+			status = "disabled";
+
+			port {
+				dsi_out: endpoint { };
+			};
+		};
+
 		ovl_2l2: ovl@14014000 {
 			compatible = "mediatek,mt8192-disp-ovl-2l";
 			reg = <0 0x14014000 0 0x1000>;
-- 
2.18.0

[PATCH 4/5] arm64: dts: mt8192: Add dsi node

[Allen-KH Cheng]

Add dsi ndoe for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 26d01544b4ea..72af328126de 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1334,6 +1334,24 @@
 			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
 		};
 
+		dsi0: dsi@14010000 {
+			compatible = "mediatek,mt8183-dsi";
+			reg = <0 0x14010000 0 0x1000>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,syscon-dsi = <&mmsys 0x140>;
+			clocks = <&mmsys CLK_MM_DSI0>,
+				 <&mmsys CLK_MM_DSI_DSI0>,
+				 <&mipi_tx0>;
+			clock-names = "engine", "digital", "hs";
+			phys = <&mipi_tx0>;
+			phy-names = "dphy";
+			status = "disabled";
+
+			port {
+				dsi_out: endpoint { };
+			};
+		};
+
 		ovl_2l2: ovl@14014000 {
 			compatible = "mediatek,mt8192-disp-ovl-2l";
 			reg = <0 0x14014000 0 0x1000>;
-- 
2.18.0


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[PATCH 5/5] arm64: dts: mt8192: Add vcodec lat and core nodes

[Allen-KH Cheng]

Add vcodec lat and core nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 72af328126de..a7f58dbe964d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1434,6 +1434,66 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
 		};
 
+		vcodec_dec: vcodec-dec@16000000 {
+			compatible = "mediatek,mt8192-vcodec-dec";
+			reg = <0 0x16000000 0 0x1000>;
+			mediatek,scp = <&scp>;
+			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0 0 0 0x16000000 0 0x26000>;
+
+			vcodec_lat: vcodec-lat@10000 {
+				compatible = "mediatek,mtk-vcodec-lat";
+				reg = <0x0 0x10000 0 0x800>;
+				interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+			};
+
+			vcodec_core: vcodec-core@25000 {
+				compatible = "mediatek,mtk-vcodec-core";
+				reg = <0 0x25000 0 0x1000>;
+				interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys CLK_VDEC_VDEC>,
+					 <&vdecsys CLK_VDEC_LAT>,
+					 <&vdecsys CLK_VDEC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+			};
+		};
+
 		larb5: larb@1600d000 {
 			compatible = "mediatek,mt8192-smi-larb";
 			reg = <0 0x1600d000 0 0x1000>;
-- 
2.18.0

[PATCH 5/5] arm64: dts: mt8192: Add vcodec lat and core nodes

[Allen-KH Cheng]

Add vcodec lat and core nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 72af328126de..a7f58dbe964d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1434,6 +1434,66 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
 		};
 
+		vcodec_dec: vcodec-dec@16000000 {
+			compatible = "mediatek,mt8192-vcodec-dec";
+			reg = <0 0x16000000 0 0x1000>;
+			mediatek,scp = <&scp>;
+			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0 0 0 0x16000000 0 0x26000>;
+
+			vcodec_lat: vcodec-lat@10000 {
+				compatible = "mediatek,mtk-vcodec-lat";
+				reg = <0x0 0x10000 0 0x800>;
+				interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+			};
+
+			vcodec_core: vcodec-core@25000 {
+				compatible = "mediatek,mtk-vcodec-core";
+				reg = <0 0x25000 0 0x1000>;
+				interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys CLK_VDEC_VDEC>,
+					 <&vdecsys CLK_VDEC_LAT>,
+					 <&vdecsys CLK_VDEC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+			};
+		};
+
 		larb5: larb@1600d000 {
 			compatible = "mediatek,mt8192-smi-larb";
 			reg = <0 0x1600d000 0 0x1000>;
-- 
2.18.0


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Re: [PATCH 4/5] arm64: dts: mt8192: Add dsi node

[AngeloGioacchino Del Regno]

Il 29/06/22 14:13, Allen-KH Cheng ha scritto:
> Add dsi ndoe for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 26d01544b4ea..72af328126de 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1334,6 +1334,24 @@
>   			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>   		};
>   
> +		dsi0: dsi@14010000 {
> +			compatible = "mediatek,mt8183-dsi";
> +			reg = <0 0x14010000 0 0x1000>;
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> +			mediatek,syscon-dsi = <&mmsys 0x140>;
> +			clocks = <&mmsys CLK_MM_DSI0>,
> +				 <&mmsys CLK_MM_DSI_DSI0>,
> +				 <&mipi_tx0>;
> +			clock-names = "engine", "digital", "hs";
> +			phys = <&mipi_tx0>;
> +			phy-names = "dphy";

resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;

^^^ This is missing, please add it and resend :-)

> +			status = "disabled";
> +
> +			port {
> +				dsi_out: endpoint { };
> +			};
> +		};
> +
>   		ovl_2l2: ovl@14014000 {
>   			compatible = "mediatek,mt8192-disp-ovl-2l";
>   			reg = <0 0x14014000 0 0x1000>;

Re: [PATCH 4/5] arm64: dts: mt8192: Add dsi node

[AngeloGioacchino Del Regno]

Il 29/06/22 14:13, Allen-KH Cheng ha scritto:
> Add dsi ndoe for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 26d01544b4ea..72af328126de 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1334,6 +1334,24 @@
>   			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>   		};
>   
> +		dsi0: dsi@14010000 {
> +			compatible = "mediatek,mt8183-dsi";
> +			reg = <0 0x14010000 0 0x1000>;
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> +			mediatek,syscon-dsi = <&mmsys 0x140>;
> +			clocks = <&mmsys CLK_MM_DSI0>,
> +				 <&mmsys CLK_MM_DSI_DSI0>,
> +				 <&mipi_tx0>;
> +			clock-names = "engine", "digital", "hs";
> +			phys = <&mipi_tx0>;
> +			phy-names = "dphy";

resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;

^^^ This is missing, please add it and resend :-)

> +			status = "disabled";
> +
> +			port {
> +				dsi_out: endpoint { };
> +			};
> +		};
> +
>   		ovl_2l2: ovl@14014000 {
>   			compatible = "mediatek,mt8192-disp-ovl-2l";
>   			reg = <0 0x14014000 0 0x1000>;



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Re: [PATCH 1/5] arm64: dts: mt8192: Add pwm node

[Nícolas F. R. A. Prado]

On Wed, Jun 29, 2022 at 08:13:54PM +0800, Allen-KH Cheng wrote:
> Add pwm node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

Re: [PATCH 1/5] arm64: dts: mt8192: Add pwm node

[Nícolas F. R. A. Prado]

On Wed, Jun 29, 2022 at 08:13:54PM +0800, Allen-KH Cheng wrote:
> Add pwm node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

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Re: [PATCH 2/5] arm64: dts: mt8192: Add mipi_tx node

[Nícolas F. R. A. Prado]

On Wed, Jun 29, 2022 at 08:13:55PM +0800, Allen-KH Cheng wrote:
> Add mipi_tx node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 731bdc665b94..a07edc82d403 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1095,6 +1095,16 @@
>  			};
>  		};
>  
> +		mipi_tx0: dsi-dphy@11e50000 {

Node name should be 'dsi-phy'.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

Re: [PATCH 2/5] arm64: dts: mt8192: Add mipi_tx node

[Nícolas F. R. A. Prado]

On Wed, Jun 29, 2022 at 08:13:55PM +0800, Allen-KH Cheng wrote:
> Add mipi_tx node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 731bdc665b94..a07edc82d403 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1095,6 +1095,16 @@
>  			};
>  		};
>  
> +		mipi_tx0: dsi-dphy@11e50000 {

Node name should be 'dsi-phy'.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

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Re: [PATCH 3/5] arm64: dts: mt8192: Add display nodes

[Nícolas F. R. A. Prado]

On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote:
> Add display nodes and gce info for mt8192 SoC.
> 
> GCE (Global Command Engine) properties to the display nodes in order to
> enable the usage of the CMDQ (Command Queue), which is required for
> operating the display.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136 +++++++++++++++++++++++
>  1 file changed, 136 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a07edc82d403..26d01544b4ea 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
[..]
>  
> +		mutex: mutex@14001000 {
> +			compatible = "mediatek,mt8192-disp-mutex";
> +			reg = <0 0x14001000 0 0x1000>;
> +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> +					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;

This node is missing power-domains.

> +		};
> +
[..]
> +		rdma0: rdma@14007000 {
> +			compatible = "mediatek,mt8192-disp-rdma";

dtbs_check is complaining that there isn't a "mediatek,mt8183-disp-rdma"
fallback compatible here. But given that the rdma driver matches directly to the
mt8192 compatible, I think the node here is fine, and the binding is the one
that should be updated.

> +			reg = <0 0x14007000 0 0x1000>;
> +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> +			mediatek,larb = <&larb0>;

mediatek,larb is no longer used, so drop it.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

Re: [PATCH 3/5] arm64: dts: mt8192: Add display nodes

[Nícolas F. R. A. Prado]

On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote:
> Add display nodes and gce info for mt8192 SoC.
> 
> GCE (Global Command Engine) properties to the display nodes in order to
> enable the usage of the CMDQ (Command Queue), which is required for
> operating the display.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136 +++++++++++++++++++++++
>  1 file changed, 136 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a07edc82d403..26d01544b4ea 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
[..]
>  
> +		mutex: mutex@14001000 {
> +			compatible = "mediatek,mt8192-disp-mutex";
> +			reg = <0 0x14001000 0 0x1000>;
> +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> +					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;

This node is missing power-domains.

> +		};
> +
[..]
> +		rdma0: rdma@14007000 {
> +			compatible = "mediatek,mt8192-disp-rdma";

dtbs_check is complaining that there isn't a "mediatek,mt8183-disp-rdma"
fallback compatible here. But given that the rdma driver matches directly to the
mt8192 compatible, I think the node here is fine, and the binding is the one
that should be updated.

> +			reg = <0 0x14007000 0 0x1000>;
> +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> +			mediatek,larb = <&larb0>;

mediatek,larb is no longer used, so drop it.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

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Re: [PATCH 4/5] arm64: dts: mt8192: Add dsi node

[Nícolas F. R. A. Prado]

On Wed, Jun 29, 2022 at 03:42:42PM +0200, AngeloGioacchino Del Regno wrote:
> Il 29/06/22 14:13, Allen-KH Cheng ha scritto:
> > Add dsi ndoe for mt8192 SoC.

Typo: s/ndoe/node.

> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++++
> >   1 file changed, 18 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 26d01544b4ea..72af328126de 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1334,6 +1334,24 @@
> >   			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> >   		};
> > +		dsi0: dsi@14010000 {
> > +			compatible = "mediatek,mt8183-dsi";
> > +			reg = <0 0x14010000 0 0x1000>;
> > +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> > +			mediatek,syscon-dsi = <&mmsys 0x140>;

Also drop this syscon-dsi property.

> > +			clocks = <&mmsys CLK_MM_DSI0>,
> > +				 <&mmsys CLK_MM_DSI_DSI0>,
> > +				 <&mipi_tx0>;
> > +			clock-names = "engine", "digital", "hs";
> > +			phys = <&mipi_tx0>;
> > +			phy-names = "dphy";

It's also missing power-domains.

> 
> resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
> 
> ^^^ This is missing, please add it and resend :-)

Also, when this is added you'll need

#include <dt-bindings/reset/mt8192-resets.h>

With those addressed,

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

> 
> > +			status = "disabled";
> > +
> > +			port {
> > +				dsi_out: endpoint { };
> > +			};
> > +		};
> > +
> >   		ovl_2l2: ovl@14014000 {
> >   			compatible = "mediatek,mt8192-disp-ovl-2l";
> >   			reg = <0 0x14014000 0 0x1000>;
> 
> 
> 

Re: [PATCH 4/5] arm64: dts: mt8192: Add dsi node

[Nícolas F. R. A. Prado]

On Wed, Jun 29, 2022 at 03:42:42PM +0200, AngeloGioacchino Del Regno wrote:
> Il 29/06/22 14:13, Allen-KH Cheng ha scritto:
> > Add dsi ndoe for mt8192 SoC.

Typo: s/ndoe/node.

> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++++
> >   1 file changed, 18 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 26d01544b4ea..72af328126de 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1334,6 +1334,24 @@
> >   			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> >   		};
> > +		dsi0: dsi@14010000 {
> > +			compatible = "mediatek,mt8183-dsi";
> > +			reg = <0 0x14010000 0 0x1000>;
> > +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> > +			mediatek,syscon-dsi = <&mmsys 0x140>;

Also drop this syscon-dsi property.

> > +			clocks = <&mmsys CLK_MM_DSI0>,
> > +				 <&mmsys CLK_MM_DSI_DSI0>,
> > +				 <&mipi_tx0>;
> > +			clock-names = "engine", "digital", "hs";
> > +			phys = <&mipi_tx0>;
> > +			phy-names = "dphy";

It's also missing power-domains.

> 
> resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
> 
> ^^^ This is missing, please add it and resend :-)

Also, when this is added you'll need

#include <dt-bindings/reset/mt8192-resets.h>

With those addressed,

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

> 
> > +			status = "disabled";
> > +
> > +			port {
> > +				dsi_out: endpoint { };
> > +			};
> > +		};
> > +
> >   		ovl_2l2: ovl@14014000 {
> >   			compatible = "mediatek,mt8192-disp-ovl-2l";
> >   			reg = <0 0x14014000 0 0x1000>;
> 
> 
> 

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Re: [PATCH 5/5] arm64: dts: mt8192: Add vcodec lat and core nodes

[Nícolas F. R. A. Prado]

On Wed, Jun 29, 2022 at 08:13:58PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

Re: [PATCH 5/5] arm64: dts: mt8192: Add vcodec lat and core nodes

[Nícolas F. R. A. Prado]

On Wed, Jun 29, 2022 at 08:13:58PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

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Re: [PATCH 3/5] arm64: dts: mt8192: Add display nodes

[allen-kh.cheng]

Hi Nícolas, 

On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote:
> On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote:
> > Add display nodes and gce info for mt8192 SoC.
> > 
> > GCE (Global Command Engine) properties to the display nodes in
> > order to
> > enable the usage of the CMDQ (Command Queue), which is required for
> > operating the display.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136
> > +++++++++++++++++++++++
> >  1 file changed, 136 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index a07edc82d403..26d01544b4ea 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> 
> [..]
> >  
> > +		mutex: mutex@14001000 {
> > +			compatible = "mediatek,mt8192-disp-mutex";
> > +			reg = <0 0x14001000 0 0x1000>;
> > +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > +			mediatek,gce-events =
> > <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> > +					      <CMDQ_EVENT_DISP_STREAM_D
> > ONE_ENG_EVENT_1>;
> 
> This node is missing power-domains.
> 
> > +		};
> > 
> 
> [..]
> > +		rdma0: rdma@14007000 {
> > +			compatible = "mediatek,mt8192-disp-rdma";
> 
> dtbs_check is complaining that there isn't a "mediatek,mt8183-disp-
> rdma"
> fallback compatible here. But given that the rdma driver matches
> directly to the
> mt8192 compatible, I think the node here is fine, and the binding is
> the one
> that should be updated.
> 

I have checked the binding and driver again.

I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove mt8192
compatible and data in mtk_disp_rdma.c because they are the same with
mt8183.

Do you think it is okay?

Thanks,
Allen


> > +			reg = <0 0x14007000 0 0x1000>;
> > +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> > +			mediatek,larb = <&larb0>;
> 
> mediatek,larb is no longer used, so drop it.
> 
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> 
> Thanks,
> Nícolas

Re: [PATCH 3/5] arm64: dts: mt8192: Add display nodes

[allen-kh.cheng]

Hi Nícolas, 

On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote:
> On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote:
> > Add display nodes and gce info for mt8192 SoC.
> > 
> > GCE (Global Command Engine) properties to the display nodes in
> > order to
> > enable the usage of the CMDQ (Command Queue), which is required for
> > operating the display.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136
> > +++++++++++++++++++++++
> >  1 file changed, 136 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index a07edc82d403..26d01544b4ea 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> 
> [..]
> >  
> > +		mutex: mutex@14001000 {
> > +			compatible = "mediatek,mt8192-disp-mutex";
> > +			reg = <0 0x14001000 0 0x1000>;
> > +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > +			mediatek,gce-events =
> > <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> > +					      <CMDQ_EVENT_DISP_STREAM_D
> > ONE_ENG_EVENT_1>;
> 
> This node is missing power-domains.
> 
> > +		};
> > 
> 
> [..]
> > +		rdma0: rdma@14007000 {
> > +			compatible = "mediatek,mt8192-disp-rdma";
> 
> dtbs_check is complaining that there isn't a "mediatek,mt8183-disp-
> rdma"
> fallback compatible here. But given that the rdma driver matches
> directly to the
> mt8192 compatible, I think the node here is fine, and the binding is
> the one
> that should be updated.
> 

I have checked the binding and driver again.

I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove mt8192
compatible and data in mtk_disp_rdma.c because they are the same with
mt8183.

Do you think it is okay?

Thanks,
Allen


> > +			reg = <0 0x14007000 0 0x1000>;
> > +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> > +			mediatek,larb = <&larb0>;
> 
> mediatek,larb is no longer used, so drop it.
> 
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> 
> Thanks,
> Nícolas


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Re: [PATCH 3/5] arm64: dts: mt8192: Add display nodes

[Nícolas F. R. A. Prado]

On Thu, Jun 30, 2022 at 05:41:31PM +0800, allen-kh.cheng wrote:
> Hi Nícolas, 
> 
> On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote:
> > On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote:
> > > Add display nodes and gce info for mt8192 SoC.
> > > 
> > > GCE (Global Command Engine) properties to the display nodes in
> > > order to
> > > enable the usage of the CMDQ (Command Queue), which is required for
> > > operating the display.
> > > 
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136
> > > +++++++++++++++++++++++
> > >  1 file changed, 136 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index a07edc82d403..26d01544b4ea 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
[..]
> > > +		rdma0: rdma@14007000 {
> > > +			compatible = "mediatek,mt8192-disp-rdma";
> > 
> > dtbs_check is complaining that there isn't a "mediatek,mt8183-disp-
> > rdma"
> > fallback compatible here. But given that the rdma driver matches
> > directly to the
> > mt8192 compatible, I think the node here is fine, and the binding is
> > the one
> > that should be updated.
> > 
> 
> I have checked the binding and driver again.
> 
> I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove mt8192
> compatible and data in mtk_disp_rdma.c because they are the same with
> mt8183.
> 
> Do you think it is okay?

Sure, that sounds good to me as well.

Thanks,
Nícolas

Re: [PATCH 3/5] arm64: dts: mt8192: Add display nodes

[Nícolas F. R. A. Prado]

On Thu, Jun 30, 2022 at 05:41:31PM +0800, allen-kh.cheng wrote:
> Hi Nícolas, 
> 
> On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote:
> > On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote:
> > > Add display nodes and gce info for mt8192 SoC.
> > > 
> > > GCE (Global Command Engine) properties to the display nodes in
> > > order to
> > > enable the usage of the CMDQ (Command Queue), which is required for
> > > operating the display.
> > > 
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136
> > > +++++++++++++++++++++++
> > >  1 file changed, 136 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index a07edc82d403..26d01544b4ea 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
[..]
> > > +		rdma0: rdma@14007000 {
> > > +			compatible = "mediatek,mt8192-disp-rdma";
> > 
> > dtbs_check is complaining that there isn't a "mediatek,mt8183-disp-
> > rdma"
> > fallback compatible here. But given that the rdma driver matches
> > directly to the
> > mt8192 compatible, I think the node here is fine, and the binding is
> > the one
> > that should be updated.
> > 
> 
> I have checked the binding and driver again.
> 
> I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove mt8192
> compatible and data in mtk_disp_rdma.c because they are the same with
> mt8183.
> 
> Do you think it is okay?

Sure, that sounds good to me as well.

Thanks,
Nícolas

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Re: [PATCH 3/5] arm64: dts: mt8192: Add display nodes

[Chen-Yu Tsai]

On Thu, Jun 30, 2022 at 9:42 PM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> On Thu, Jun 30, 2022 at 05:41:31PM +0800, allen-kh.cheng wrote:
> > Hi Nícolas,
> >
> > On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote:
> > > On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote:
> > > > Add display nodes and gce info for mt8192 SoC.
> > > >
> > > > GCE (Global Command Engine) properties to the display nodes in
> > > > order to
> > > > enable the usage of the CMDQ (Command Queue), which is required for
> > > > operating the display.
> > > >
> > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > ---
> > > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136
> > > > +++++++++++++++++++++++
> > > >  1 file changed, 136 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > index a07edc82d403..26d01544b4ea 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> [..]
> > > > +         rdma0: rdma@14007000 {
> > > > +                 compatible = "mediatek,mt8192-disp-rdma";
> > >
> > > dtbs_check is complaining that there isn't a "mediatek,mt8183-disp-
> > > rdma"
> > > fallback compatible here. But given that the rdma driver matches
> > > directly to the
> > > mt8192 compatible, I think the node here is fine, and the binding is
> > > the one
> > > that should be updated.
> > >
> >
> > I have checked the binding and driver again.
> >
> > I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove mt8192
> > compatible and data in mtk_disp_rdma.c because they are the same with
> > mt8183.
> >
> > Do you think it is okay?
>
> Sure, that sounds good to me as well.

That's backwards. MT8192 was released well before MT8186. The latter hasn't
even hit the market yet.

Please use "mediatek,mt8183-disp-rdma" as fallback. And you need to keep
"mediatek,mt8192-disp-rdma" as the most specific compatible string, because
we want SoC specific compatible strings.

For the driver, there isn't any difference between mt8183 and mt8192 for
the rdma part, so we might as well just remove the mt8192 compatible from
the driver.


Regards
ChenYu

Re: [PATCH 3/5] arm64: dts: mt8192: Add display nodes

[Chen-Yu Tsai]

On Thu, Jun 30, 2022 at 9:42 PM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> On Thu, Jun 30, 2022 at 05:41:31PM +0800, allen-kh.cheng wrote:
> > Hi Nícolas,
> >
> > On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote:
> > > On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote:
> > > > Add display nodes and gce info for mt8192 SoC.
> > > >
> > > > GCE (Global Command Engine) properties to the display nodes in
> > > > order to
> > > > enable the usage of the CMDQ (Command Queue), which is required for
> > > > operating the display.
> > > >
> > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > ---
> > > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136
> > > > +++++++++++++++++++++++
> > > >  1 file changed, 136 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > index a07edc82d403..26d01544b4ea 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> [..]
> > > > +         rdma0: rdma@14007000 {
> > > > +                 compatible = "mediatek,mt8192-disp-rdma";
> > >
> > > dtbs_check is complaining that there isn't a "mediatek,mt8183-disp-
> > > rdma"
> > > fallback compatible here. But given that the rdma driver matches
> > > directly to the
> > > mt8192 compatible, I think the node here is fine, and the binding is
> > > the one
> > > that should be updated.
> > >
> >
> > I have checked the binding and driver again.
> >
> > I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove mt8192
> > compatible and data in mtk_disp_rdma.c because they are the same with
> > mt8183.
> >
> > Do you think it is okay?
>
> Sure, that sounds good to me as well.

That's backwards. MT8192 was released well before MT8186. The latter hasn't
even hit the market yet.

Please use "mediatek,mt8183-disp-rdma" as fallback. And you need to keep
"mediatek,mt8192-disp-rdma" as the most specific compatible string, because
we want SoC specific compatible strings.

For the driver, there isn't any difference between mt8183 and mt8192 for
the rdma part, so we might as well just remove the mt8192 compatible from
the driver.


Regards
ChenYu

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Re: [PATCH 3/5] arm64: dts: mt8192: Add display nodes

[allen-kh.cheng]

Hi Chen-Yu,

On Fri, 2022-07-01 at 13:25 +0800, Chen-Yu Tsai wrote:
> On Thu, Jun 30, 2022 at 9:42 PM Nícolas F. R. A. Prado
> <nfraprado@collabora.com> wrote:
> > 
> > On Thu, Jun 30, 2022 at 05:41:31PM +0800, allen-kh.cheng wrote:
> > > Hi Nícolas,
> > > 
> > > On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote:
> > > > On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote:
> > > > > Add display nodes and gce info for mt8192 SoC.
> > > > > 
> > > > > GCE (Global Command Engine) properties to the display nodes
> > > > > in
> > > > > order to
> > > > > enable the usage of the CMDQ (Command Queue), which is
> > > > > required for
> > > > > operating the display.
> > > > > 
> > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > > angelogioacchino.delregno@collabora.com>
> > > > > ---
> > > > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136
> > > > > +++++++++++++++++++++++
> > > > >  1 file changed, 136 insertions(+)
> > > > > 
> > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > > index a07edc82d403..26d01544b4ea 100644
> > > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > 
> > [..]
> > > > > +         rdma0: rdma@14007000 {
> > > > > +                 compatible = "mediatek,mt8192-disp-rdma";
> > > > 
> > > > dtbs_check is complaining that there isn't a "mediatek,mt8183-
> > > > disp-
> > > > rdma"
> > > > fallback compatible here. But given that the rdma driver
> > > > matches
> > > > directly to the
> > > > mt8192 compatible, I think the node here is fine, and the
> > > > binding is
> > > > the one
> > > > that should be updated.
> > > > 
> > > 
> > > I have checked the binding and driver again.
> > > 
> > > I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove
> > > mt8192
> > > compatible and data in mtk_disp_rdma.c because they are the same
> > > with
> > > mt8183.
> > > 
> > > Do you think it is okay?
> > 
> > Sure, that sounds good to me as well.
> 
> That's backwards. MT8192 was released well before MT8186. The latter
> hasn't
> even hit the market yet.
> 
> Please use "mediatek,mt8183-disp-rdma" as fallback. And you need to
> keep
> "mediatek,mt8192-disp-rdma" as the most specific compatible string,
> because
> we want SoC specific compatible strings.
> 
> For the driver, there isn't any difference between mt8183 and mt8192
> for
> the rdma part, so we might as well just remove the mt8192 compatible
> from
> the driver.
> 
> 
> Regards
> ChenYu

Yes, I agree with you. it appears that for some reasons I made a typo
in my repy.

I will use "mediatek,mt8183-disp-rdma" as fallback in next version.

Thanks,
Allen

Re: [PATCH 3/5] arm64: dts: mt8192: Add display nodes

[allen-kh.cheng]

Hi Chen-Yu,

On Fri, 2022-07-01 at 13:25 +0800, Chen-Yu Tsai wrote:
> On Thu, Jun 30, 2022 at 9:42 PM Nícolas F. R. A. Prado
> <nfraprado@collabora.com> wrote:
> > 
> > On Thu, Jun 30, 2022 at 05:41:31PM +0800, allen-kh.cheng wrote:
> > > Hi Nícolas,
> > > 
> > > On Wed, 2022-06-29 at 19:24 -0400, Nícolas F. R. A. Prado wrote:
> > > > On Wed, Jun 29, 2022 at 08:13:56PM +0800, Allen-KH Cheng wrote:
> > > > > Add display nodes and gce info for mt8192 SoC.
> > > > > 
> > > > > GCE (Global Command Engine) properties to the display nodes
> > > > > in
> > > > > order to
> > > > > enable the usage of the CMDQ (Command Queue), which is
> > > > > required for
> > > > > operating the display.
> > > > > 
> > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > > angelogioacchino.delregno@collabora.com>
> > > > > ---
> > > > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 136
> > > > > +++++++++++++++++++++++
> > > > >  1 file changed, 136 insertions(+)
> > > > > 
> > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > > index a07edc82d403..26d01544b4ea 100644
> > > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > 
> > [..]
> > > > > +         rdma0: rdma@14007000 {
> > > > > +                 compatible = "mediatek,mt8192-disp-rdma";
> > > > 
> > > > dtbs_check is complaining that there isn't a "mediatek,mt8183-
> > > > disp-
> > > > rdma"
> > > > fallback compatible here. But given that the rdma driver
> > > > matches
> > > > directly to the
> > > > mt8192 compatible, I think the node here is fine, and the
> > > > binding is
> > > > the one
> > > > that should be updated.
> > > > 
> > > 
> > > I have checked the binding and driver again.
> > > 
> > > I prefer use "mediatek,mt8186-disp-rdma" as fallback and remove
> > > mt8192
> > > compatible and data in mtk_disp_rdma.c because they are the same
> > > with
> > > mt8183.
> > > 
> > > Do you think it is okay?
> > 
> > Sure, that sounds good to me as well.
> 
> That's backwards. MT8192 was released well before MT8186. The latter
> hasn't
> even hit the market yet.
> 
> Please use "mediatek,mt8183-disp-rdma" as fallback. And you need to
> keep
> "mediatek,mt8192-disp-rdma" as the most specific compatible string,
> because
> we want SoC specific compatible strings.
> 
> For the driver, there isn't any difference between mt8183 and mt8192
> for
> the rdma part, so we might as well just remove the mt8192 compatible
> from
> the driver.
> 
> 
> Regards
> ChenYu

Yes, I agree with you. it appears that for some reasons I made a typo
in my repy.

I will use "mediatek,mt8183-disp-rdma" as fallback in next version.

Thanks,
Allen




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