[PATCH v1 0/6] add support for MT8195 VPPSYS on MMSYS and MUTEX

[PATCH v1 0/6] add support for MT8195 VPPSYS on MMSYS and MUTEX

[Moudy Ho]

Hi,

This series add support for MT8195's two VPPSYS(Video Processor Pipe Subsystem),
under which there will be corresponding MMSYS and MUTEX settings that
need to be configured.

Roy-CW.Yeh (6):
  dt-bindings: soc: mediatek: Add support for MT8195 VPPSYS
  dts: arm64: mt8195: add MMSYS and MUTEX configuration for VPPSYS
  soc: mediatek: mmsys: add support for MT8195 VPPSYS
  soc: mediatek: mmsys: add config api for RSZ switching and DCM
  soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1
  soc: mediatek: mutex: support MT8195 VPPSYS

 .../bindings/soc/mediatek/mediatek,mutex.yaml |   1 +
 arch/arm64/boot/dts/mediatek/mt8195.dtsi      |  22 ++-
 drivers/soc/mediatek/mt8195-mmsys.h           |   8 ++
 drivers/soc/mediatek/mtk-mmsys.c              |  60 +++++++-
 drivers/soc/mediatek/mtk-mmsys.h              |   1 +
 drivers/soc/mediatek/mtk-mutex.c              | 129 ++++++++++++++++--
 include/linux/soc/mediatek/mtk-mmsys.h        |   4 +
 include/linux/soc/mediatek/mtk-mutex.h        |  36 +++++
 8 files changed, 250 insertions(+), 11 deletions(-)

-- 
2.18.0

[PATCH v1 0/6] add support for MT8195 VPPSYS on MMSYS and MUTEX

[Moudy Ho]

Hi,

This series add support for MT8195's two VPPSYS(Video Processor Pipe Subsystem),
under which there will be corresponding MMSYS and MUTEX settings that
need to be configured.

Roy-CW.Yeh (6):
  dt-bindings: soc: mediatek: Add support for MT8195 VPPSYS
  dts: arm64: mt8195: add MMSYS and MUTEX configuration for VPPSYS
  soc: mediatek: mmsys: add support for MT8195 VPPSYS
  soc: mediatek: mmsys: add config api for RSZ switching and DCM
  soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1
  soc: mediatek: mutex: support MT8195 VPPSYS

 .../bindings/soc/mediatek/mediatek,mutex.yaml |   1 +
 arch/arm64/boot/dts/mediatek/mt8195.dtsi      |  22 ++-
 drivers/soc/mediatek/mt8195-mmsys.h           |   8 ++
 drivers/soc/mediatek/mtk-mmsys.c              |  60 +++++++-
 drivers/soc/mediatek/mtk-mmsys.h              |   1 +
 drivers/soc/mediatek/mtk-mutex.c              | 129 ++++++++++++++++--
 include/linux/soc/mediatek/mtk-mmsys.h        |   4 +
 include/linux/soc/mediatek/mtk-mutex.h        |  36 +++++
 8 files changed, 250 insertions(+), 11 deletions(-)

-- 
2.18.0


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[PATCH v1 1/6] dt-bindings: soc: mediatek: Add support for MT8195 VPPSYS

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Add compatible for MT8195 VPPSYS.

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
index 9241e5fc7cff..5f044ba183fd 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -34,6 +34,7 @@ properties:
       - mediatek,mt8186-mdp3-mutex
       - mediatek,mt8192-disp-mutex
       - mediatek,mt8195-disp-mutex
+      - mediatek,mt8195-vpp-mutex
 
   reg:
     maxItems: 1
-- 
2.18.0

[PATCH v1 1/6] dt-bindings: soc: mediatek: Add support for MT8195 VPPSYS

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Add compatible for MT8195 VPPSYS.

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
index 9241e5fc7cff..5f044ba183fd 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -34,6 +34,7 @@ properties:
       - mediatek,mt8186-mdp3-mutex
       - mediatek,mt8192-disp-mutex
       - mediatek,mt8195-disp-mutex
+      - mediatek,mt8195-vpp-mutex
 
   reg:
     maxItems: 1
-- 
2.18.0


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Re: [PATCH v1 1/6] dt-bindings: soc: mediatek: Add support for MT8195 VPPSYS

[Krzysztof Kozlowski]

On 04/10/2022 11:33, Moudy Ho wrote:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Add compatible for MT8195 VPPSYS.
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>

Missing SoB.

Best regards,
Krzysztof

Re: [PATCH v1 1/6] dt-bindings: soc: mediatek: Add support for MT8195 VPPSYS

[Krzysztof Kozlowski]

On 04/10/2022 11:33, Moudy Ho wrote:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Add compatible for MT8195 VPPSYS.
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>

Missing SoB.

Best regards,
Krzysztof


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[PATCH v1 2/6] dts: arm64: mt8195: add MMSYS and MUTEX configuration for VPPSYS

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Compatible names of VPPSYS0 and VPPSYS1 should be renamed to
"mediatek,mt8195-mmsys" to match the description of the binding file.
Also, add two nodes for MT8195 VPPSYS0/1 MUTEX.

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..7f54fa7d0185 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1477,11 +1477,20 @@
 		};
 
 		vppsys0: clock-controller@14000000 {
-			compatible = "mediatek,mt8195-vppsys0";
+			compatible = "mediatek,mt8195-mmsys";
 			reg = <0 0x14000000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		vpp0-mutex@1400f000 {
+			compatible = "mediatek,mt8195-vpp-mutex";
+			reg = <0 0x1400f000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_MUTEX>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+		};
+
 		smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
 			compatible = "mediatek,mt8195-smi-sub-common";
 			reg = <0 0x14010000 0 0x1000>;
@@ -1582,11 +1591,20 @@
 		};
 
 		vppsys1: clock-controller@14f00000 {
-			compatible = "mediatek,mt8195-vppsys1";
+			compatible = "mediatek,mt8195-mmsys";
 			reg = <0 0x14f00000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		vpp1-mutex@14f01000 {
+			compatible = "mediatek,mt8195-vpp-mutex";
+			reg = <0 0x14f01000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+		};
+
 		larb5: larb@14f02000 {
 			compatible = "mediatek,mt8195-smi-larb";
 			reg = <0 0x14f02000 0 0x1000>;
-- 
2.18.0

[PATCH v1 2/6] dts: arm64: mt8195: add MMSYS and MUTEX configuration for VPPSYS

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Compatible names of VPPSYS0 and VPPSYS1 should be renamed to
"mediatek,mt8195-mmsys" to match the description of the binding file.
Also, add two nodes for MT8195 VPPSYS0/1 MUTEX.

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..7f54fa7d0185 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1477,11 +1477,20 @@
 		};
 
 		vppsys0: clock-controller@14000000 {
-			compatible = "mediatek,mt8195-vppsys0";
+			compatible = "mediatek,mt8195-mmsys";
 			reg = <0 0x14000000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		vpp0-mutex@1400f000 {
+			compatible = "mediatek,mt8195-vpp-mutex";
+			reg = <0 0x1400f000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_MUTEX>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+		};
+
 		smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
 			compatible = "mediatek,mt8195-smi-sub-common";
 			reg = <0 0x14010000 0 0x1000>;
@@ -1582,11 +1591,20 @@
 		};
 
 		vppsys1: clock-controller@14f00000 {
-			compatible = "mediatek,mt8195-vppsys1";
+			compatible = "mediatek,mt8195-mmsys";
 			reg = <0 0x14f00000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		vpp1-mutex@14f01000 {
+			compatible = "mediatek,mt8195-vpp-mutex";
+			reg = <0 0x14f01000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+		};
+
 		larb5: larb@14f02000 {
 			compatible = "mediatek,mt8195-smi-larb";
 			reg = <0 0x14f02000 0 0x1000>;
-- 
2.18.0


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Re: [PATCH v1 2/6] dts: arm64: mt8195: add MMSYS and MUTEX configuration for VPPSYS

[Allen-KH Cheng (程冠勳)]

Hi Moudy,

On Tue, 2022-10-04 at 17:33 +0800, Moudy Ho wrote:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Compatible names of VPPSYS0 and VPPSYS1 should be renamed to
> "mediatek,mt8195-mmsys" to match the description of the binding file.
> Also, add two nodes for MT8195 VPPSYS0/1 MUTEX.
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++--
>  1 file changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..7f54fa7d0185 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1477,11 +1477,20 @@
>  		};
>  
>  		vppsys0: clock-controller@14000000 {
> -			compatible = "mediatek,mt8195-vppsys0";
> +			compatible = "mediatek,mt8195-mmsys";
>  			reg = <0 0x14000000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce1
> SUBSYS_1400XXXX 0 0x1000>;
>  			#clock-cells = <1>;
>  		};
>  

I run "ARCH=arm64 make dtbs check" and some of the tests failed.

The node name should be 'syscon' from mediatek/mediatek,mmsys.yaml.


> +		vpp0-mutex@1400f000 {
> +			compatible = "mediatek,mt8195-vpp-mutex";
> +			reg = <0 0x1400f000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce1
> SUBSYS_1400XXXX 0xf000 0x1000>;
> +			clocks = <&vppsys0 CLK_VPP0_MUTEX>;
> +			power-domains = <&spm
> MT8195_POWER_DOMAIN_VPPSYS0>;
> +		};
> +

'interrupts' is a required property from mediatek/mediatek,mutex.yaml


>  		smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
>  			compatible = "mediatek,mt8195-smi-sub-common";
>  			reg = <0 0x14010000 0 0x1000>;
> @@ -1582,11 +1591,20 @@
>  		};
>  
>  		vppsys1: clock-controller@14f00000 {
> -			compatible = "mediatek,mt8195-vppsys1";
> +			compatible = "mediatek,mt8195-mmsys";
>  			reg = <0 0x14f00000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce1
> SUBSYS_14f0XXXX 0 0x1000>;

Node name: syscon.

>  			#clock-cells = <1>;
>  		};
>  
> +		vpp1-mutex@14f01000 {
> +			compatible = "mediatek,mt8195-vpp-mutex";
> +			reg = <0 0x14f01000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce1
> SUBSYS_14f0XXXX 0x1000 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
> +			power-domains = <&spm
> MT8195_POWER_DOMAIN_VPPSYS1>;
> +		};
> +

'interrupts' is a required property

Thanks,
Allen

>  		larb5: larb@14f02000 {
>  			compatible = "mediatek,mt8195-smi-larb";
>  			reg = <0 0x14f02000 0 0x1000>;

Re: [PATCH v1 2/6] dts: arm64: mt8195: add MMSYS and MUTEX configuration for VPPSYS

[Allen-KH Cheng (程冠勳)]

Hi Moudy,

On Tue, 2022-10-04 at 17:33 +0800, Moudy Ho wrote:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Compatible names of VPPSYS0 and VPPSYS1 should be renamed to
> "mediatek,mt8195-mmsys" to match the description of the binding file.
> Also, add two nodes for MT8195 VPPSYS0/1 MUTEX.
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++--
>  1 file changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..7f54fa7d0185 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1477,11 +1477,20 @@
>  		};
>  
>  		vppsys0: clock-controller@14000000 {
> -			compatible = "mediatek,mt8195-vppsys0";
> +			compatible = "mediatek,mt8195-mmsys";
>  			reg = <0 0x14000000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce1
> SUBSYS_1400XXXX 0 0x1000>;
>  			#clock-cells = <1>;
>  		};
>  

I run "ARCH=arm64 make dtbs check" and some of the tests failed.

The node name should be 'syscon' from mediatek/mediatek,mmsys.yaml.


> +		vpp0-mutex@1400f000 {
> +			compatible = "mediatek,mt8195-vpp-mutex";
> +			reg = <0 0x1400f000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce1
> SUBSYS_1400XXXX 0xf000 0x1000>;
> +			clocks = <&vppsys0 CLK_VPP0_MUTEX>;
> +			power-domains = <&spm
> MT8195_POWER_DOMAIN_VPPSYS0>;
> +		};
> +

'interrupts' is a required property from mediatek/mediatek,mutex.yaml


>  		smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
>  			compatible = "mediatek,mt8195-smi-sub-common";
>  			reg = <0 0x14010000 0 0x1000>;
> @@ -1582,11 +1591,20 @@
>  		};
>  
>  		vppsys1: clock-controller@14f00000 {
> -			compatible = "mediatek,mt8195-vppsys1";
> +			compatible = "mediatek,mt8195-mmsys";
>  			reg = <0 0x14f00000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce1
> SUBSYS_14f0XXXX 0 0x1000>;

Node name: syscon.

>  			#clock-cells = <1>;
>  		};
>  
> +		vpp1-mutex@14f01000 {
> +			compatible = "mediatek,mt8195-vpp-mutex";
> +			reg = <0 0x14f01000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce1
> SUBSYS_14f0XXXX 0x1000 0x1000>;
> +			clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
> +			power-domains = <&spm
> MT8195_POWER_DOMAIN_VPPSYS1>;
> +		};
> +

'interrupts' is a required property

Thanks,
Allen

>  		larb5: larb@14f02000 {
>  			compatible = "mediatek,mt8195-smi-larb";
>  			reg = <0 0x14f02000 0 0x1000>;



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Re: [PATCH v1 2/6] dts: arm64: mt8195: add MMSYS and MUTEX configuration for VPPSYS

[moudy ho]

On Tue, 2022-10-04 at 19:46 +0800, Allen-KH Cheng (程冠勳) wrote:
> Hi Moudy,
> 
> On Tue, 2022-10-04 at 17:33 +0800, Moudy Ho wrote:
> > From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> > 
> > Compatible names of VPPSYS0 and VPPSYS1 should be renamed to
> > "mediatek,mt8195-mmsys" to match the description of the binding
> > file.
> > Also, add two nodes for MT8195 VPPSYS0/1 MUTEX.
> > 
> > Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22
> > ++++++++++++++++++++--
> >  1 file changed, 20 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 905d1a90b406..7f54fa7d0185 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1477,11 +1477,20 @@
> >  		};
> >  
> >  		vppsys0: clock-controller@14000000 {
> > -			compatible = "mediatek,mt8195-vppsys0";
> > +			compatible = "mediatek,mt8195-mmsys";
> >  			reg = <0 0x14000000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce1
> > SUBSYS_1400XXXX 0 0x1000>;
> >  			#clock-cells = <1>;
> >  		};
> >  
> 
> I run "ARCH=arm64 make dtbs check" and some of the tests failed.
> 
> The node name should be 'syscon' from mediatek/mediatek,mmsys.yaml.
> 
> 
> > +		vpp0-mutex@1400f000 {
> > +			compatible = "mediatek,mt8195-vpp-mutex";
> > +			reg = <0 0x1400f000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce1
> > SUBSYS_1400XXXX 0xf000 0x1000>;
> > +			clocks = <&vppsys0 CLK_VPP0_MUTEX>;
> > +			power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS0>;
> > +		};
> > +
> 
> 'interrupts' is a required property from mediatek/mediatek,mutex.yaml
> 
> 
> >  		smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
> >  			compatible = "mediatek,mt8195-smi-sub-common";
> >  			reg = <0 0x14010000 0 0x1000>;
> > @@ -1582,11 +1591,20 @@
> >  		};
> >  
> >  		vppsys1: clock-controller@14f00000 {
> > -			compatible = "mediatek,mt8195-vppsys1";
> > +			compatible = "mediatek,mt8195-mmsys";
> >  			reg = <0 0x14f00000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f0XXXX 0 0x1000>;
> 
> Node name: syscon.
> 
> >  			#clock-cells = <1>;
> >  		};
> >  
> > +		vpp1-mutex@14f01000 {
> > +			compatible = "mediatek,mt8195-vpp-mutex";
> > +			reg = <0 0x14f01000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f0XXXX 0x1000 0x1000>;
> > +			clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
> > +			power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS1>;
> > +		};
> > +
> 
> 'interrupts' is a required property
> 
> Thanks,
> Allen
> 

Hi Allen,

Apologies for the failed test, I'll check again by adding dtsb_check
instead of just dt_binding_check .

Thanks & Regards,
Moudy

> >  		larb5: larb@14f02000 {
> >  			compatible = "mediatek,mt8195-smi-larb";
> >  			reg = <0 0x14f02000 0 0x1000>;
> 
> 
> 

Re: [PATCH v1 2/6] dts: arm64: mt8195: add MMSYS and MUTEX configuration for VPPSYS

[moudy ho]

On Tue, 2022-10-04 at 19:46 +0800, Allen-KH Cheng (程冠勳) wrote:
> Hi Moudy,
> 
> On Tue, 2022-10-04 at 17:33 +0800, Moudy Ho wrote:
> > From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> > 
> > Compatible names of VPPSYS0 and VPPSYS1 should be renamed to
> > "mediatek,mt8195-mmsys" to match the description of the binding
> > file.
> > Also, add two nodes for MT8195 VPPSYS0/1 MUTEX.
> > 
> > Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22
> > ++++++++++++++++++++--
> >  1 file changed, 20 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 905d1a90b406..7f54fa7d0185 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1477,11 +1477,20 @@
> >  		};
> >  
> >  		vppsys0: clock-controller@14000000 {
> > -			compatible = "mediatek,mt8195-vppsys0";
> > +			compatible = "mediatek,mt8195-mmsys";
> >  			reg = <0 0x14000000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce1
> > SUBSYS_1400XXXX 0 0x1000>;
> >  			#clock-cells = <1>;
> >  		};
> >  
> 
> I run "ARCH=arm64 make dtbs check" and some of the tests failed.
> 
> The node name should be 'syscon' from mediatek/mediatek,mmsys.yaml.
> 
> 
> > +		vpp0-mutex@1400f000 {
> > +			compatible = "mediatek,mt8195-vpp-mutex";
> > +			reg = <0 0x1400f000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce1
> > SUBSYS_1400XXXX 0xf000 0x1000>;
> > +			clocks = <&vppsys0 CLK_VPP0_MUTEX>;
> > +			power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS0>;
> > +		};
> > +
> 
> 'interrupts' is a required property from mediatek/mediatek,mutex.yaml
> 
> 
> >  		smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
> >  			compatible = "mediatek,mt8195-smi-sub-common";
> >  			reg = <0 0x14010000 0 0x1000>;
> > @@ -1582,11 +1591,20 @@
> >  		};
> >  
> >  		vppsys1: clock-controller@14f00000 {
> > -			compatible = "mediatek,mt8195-vppsys1";
> > +			compatible = "mediatek,mt8195-mmsys";
> >  			reg = <0 0x14f00000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f0XXXX 0 0x1000>;
> 
> Node name: syscon.
> 
> >  			#clock-cells = <1>;
> >  		};
> >  
> > +		vpp1-mutex@14f01000 {
> > +			compatible = "mediatek,mt8195-vpp-mutex";
> > +			reg = <0 0x14f01000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f0XXXX 0x1000 0x1000>;
> > +			clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
> > +			power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS1>;
> > +		};
> > +
> 
> 'interrupts' is a required property
> 
> Thanks,
> Allen
> 

Hi Allen,

Apologies for the failed test, I'll check again by adding dtsb_check
instead of just dt_binding_check .

Thanks & Regards,
Moudy

> >  		larb5: larb@14f02000 {
> >  			compatible = "mediatek,mt8195-smi-larb";
> >  			reg = <0 0x14f02000 0 0x1000>;
> 
> 
> 


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Re: [PATCH v1 2/6] dts: arm64: mt8195: add MMSYS and MUTEX configuration for VPPSYS

[Krzysztof Kozlowski]

On 04/10/2022 11:33, Moudy Ho wrote:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Compatible names of VPPSYS0 and VPPSYS1 should be renamed to
> "mediatek,mt8195-mmsys" to match the description of the binding file.
> Also, add two nodes for MT8195 VPPSYS0/1 MUTEX.
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++--
>  1 file changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..7f54fa7d0185 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1477,11 +1477,20 @@
>  		};
>  
>  		vppsys0: clock-controller@14000000 {
> -			compatible = "mediatek,mt8195-vppsys0";
> +			compatible = "mediatek,mt8195-mmsys";

This does not look like matching bindings. Last patch for bindings was
requiring this to be prepended with vdosys0 and followed with syscon.

Best regards,
Krzysztof

Re: [PATCH v1 2/6] dts: arm64: mt8195: add MMSYS and MUTEX configuration for VPPSYS

[Krzysztof Kozlowski]

On 04/10/2022 11:33, Moudy Ho wrote:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Compatible names of VPPSYS0 and VPPSYS1 should be renamed to
> "mediatek,mt8195-mmsys" to match the description of the binding file.
> Also, add two nodes for MT8195 VPPSYS0/1 MUTEX.
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++--
>  1 file changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..7f54fa7d0185 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1477,11 +1477,20 @@
>  		};
>  
>  		vppsys0: clock-controller@14000000 {
> -			compatible = "mediatek,mt8195-vppsys0";
> +			compatible = "mediatek,mt8195-mmsys";

This does not look like matching bindings. Last patch for bindings was
requiring this to be prepended with vdosys0 and followed with syscon.

Best regards,
Krzysztof


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[PATCH v1 3/6] soc: mediatek: mmsys: add support for MT8195 VPPSYS

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Add MT8195 VPPSYS0 and VPPSYS1 driver data.

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c | 20 +++++++++++++++++++-
 drivers/soc/mediatek/mtk-mmsys.h |  1 +
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index d2c7a87aab87..c4d15f99f853 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -149,11 +149,25 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
 	.clk_driver = "clk-mt8195-vdo1",
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
+	.io_start = 0x14000000,
+	.clk_driver = "clk-mt8195-vpp0",
+	.is_copies = true,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
+	.io_start = 0x14f00000,
+	.clk_driver = "clk-mt8195-vpp1",
+	.is_copies = true,
+};
+
 static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
-	.num_drv_data = 2,
+	.num_drv_data = 4,
 	.drv_data = {
 		&mt8195_vdosys0_driver_data,
 		&mt8195_vdosys1_driver_data,
+		&mt8195_vppsys0_driver_data,
+		&mt8195_vppsys1_driver_data,
 	},
 };
 
@@ -360,6 +374,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	if (IS_ERR(clks))
 		return PTR_ERR(clks);
 
+	if (mmsys->data->is_copies)
+		goto out_probe_done;
+
 	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
 					    PLATFORM_DEVID_AUTO, NULL, 0);
 	if (IS_ERR(drm)) {
@@ -367,6 +384,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return PTR_ERR(drm);
 	}
 
+out_probe_done:
 	return 0;
 }
 
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index f01ba206481d..d454b4a256af 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
+	bool is_copies;
 };
 
 struct mtk_mmsys_match_data {
-- 
2.18.0

[PATCH v1 3/6] soc: mediatek: mmsys: add support for MT8195 VPPSYS

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Add MT8195 VPPSYS0 and VPPSYS1 driver data.

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c | 20 +++++++++++++++++++-
 drivers/soc/mediatek/mtk-mmsys.h |  1 +
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index d2c7a87aab87..c4d15f99f853 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -149,11 +149,25 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
 	.clk_driver = "clk-mt8195-vdo1",
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
+	.io_start = 0x14000000,
+	.clk_driver = "clk-mt8195-vpp0",
+	.is_copies = true,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
+	.io_start = 0x14f00000,
+	.clk_driver = "clk-mt8195-vpp1",
+	.is_copies = true,
+};
+
 static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
-	.num_drv_data = 2,
+	.num_drv_data = 4,
 	.drv_data = {
 		&mt8195_vdosys0_driver_data,
 		&mt8195_vdosys1_driver_data,
+		&mt8195_vppsys0_driver_data,
+		&mt8195_vppsys1_driver_data,
 	},
 };
 
@@ -360,6 +374,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	if (IS_ERR(clks))
 		return PTR_ERR(clks);
 
+	if (mmsys->data->is_copies)
+		goto out_probe_done;
+
 	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
 					    PLATFORM_DEVID_AUTO, NULL, 0);
 	if (IS_ERR(drm)) {
@@ -367,6 +384,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return PTR_ERR(drm);
 	}
 
+out_probe_done:
 	return 0;
 }
 
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index f01ba206481d..d454b4a256af 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
+	bool is_copies;
 };
 
 struct mtk_mmsys_match_data {
-- 
2.18.0


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Re: [PATCH v1 3/6] soc: mediatek: mmsys: add support for MT8195 VPPSYS

[AngeloGioacchino Del Regno]

Il 04/10/22 11:33, Moudy Ho ha scritto:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Add MT8195 VPPSYS0 and VPPSYS1 driver data.
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
>   drivers/soc/mediatek/mtk-mmsys.c | 20 +++++++++++++++++++-
>   drivers/soc/mediatek/mtk-mmsys.h |  1 +
>   2 files changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index d2c7a87aab87..c4d15f99f853 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -149,11 +149,25 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
>   	.clk_driver = "clk-mt8195-vdo1",
>   };
>   
> +static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
> +	.io_start = 0x14000000,
> +	.clk_driver = "clk-mt8195-vpp0",
> +	.is_copies = true,
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
> +	.io_start = 0x14f00000,
> +	.clk_driver = "clk-mt8195-vpp1",
> +	.is_copies = true,
> +};
> +
>   static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> -	.num_drv_data = 2,
> +	.num_drv_data = 4,

After a long discussion, it was chosen to not use the io_start way, but to change
the devicetree compatible....

Check this series, and rebase on top of it:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=681097

Cheers,
Angelo

>   	.drv_data = {
>   		&mt8195_vdosys0_driver_data,
>   		&mt8195_vdosys1_driver_data,
> +		&mt8195_vppsys0_driver_data,
> +		&mt8195_vppsys1_driver_data,
>   	},
>   };
>   
> @@ -360,6 +374,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
>   	if (IS_ERR(clks))
>   		return PTR_ERR(clks);
>   
> +	if (mmsys->data->is_copies)

I don't get what "is_copies" means, sorry. I'm sure that there's a better name
for this one.

> +		goto out_probe_done;
> +
>   	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
>   					    PLATFORM_DEVID_AUTO, NULL, 0);
>   	if (IS_ERR(drm)) {

Regards,
Angelo

Re: [PATCH v1 3/6] soc: mediatek: mmsys: add support for MT8195 VPPSYS

[AngeloGioacchino Del Regno]

Il 04/10/22 11:33, Moudy Ho ha scritto:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Add MT8195 VPPSYS0 and VPPSYS1 driver data.
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
>   drivers/soc/mediatek/mtk-mmsys.c | 20 +++++++++++++++++++-
>   drivers/soc/mediatek/mtk-mmsys.h |  1 +
>   2 files changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index d2c7a87aab87..c4d15f99f853 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -149,11 +149,25 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
>   	.clk_driver = "clk-mt8195-vdo1",
>   };
>   
> +static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
> +	.io_start = 0x14000000,
> +	.clk_driver = "clk-mt8195-vpp0",
> +	.is_copies = true,
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
> +	.io_start = 0x14f00000,
> +	.clk_driver = "clk-mt8195-vpp1",
> +	.is_copies = true,
> +};
> +
>   static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> -	.num_drv_data = 2,
> +	.num_drv_data = 4,

After a long discussion, it was chosen to not use the io_start way, but to change
the devicetree compatible....

Check this series, and rebase on top of it:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=681097

Cheers,
Angelo

>   	.drv_data = {
>   		&mt8195_vdosys0_driver_data,
>   		&mt8195_vdosys1_driver_data,
> +		&mt8195_vppsys0_driver_data,
> +		&mt8195_vppsys1_driver_data,
>   	},
>   };
>   
> @@ -360,6 +374,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
>   	if (IS_ERR(clks))
>   		return PTR_ERR(clks);
>   
> +	if (mmsys->data->is_copies)

I don't get what "is_copies" means, sorry. I'm sure that there's a better name
for this one.

> +		goto out_probe_done;
> +
>   	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
>   					    PLATFORM_DEVID_AUTO, NULL, 0);
>   	if (IS_ERR(drm)) {

Regards,
Angelo


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Re: [PATCH v1 3/6] soc: mediatek: mmsys: add support for MT8195 VPPSYS

[moudy ho]

Hi Angelo,

On Tue, 2022-10-04 at 14:17 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/10/22 11:33, Moudy Ho ha scritto:
> > From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> > 
> > Add MT8195 VPPSYS0 and VPPSYS1 driver data.
> > 
> > Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> > ---
> >   drivers/soc/mediatek/mtk-mmsys.c | 20 +++++++++++++++++++-
> >   drivers/soc/mediatek/mtk-mmsys.h |  1 +
> >   2 files changed, 20 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index d2c7a87aab87..c4d15f99f853 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -149,11 +149,25 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> >   	.clk_driver = "clk-mt8195-vdo1",
> >   };
> >   
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vppsys0_driver_data = {
> > +	.io_start = 0x14000000,
> > +	.clk_driver = "clk-mt8195-vpp0",
> > +	.is_copies = true,
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vppsys1_driver_data = {
> > +	.io_start = 0x14f00000,
> > +	.clk_driver = "clk-mt8195-vpp1",
> > +	.is_copies = true,
> > +};
> > +
> >   static const struct mtk_mmsys_match_data mt8195_mmsys_match_data
> > = {
> > -	.num_drv_data = 2,
> > +	.num_drv_data = 4,
> 
> After a long discussion, it was chosen to not use the io_start way,
> but to change
> the devicetree compatible....
> 
> Check this series, and rebase on top of it:
> 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=681097__;!!CTRNKA9wMg0ARbw!3qjICTDNn82OJyHA0U_WAuEnMSy1mL31r14l72jY5rSrBaJN0_tDU_08BBZcEm6V$
>  
> 
> Cheers,
> Angelo
> 

Sorry for not noticing the change here, I'll rebase on it and fix
accordingly.

> >   	.drv_data = {
> >   		&mt8195_vdosys0_driver_data,
> >   		&mt8195_vdosys1_driver_data,
> > +		&mt8195_vppsys0_driver_data,
> > +		&mt8195_vppsys1_driver_data,
> >   	},
> >   };
> >   
> > @@ -360,6 +374,9 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> >   	if (IS_ERR(clks))
> >   		return PTR_ERR(clks);
> >   
> > +	if (mmsys->data->is_copies)
> 
> I don't get what "is_copies" means, sorry. I'm sure that there's a
> better name
> for this one.
> 

It's a flag to avoid probing the DRM driver multiple times.
Would it be more readable if the name was changed to "is_vppsys"?

> > +		goto out_probe_done;
> > +
> >   	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> >   					    PLATFORM_DEVID_AUTO, NULL,
> > 0);
> >   	if (IS_ERR(drm)) {
> 
> Regards,
> Angelo
> 

Thanks and Regards,
Moudy

Re: [PATCH v1 3/6] soc: mediatek: mmsys: add support for MT8195 VPPSYS

[moudy ho]

Hi Angelo,

On Tue, 2022-10-04 at 14:17 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/10/22 11:33, Moudy Ho ha scritto:
> > From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> > 
> > Add MT8195 VPPSYS0 and VPPSYS1 driver data.
> > 
> > Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> > ---
> >   drivers/soc/mediatek/mtk-mmsys.c | 20 +++++++++++++++++++-
> >   drivers/soc/mediatek/mtk-mmsys.h |  1 +
> >   2 files changed, 20 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index d2c7a87aab87..c4d15f99f853 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -149,11 +149,25 @@ static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> >   	.clk_driver = "clk-mt8195-vdo1",
> >   };
> >   
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vppsys0_driver_data = {
> > +	.io_start = 0x14000000,
> > +	.clk_driver = "clk-mt8195-vpp0",
> > +	.is_copies = true,
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vppsys1_driver_data = {
> > +	.io_start = 0x14f00000,
> > +	.clk_driver = "clk-mt8195-vpp1",
> > +	.is_copies = true,
> > +};
> > +
> >   static const struct mtk_mmsys_match_data mt8195_mmsys_match_data
> > = {
> > -	.num_drv_data = 2,
> > +	.num_drv_data = 4,
> 
> After a long discussion, it was chosen to not use the io_start way,
> but to change
> the devicetree compatible....
> 
> Check this series, and rebase on top of it:
> 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=681097__;!!CTRNKA9wMg0ARbw!3qjICTDNn82OJyHA0U_WAuEnMSy1mL31r14l72jY5rSrBaJN0_tDU_08BBZcEm6V$
>  
> 
> Cheers,
> Angelo
> 

Sorry for not noticing the change here, I'll rebase on it and fix
accordingly.

> >   	.drv_data = {
> >   		&mt8195_vdosys0_driver_data,
> >   		&mt8195_vdosys1_driver_data,
> > +		&mt8195_vppsys0_driver_data,
> > +		&mt8195_vppsys1_driver_data,
> >   	},
> >   };
> >   
> > @@ -360,6 +374,9 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> >   	if (IS_ERR(clks))
> >   		return PTR_ERR(clks);
> >   
> > +	if (mmsys->data->is_copies)
> 
> I don't get what "is_copies" means, sorry. I'm sure that there's a
> better name
> for this one.
> 

It's a flag to avoid probing the DRM driver multiple times.
Would it be more readable if the name was changed to "is_vppsys"?

> > +		goto out_probe_done;
> > +
> >   	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> >   					    PLATFORM_DEVID_AUTO, NULL,
> > 0);
> >   	if (IS_ERR(drm)) {
> 
> Regards,
> Angelo
> 

Thanks and Regards,
Moudy


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[PATCH v1 4/6] soc: mediatek: mmsys: add config api for RSZ switching and DCM

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Due to MT8195 HW design, some RSZs have additional settings that
need to be configured in MMSYS.

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 drivers/soc/mediatek/mt8195-mmsys.h    |  8 ++++++
 drivers/soc/mediatek/mtk-mmsys.c       | 40 ++++++++++++++++++++++++++
 include/linux/soc/mediatek/mtk-mmsys.h |  4 +++
 3 files changed, 52 insertions(+)

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index abfe94a30248..e0cf13d09763 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -75,6 +75,14 @@
 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
 
+/* VPPSYS1 */
+#define MT8195_SVPP1_HW_DCM_1ST_DIS0				0x150
+#define MT8195_SVPP1_HW_DCM_1ST_DIS1				0x160
+#define MT8195_SVPP1_HW_DCM_2ND_DIS0				0x1a0
+#define MT8195_SVPP1_HW_DCM_2ND_DIS1				0x1b0
+#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH				0xf48
+#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH				0xf74
+
 static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index c4d15f99f853..c98cfcb7db38 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -261,6 +261,46 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
 
+void mtk_mmsys_merge_config(struct device *dev, u32 id, bool enable)
+{
+	u32 reg;
+
+	switch (id) {
+	case 2:
+		reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH;
+		break;
+	case 3:
+		reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH;
+		break;
+	default:
+		dev_err(dev, "Invalid id %d\n", id);
+		return;
+	}
+
+	mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_merge_config);
+
+void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable)
+{
+	u32 val = 0;
+
+	if (enable)
+		val = BIT(25);
+	mtk_mmsys_update_bits(dev_get_drvdata(dev),
+			      MT8195_SVPP1_HW_DCM_1ST_DIS0, BIT(25), val);
+	mtk_mmsys_update_bits(dev_get_drvdata(dev),
+			      MT8195_SVPP1_HW_DCM_2ND_DIS0, BIT(25), val);
+
+	if (enable)
+		val = (BIT(4) | BIT(5));
+	mtk_mmsys_update_bits(dev_get_drvdata(dev),
+			      MT8195_SVPP1_HW_DCM_1ST_DIS1, (BIT(4) | BIT(5)), val);
+	mtk_mmsys_update_bits(dev_get_drvdata(dev),
+			      MT8195_SVPP1_HW_DCM_2ND_DIS1, (BIT(4) | BIT(5)), val);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_rsz_dcm_config);
+
 static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
 				  bool assert)
 {
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index d2b02bb43768..2d5c7fe920b0 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -67,4 +67,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
 
 void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
 
+void mtk_mmsys_merge_config(struct device *dev, u32 id, bool enable);
+
+void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable);
+
 #endif /* __MTK_MMSYS_H */
-- 
2.18.0

[PATCH v1 4/6] soc: mediatek: mmsys: add config api for RSZ switching and DCM

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Due to MT8195 HW design, some RSZs have additional settings that
need to be configured in MMSYS.

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 drivers/soc/mediatek/mt8195-mmsys.h    |  8 ++++++
 drivers/soc/mediatek/mtk-mmsys.c       | 40 ++++++++++++++++++++++++++
 include/linux/soc/mediatek/mtk-mmsys.h |  4 +++
 3 files changed, 52 insertions(+)

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index abfe94a30248..e0cf13d09763 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -75,6 +75,14 @@
 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
 
+/* VPPSYS1 */
+#define MT8195_SVPP1_HW_DCM_1ST_DIS0				0x150
+#define MT8195_SVPP1_HW_DCM_1ST_DIS1				0x160
+#define MT8195_SVPP1_HW_DCM_2ND_DIS0				0x1a0
+#define MT8195_SVPP1_HW_DCM_2ND_DIS1				0x1b0
+#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH				0xf48
+#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH				0xf74
+
 static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index c4d15f99f853..c98cfcb7db38 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -261,6 +261,46 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
 
+void mtk_mmsys_merge_config(struct device *dev, u32 id, bool enable)
+{
+	u32 reg;
+
+	switch (id) {
+	case 2:
+		reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH;
+		break;
+	case 3:
+		reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH;
+		break;
+	default:
+		dev_err(dev, "Invalid id %d\n", id);
+		return;
+	}
+
+	mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_merge_config);
+
+void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable)
+{
+	u32 val = 0;
+
+	if (enable)
+		val = BIT(25);
+	mtk_mmsys_update_bits(dev_get_drvdata(dev),
+			      MT8195_SVPP1_HW_DCM_1ST_DIS0, BIT(25), val);
+	mtk_mmsys_update_bits(dev_get_drvdata(dev),
+			      MT8195_SVPP1_HW_DCM_2ND_DIS0, BIT(25), val);
+
+	if (enable)
+		val = (BIT(4) | BIT(5));
+	mtk_mmsys_update_bits(dev_get_drvdata(dev),
+			      MT8195_SVPP1_HW_DCM_1ST_DIS1, (BIT(4) | BIT(5)), val);
+	mtk_mmsys_update_bits(dev_get_drvdata(dev),
+			      MT8195_SVPP1_HW_DCM_2ND_DIS1, (BIT(4) | BIT(5)), val);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_rsz_dcm_config);
+
 static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
 				  bool assert)
 {
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index d2b02bb43768..2d5c7fe920b0 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -67,4 +67,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
 
 void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
 
+void mtk_mmsys_merge_config(struct device *dev, u32 id, bool enable);
+
+void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable);
+
 #endif /* __MTK_MMSYS_H */
-- 
2.18.0


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Re: [PATCH v1 4/6] soc: mediatek: mmsys: add config api for RSZ switching and DCM

[AngeloGioacchino Del Regno]

Il 04/10/22 11:33, Moudy Ho ha scritto:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Due to MT8195 HW design, some RSZs have additional settings that
> need to be configured in MMSYS.
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>

Hello Moudy,

please remember that you have to add your Signed-off-by tag to all of the commits
that you're sending, even if you're not the author, otherwise they are not
acceptable.

> ---
>   drivers/soc/mediatek/mt8195-mmsys.h    |  8 ++++++
>   drivers/soc/mediatek/mtk-mmsys.c       | 40 ++++++++++++++++++++++++++
>   include/linux/soc/mediatek/mtk-mmsys.h |  4 +++
>   3 files changed, 52 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index abfe94a30248..e0cf13d09763 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -75,6 +75,14 @@
>   #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
>   #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
>   
> +/* VPPSYS1 */
> +#define MT8195_SVPP1_HW_DCM_1ST_DIS0				0x150
> +#define MT8195_SVPP1_HW_DCM_1ST_DIS1				0x160
> +#define MT8195_SVPP1_HW_DCM_2ND_DIS0				0x1a0
> +#define MT8195_SVPP1_HW_DCM_2ND_DIS1				0x1b0
> +#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH				0xf48
> +#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH				0xf74
> +
>   static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
>   	{
>   		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index c4d15f99f853..c98cfcb7db38 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -261,6 +261,46 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
>   }
>   EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
>   
> +void mtk_mmsys_merge_config(struct device *dev, u32 id, bool enable)

void mtk_mmsys_merge_config(struct device *dev, u32 svpp_id, bool enable)

or

void mtk_mmsys_vpp_merge_config(struct device *dev, u32 id, bool enable)

...adding that "svpp" or "vpp" word makes the function easier to understand :-)

> +{
> +	u32 reg;
> +
> +	switch (id) {
> +	case 2:
> +		reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH;
> +		break;
> +	case 3:
> +		reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH;
> +		break;
> +	default:
> +		dev_err(dev, "Invalid id %d\n", id);
> +		return;
> +	}
> +
> +	mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_merge_config);
> +
> +void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable)

...would be the same here, but only about the function name, so I'd go with
changing the name for both.

> +{
> +	u32 val = 0;
> +
> +	if (enable)
> +		val = BIT(25);

No magic bits please, add a definition for them

> +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> +			      MT8195_SVPP1_HW_DCM_1ST_DIS0, BIT(25), val);
> +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> +			      MT8195_SVPP1_HW_DCM_2ND_DIS0, BIT(25), val);
> +
> +	if (enable)
> +		val = (BIT(4) | BIT(5));

same here

> +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> +			      MT8195_SVPP1_HW_DCM_1ST_DIS1, (BIT(4) | BIT(5)), val);
> +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> +			      MT8195_SVPP1_HW_DCM_2ND_DIS1, (BIT(4) | BIT(5)), val);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_rsz_dcm_config);
> +
>   static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
>   				  bool assert)
>   {
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index d2b02bb43768..2d5c7fe920b0 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -67,4 +67,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>   
>   void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
>   
> +void mtk_mmsys_merge_config(struct device *dev, u32 id, bool enable);
> +
> +void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable);
> +
>   #endif /* __MTK_MMSYS_H */

Re: [PATCH v1 4/6] soc: mediatek: mmsys: add config api for RSZ switching and DCM

[AngeloGioacchino Del Regno]

Il 04/10/22 11:33, Moudy Ho ha scritto:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Due to MT8195 HW design, some RSZs have additional settings that
> need to be configured in MMSYS.
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>

Hello Moudy,

please remember that you have to add your Signed-off-by tag to all of the commits
that you're sending, even if you're not the author, otherwise they are not
acceptable.

> ---
>   drivers/soc/mediatek/mt8195-mmsys.h    |  8 ++++++
>   drivers/soc/mediatek/mtk-mmsys.c       | 40 ++++++++++++++++++++++++++
>   include/linux/soc/mediatek/mtk-mmsys.h |  4 +++
>   3 files changed, 52 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index abfe94a30248..e0cf13d09763 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -75,6 +75,14 @@
>   #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
>   #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
>   
> +/* VPPSYS1 */
> +#define MT8195_SVPP1_HW_DCM_1ST_DIS0				0x150
> +#define MT8195_SVPP1_HW_DCM_1ST_DIS1				0x160
> +#define MT8195_SVPP1_HW_DCM_2ND_DIS0				0x1a0
> +#define MT8195_SVPP1_HW_DCM_2ND_DIS1				0x1b0
> +#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH				0xf48
> +#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH				0xf74
> +
>   static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
>   	{
>   		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index c4d15f99f853..c98cfcb7db38 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -261,6 +261,46 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
>   }
>   EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
>   
> +void mtk_mmsys_merge_config(struct device *dev, u32 id, bool enable)

void mtk_mmsys_merge_config(struct device *dev, u32 svpp_id, bool enable)

or

void mtk_mmsys_vpp_merge_config(struct device *dev, u32 id, bool enable)

...adding that "svpp" or "vpp" word makes the function easier to understand :-)

> +{
> +	u32 reg;
> +
> +	switch (id) {
> +	case 2:
> +		reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH;
> +		break;
> +	case 3:
> +		reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH;
> +		break;
> +	default:
> +		dev_err(dev, "Invalid id %d\n", id);
> +		return;
> +	}
> +
> +	mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_merge_config);
> +
> +void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable)

...would be the same here, but only about the function name, so I'd go with
changing the name for both.

> +{
> +	u32 val = 0;
> +
> +	if (enable)
> +		val = BIT(25);

No magic bits please, add a definition for them

> +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> +			      MT8195_SVPP1_HW_DCM_1ST_DIS0, BIT(25), val);
> +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> +			      MT8195_SVPP1_HW_DCM_2ND_DIS0, BIT(25), val);
> +
> +	if (enable)
> +		val = (BIT(4) | BIT(5));

same here

> +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> +			      MT8195_SVPP1_HW_DCM_1ST_DIS1, (BIT(4) | BIT(5)), val);
> +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> +			      MT8195_SVPP1_HW_DCM_2ND_DIS1, (BIT(4) | BIT(5)), val);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_rsz_dcm_config);
> +
>   static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
>   				  bool assert)
>   {
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index d2b02bb43768..2d5c7fe920b0 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -67,4 +67,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>   
>   void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
>   
> +void mtk_mmsys_merge_config(struct device *dev, u32 id, bool enable);
> +
> +void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable);
> +
>   #endif /* __MTK_MMSYS_H */



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Re: [PATCH v1 4/6] soc: mediatek: mmsys: add config api for RSZ switching and DCM

[moudy ho]

On Tue, 2022-10-04 at 14:17 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/10/22 11:33, Moudy Ho ha scritto:
> > From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> > 
> > Due to MT8195 HW design, some RSZs have additional settings that
> > need to be configured in MMSYS.
> > 
> > Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> 
> Hello Moudy,
> 
> please remember that you have to add your Signed-off-by tag to all of
> the commits
> that you're sending, even if you're not the author, otherwise they
> are not
> acceptable.
> 

Hi Angelo,

Thanks for the reminder, I'll add the required tags and resend the
entire patch.

Regards,
Moudy
> > ---
> >   drivers/soc/mediatek/mt8195-mmsys.h    |  8 ++++++
> >   drivers/soc/mediatek/mtk-mmsys.c       | 40
> > ++++++++++++++++++++++++++
> >   include/linux/soc/mediatek/mtk-mmsys.h |  4 +++
> >   3 files changed, 52 insertions(+)
> > 
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index abfe94a30248..e0cf13d09763 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -75,6 +75,14 @@
> >   #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		
> > (2 << 16)
> >   #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			
> > (3 << 16)
> >   
> > +/* VPPSYS1 */
> > +#define MT8195_SVPP1_HW_DCM_1ST_DIS0				
> > 0x150
> > +#define MT8195_SVPP1_HW_DCM_1ST_DIS1				
> > 0x160
> > +#define MT8195_SVPP1_HW_DCM_2ND_DIS0				
> > 0x1a0
> > +#define MT8195_SVPP1_HW_DCM_2ND_DIS1				
> > 0x1b0
> > +#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH				
> > 0xf48
> > +#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH				
> > 0xf74
> > +
> >   static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> >   	{
> >   		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index c4d15f99f853..c98cfcb7db38 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -261,6 +261,46 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct
> > device *dev, u32 val)
> >   }
> >   EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
> >   
> > +void mtk_mmsys_merge_config(struct device *dev, u32 id, bool
> > enable)
> 
> void mtk_mmsys_merge_config(struct device *dev, u32 svpp_id, bool
> enable)
> 
> or
> 
> void mtk_mmsys_vpp_merge_config(struct device *dev, u32 id, bool
> enable)
> 
> ...adding that "svpp" or "vpp" word makes the function easier to
> understand :-)
> 
> > +{
> > +	u32 reg;
> > +
> > +	switch (id) {
> > +	case 2:
> > +		reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH;
> > +		break;
> > +	case 3:
> > +		reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH;
> > +		break;
> > +	default:
> > +		dev_err(dev, "Invalid id %d\n", id);
> > +		return;
> > +	}
> > +
> > +	mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_merge_config);
> > +
> > +void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable)
> 
> ...would be the same here, but only about the function name, so I'd
> go with
> changing the name for both.
> 
> > +{
> > +	u32 val = 0;
> > +
> > +	if (enable)
> > +		val = BIT(25);
> 
> No magic bits please, add a definition for them
> 
> > +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> > +			      MT8195_SVPP1_HW_DCM_1ST_DIS0, BIT(25),
> > val);
> > +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> > +			      MT8195_SVPP1_HW_DCM_2ND_DIS0, BIT(25),
> > val);
> > +
> > +	if (enable)
> > +		val = (BIT(4) | BIT(5));
> 
> same here
> 
> > +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> > +			      MT8195_SVPP1_HW_DCM_1ST_DIS1, (BIT(4) |
> > BIT(5)), val);
> > +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> > +			      MT8195_SVPP1_HW_DCM_2ND_DIS1, (BIT(4) |
> > BIT(5)), val);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_rsz_dcm_config);
> > +
> >   static int mtk_mmsys_reset_update(struct reset_controller_dev
> > *rcdev, unsigned long id,
> >   				  bool assert)
> >   {
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index d2b02bb43768..2d5c7fe920b0 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -67,4 +67,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> >   
> >   void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
> >   
> > +void mtk_mmsys_merge_config(struct device *dev, u32 id, bool
> > enable);
> > +
> > +void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable);
> > +
> >   #endif /* __MTK_MMSYS_H */
> 
> 

Re: [PATCH v1 4/6] soc: mediatek: mmsys: add config api for RSZ switching and DCM

[moudy ho]

On Tue, 2022-10-04 at 14:17 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/10/22 11:33, Moudy Ho ha scritto:
> > From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> > 
> > Due to MT8195 HW design, some RSZs have additional settings that
> > need to be configured in MMSYS.
> > 
> > Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> 
> Hello Moudy,
> 
> please remember that you have to add your Signed-off-by tag to all of
> the commits
> that you're sending, even if you're not the author, otherwise they
> are not
> acceptable.
> 

Hi Angelo,

Thanks for the reminder, I'll add the required tags and resend the
entire patch.

Regards,
Moudy
> > ---
> >   drivers/soc/mediatek/mt8195-mmsys.h    |  8 ++++++
> >   drivers/soc/mediatek/mtk-mmsys.c       | 40
> > ++++++++++++++++++++++++++
> >   include/linux/soc/mediatek/mtk-mmsys.h |  4 +++
> >   3 files changed, 52 insertions(+)
> > 
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index abfe94a30248..e0cf13d09763 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -75,6 +75,14 @@
> >   #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		
> > (2 << 16)
> >   #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			
> > (3 << 16)
> >   
> > +/* VPPSYS1 */
> > +#define MT8195_SVPP1_HW_DCM_1ST_DIS0				
> > 0x150
> > +#define MT8195_SVPP1_HW_DCM_1ST_DIS1				
> > 0x160
> > +#define MT8195_SVPP1_HW_DCM_2ND_DIS0				
> > 0x1a0
> > +#define MT8195_SVPP1_HW_DCM_2ND_DIS1				
> > 0x1b0
> > +#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH				
> > 0xf48
> > +#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH				
> > 0xf74
> > +
> >   static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> >   	{
> >   		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index c4d15f99f853..c98cfcb7db38 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -261,6 +261,46 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct
> > device *dev, u32 val)
> >   }
> >   EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
> >   
> > +void mtk_mmsys_merge_config(struct device *dev, u32 id, bool
> > enable)
> 
> void mtk_mmsys_merge_config(struct device *dev, u32 svpp_id, bool
> enable)
> 
> or
> 
> void mtk_mmsys_vpp_merge_config(struct device *dev, u32 id, bool
> enable)
> 
> ...adding that "svpp" or "vpp" word makes the function easier to
> understand :-)
> 
> > +{
> > +	u32 reg;
> > +
> > +	switch (id) {
> > +	case 2:
> > +		reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH;
> > +		break;
> > +	case 3:
> > +		reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH;
> > +		break;
> > +	default:
> > +		dev_err(dev, "Invalid id %d\n", id);
> > +		return;
> > +	}
> > +
> > +	mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_merge_config);
> > +
> > +void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable)
> 
> ...would be the same here, but only about the function name, so I'd
> go with
> changing the name for both.
> 
> > +{
> > +	u32 val = 0;
> > +
> > +	if (enable)
> > +		val = BIT(25);
> 
> No magic bits please, add a definition for them
> 
> > +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> > +			      MT8195_SVPP1_HW_DCM_1ST_DIS0, BIT(25),
> > val);
> > +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> > +			      MT8195_SVPP1_HW_DCM_2ND_DIS0, BIT(25),
> > val);
> > +
> > +	if (enable)
> > +		val = (BIT(4) | BIT(5));
> 
> same here
> 
> > +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> > +			      MT8195_SVPP1_HW_DCM_1ST_DIS1, (BIT(4) |
> > BIT(5)), val);
> > +	mtk_mmsys_update_bits(dev_get_drvdata(dev),
> > +			      MT8195_SVPP1_HW_DCM_2ND_DIS1, (BIT(4) |
> > BIT(5)), val);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_rsz_dcm_config);
> > +
> >   static int mtk_mmsys_reset_update(struct reset_controller_dev
> > *rcdev, unsigned long id,
> >   				  bool assert)
> >   {
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index d2b02bb43768..2d5c7fe920b0 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -67,4 +67,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> >   
> >   void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
> >   
> > +void mtk_mmsys_merge_config(struct device *dev, u32 id, bool
> > enable);
> > +
> > +void mtk_mmsys_rsz_dcm_config(struct device *dev, bool enable);
> > +
> >   #endif /* __MTK_MMSYS_H */
> 
> 


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[PATCH v1 5/6] soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Add mtk_mutex_set_mod support to set MOD1

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c1a33d52038e..5dcbd61fe42c 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -23,6 +23,7 @@
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
 #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n)	(mutex_mod_reg + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n)	((mutex_mod_reg) + 0x20 * (n) + 0x4)
 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n)	(mutex_sof_reg + 0x20 * (n))
 #define DISP_REG_MUTEX_MOD2(n)			(0x34 + 0x20 * (n))
 
@@ -750,14 +751,24 @@ int mtk_mutex_write_mod(struct mtk_mutex *mutex,
 		return -EINVAL;
 	}
 
-	offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
-				    mutex->id);
-	reg = readl_relaxed(mtx->regs + offset);
-
-	if (clear)
-		reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
-	else
-		reg |= BIT(mtx->data->mutex_table_mod[idx]);
+	if (mtx->data->mutex_table_mod[idx] < 32) {
+		offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
+					    mutex->id);
+		reg = readl_relaxed(mtx->regs + offset);
+		if (clear)
+			reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
+		else
+			reg |= BIT(mtx->data->mutex_table_mod[idx]);
+
+	} else {
+		offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
+					     mutex->id);
+		reg = readl_relaxed(mtx->regs + offset);
+		if (clear)
+			reg &= ~BIT(mtx->data->mutex_table_mod[idx] - 32);
+		else
+			reg |= BIT(mtx->data->mutex_table_mod[idx] - 32);
+	}
 
 	writel_relaxed(reg, mtx->regs + offset);
 
-- 
2.18.0

[PATCH v1 5/6] soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Add mtk_mutex_set_mod support to set MOD1

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c1a33d52038e..5dcbd61fe42c 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -23,6 +23,7 @@
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
 #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n)	(mutex_mod_reg + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n)	((mutex_mod_reg) + 0x20 * (n) + 0x4)
 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n)	(mutex_sof_reg + 0x20 * (n))
 #define DISP_REG_MUTEX_MOD2(n)			(0x34 + 0x20 * (n))
 
@@ -750,14 +751,24 @@ int mtk_mutex_write_mod(struct mtk_mutex *mutex,
 		return -EINVAL;
 	}
 
-	offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
-				    mutex->id);
-	reg = readl_relaxed(mtx->regs + offset);
-
-	if (clear)
-		reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
-	else
-		reg |= BIT(mtx->data->mutex_table_mod[idx]);
+	if (mtx->data->mutex_table_mod[idx] < 32) {
+		offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
+					    mutex->id);
+		reg = readl_relaxed(mtx->regs + offset);
+		if (clear)
+			reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
+		else
+			reg |= BIT(mtx->data->mutex_table_mod[idx]);
+
+	} else {
+		offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
+					     mutex->id);
+		reg = readl_relaxed(mtx->regs + offset);
+		if (clear)
+			reg &= ~BIT(mtx->data->mutex_table_mod[idx] - 32);
+		else
+			reg |= BIT(mtx->data->mutex_table_mod[idx] - 32);
+	}
 
 	writel_relaxed(reg, mtx->regs + offset);
 
-- 
2.18.0


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Re: [PATCH v1 5/6] soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1

[AngeloGioacchino Del Regno]

Il 04/10/22 11:33, Moudy Ho ha scritto:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Add mtk_mutex_set_mod support to set MOD1
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
>   drivers/soc/mediatek/mtk-mutex.c | 27 +++++++++++++++++++--------
>   1 file changed, 19 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index c1a33d52038e..5dcbd61fe42c 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -23,6 +23,7 @@
>   #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
>   #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
>   #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n)	(mutex_mod_reg + 0x20 * (n))
> +#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n)	((mutex_mod_reg) + 0x20 * (n) + 0x4)
>   #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n)	(mutex_sof_reg + 0x20 * (n))
>   #define DISP_REG_MUTEX_MOD2(n)			(0x34 + 0x20 * (n))
>   
> @@ -750,14 +751,24 @@ int mtk_mutex_write_mod(struct mtk_mutex *mutex,
>   		return -EINVAL;
>   	}
>   
> -	offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> -				    mutex->id);
> -	reg = readl_relaxed(mtx->regs + offset);
> -
> -	if (clear)
> -		reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
> -	else
> -		reg |= BIT(mtx->data->mutex_table_mod[idx]);
> +	if (mtx->data->mutex_table_mod[idx] < 32) {

What if we do...

	u8 id_offset = 0;

	/*
	 * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods
	 * are present, hence requiring multiple 32-bits registers.
	 *
	 * The mutex_table_mod fully represents that by defining the number of
	 * the mod sequentially, later used as a bit number, which can be more
	 * than 0..31.
	 *
	 * In order to retain compatibility with older SoCs, we perform R/W on
	 * the single 32 bits registers, but this requires us to translate the
	 * mutex ID bit accordingly.
	 */
	if (mtx->data->mutex_table_mod[idx] < 32) {
		reg_offset = DISP_REG_MUTEX_MOD0(mtx->data->mutex_mod_reg,
						 mutex->id);
	} else {
		reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
						 mutex->id);
		id_offset = 32;
	}

	reg = readl_relaxed(mtx->regs + offset);
	if (clear)
		reg &= ~BIT(mtx->data->mutex_table_mod[idx] - id_offset);
	else
		reg |= BIT(mtx->data->mutex_table_mod[idx] - id_offset);

	writel_relaxed(reg, mtx->regs + offset);

...like this, we give good documentation and also keep the code "short" :-)

Regards,
Angelo


> +		offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> +					    mutex->id);
> +		reg = readl_relaxed(mtx->regs + offset);
> +		if (clear)
> +			reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
> +		else
> +			reg |= BIT(mtx->data->mutex_table_mod[idx]);
> +
> +	} else {
> +		offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
> +					     mutex->id);
> +		reg = readl_relaxed(mtx->regs + offset);
> +		if (clear)
> +			reg &= ~BIT(mtx->data->mutex_table_mod[idx] - 32);
> +		else
> +			reg |= BIT(mtx->data->mutex_table_mod[idx] - 32);
> +	}
>   
>   	writel_relaxed(reg, mtx->regs + offset);
>   

Re: [PATCH v1 5/6] soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1

[AngeloGioacchino Del Regno]

Il 04/10/22 11:33, Moudy Ho ha scritto:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> 
> Add mtk_mutex_set_mod support to set MOD1
> 
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
>   drivers/soc/mediatek/mtk-mutex.c | 27 +++++++++++++++++++--------
>   1 file changed, 19 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index c1a33d52038e..5dcbd61fe42c 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -23,6 +23,7 @@
>   #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
>   #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
>   #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n)	(mutex_mod_reg + 0x20 * (n))
> +#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n)	((mutex_mod_reg) + 0x20 * (n) + 0x4)
>   #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n)	(mutex_sof_reg + 0x20 * (n))
>   #define DISP_REG_MUTEX_MOD2(n)			(0x34 + 0x20 * (n))
>   
> @@ -750,14 +751,24 @@ int mtk_mutex_write_mod(struct mtk_mutex *mutex,
>   		return -EINVAL;
>   	}
>   
> -	offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> -				    mutex->id);
> -	reg = readl_relaxed(mtx->regs + offset);
> -
> -	if (clear)
> -		reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
> -	else
> -		reg |= BIT(mtx->data->mutex_table_mod[idx]);
> +	if (mtx->data->mutex_table_mod[idx] < 32) {

What if we do...

	u8 id_offset = 0;

	/*
	 * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods
	 * are present, hence requiring multiple 32-bits registers.
	 *
	 * The mutex_table_mod fully represents that by defining the number of
	 * the mod sequentially, later used as a bit number, which can be more
	 * than 0..31.
	 *
	 * In order to retain compatibility with older SoCs, we perform R/W on
	 * the single 32 bits registers, but this requires us to translate the
	 * mutex ID bit accordingly.
	 */
	if (mtx->data->mutex_table_mod[idx] < 32) {
		reg_offset = DISP_REG_MUTEX_MOD0(mtx->data->mutex_mod_reg,
						 mutex->id);
	} else {
		reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
						 mutex->id);
		id_offset = 32;
	}

	reg = readl_relaxed(mtx->regs + offset);
	if (clear)
		reg &= ~BIT(mtx->data->mutex_table_mod[idx] - id_offset);
	else
		reg |= BIT(mtx->data->mutex_table_mod[idx] - id_offset);

	writel_relaxed(reg, mtx->regs + offset);

...like this, we give good documentation and also keep the code "short" :-)

Regards,
Angelo


> +		offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> +					    mutex->id);
> +		reg = readl_relaxed(mtx->regs + offset);
> +		if (clear)
> +			reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
> +		else
> +			reg |= BIT(mtx->data->mutex_table_mod[idx]);
> +
> +	} else {
> +		offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
> +					     mutex->id);
> +		reg = readl_relaxed(mtx->regs + offset);
> +		if (clear)
> +			reg &= ~BIT(mtx->data->mutex_table_mod[idx] - 32);
> +		else
> +			reg |= BIT(mtx->data->mutex_table_mod[idx] - 32);
> +	}
>   
>   	writel_relaxed(reg, mtx->regs + offset);
>   



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Re: [PATCH v1 5/6] soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1

[moudy ho]

On Tue, 2022-10-04 at 14:38 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/10/22 11:33, Moudy Ho ha scritto:
> > From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> > 
> > Add mtk_mutex_set_mod support to set MOD1
> > 
> > Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> > ---
> >   drivers/soc/mediatek/mtk-mutex.c | 27 +++++++++++++++++++--------
> >   1 file changed, 19 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index c1a33d52038e..5dcbd61fe42c 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -23,6 +23,7 @@
> >   #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
> >   #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 *
> > (n))
> >   #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n)	(mutex_mod_reg
> > + 0x20 * (n))
> > +#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n)	((mutex_mod_reg
> > ) + 0x20 * (n) + 0x4)
> >   #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n)	(mutex_sof_reg
> > + 0x20 * (n))
> >   #define DISP_REG_MUTEX_MOD2(n)			(0x34 + 0x20 *
> > (n))
> >   
> > @@ -750,14 +751,24 @@ int mtk_mutex_write_mod(struct mtk_mutex
> > *mutex,
> >   		return -EINVAL;
> >   	}
> >   
> > -	offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> > -				    mutex->id);
> > -	reg = readl_relaxed(mtx->regs + offset);
> > -
> > -	if (clear)
> > -		reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
> > -	else
> > -		reg |= BIT(mtx->data->mutex_table_mod[idx]);
> > +	if (mtx->data->mutex_table_mod[idx] < 32) {
> 
> What if we do...
> 
> 	u8 id_offset = 0;
> 
> 	/*
> 	 * Some SoCs may have multiple MUTEX_MOD registers as more than
> 32 mods
> 	 * are present, hence requiring multiple 32-bits registers.
> 	 *
> 	 * The mutex_table_mod fully represents that by defining the
> number of
> 	 * the mod sequentially, later used as a bit number, which can
> be more
> 	 * than 0..31.
> 	 *
> 	 * In order to retain compatibility with older SoCs, we perform
> R/W on
> 	 * the single 32 bits registers, but this requires us to
> translate the
> 	 * mutex ID bit accordingly.
> 	 */
> 	if (mtx->data->mutex_table_mod[idx] < 32) {
> 		reg_offset = DISP_REG_MUTEX_MOD0(mtx->data-
> >mutex_mod_reg,
> 						 mutex->id);
> 	} else {
> 		reg_offset = DISP_REG_MUTEX_MOD1(mtx->data-
> >mutex_mod_reg,
> 						 mutex->id);
> 		id_offset = 32;
> 	}
> 
> 	reg = readl_relaxed(mtx->regs + offset);
> 	if (clear)
> 		reg &= ~BIT(mtx->data->mutex_table_mod[idx] -
> id_offset);
> 	else
> 		reg |= BIT(mtx->data->mutex_table_mod[idx] -
> id_offset);
> 
> 	writel_relaxed(reg, mtx->regs + offset);
> 
> ...like this, we give good documentation and also keep the code
> "short" :-)
> 
> Regards,
> Angelo
> 
> 

Hi Angelo,

Thanks for helping with outstanding comments and cleaning up the code,
I'll follow this guide to improve accordingly.

Regards,
Moudy

> > +		offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> > +					    mutex->id);
> > +		reg = readl_relaxed(mtx->regs + offset);
> > +		if (clear)
> > +			reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
> > +		else
> > +			reg |= BIT(mtx->data->mutex_table_mod[idx]);
> > +
> > +	} else {
> > +		offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
> > +					     mutex->id);
> > +		reg = readl_relaxed(mtx->regs + offset);
> > +		if (clear)
> > +			reg &= ~BIT(mtx->data->mutex_table_mod[idx] -
> > 32);
> > +		else
> > +			reg |= BIT(mtx->data->mutex_table_mod[idx] -
> > 32);
> > +	}
> >   
> >   	writel_relaxed(reg, mtx->regs + offset);
> >   
> 
> 

Re: [PATCH v1 5/6] soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1

[moudy ho]

On Tue, 2022-10-04 at 14:38 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/10/22 11:33, Moudy Ho ha scritto:
> > From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
> > 
> > Add mtk_mutex_set_mod support to set MOD1
> > 
> > Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> > ---
> >   drivers/soc/mediatek/mtk-mutex.c | 27 +++++++++++++++++++--------
> >   1 file changed, 19 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index c1a33d52038e..5dcbd61fe42c 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -23,6 +23,7 @@
> >   #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
> >   #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 *
> > (n))
> >   #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n)	(mutex_mod_reg
> > + 0x20 * (n))
> > +#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n)	((mutex_mod_reg
> > ) + 0x20 * (n) + 0x4)
> >   #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n)	(mutex_sof_reg
> > + 0x20 * (n))
> >   #define DISP_REG_MUTEX_MOD2(n)			(0x34 + 0x20 *
> > (n))
> >   
> > @@ -750,14 +751,24 @@ int mtk_mutex_write_mod(struct mtk_mutex
> > *mutex,
> >   		return -EINVAL;
> >   	}
> >   
> > -	offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> > -				    mutex->id);
> > -	reg = readl_relaxed(mtx->regs + offset);
> > -
> > -	if (clear)
> > -		reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
> > -	else
> > -		reg |= BIT(mtx->data->mutex_table_mod[idx]);
> > +	if (mtx->data->mutex_table_mod[idx] < 32) {
> 
> What if we do...
> 
> 	u8 id_offset = 0;
> 
> 	/*
> 	 * Some SoCs may have multiple MUTEX_MOD registers as more than
> 32 mods
> 	 * are present, hence requiring multiple 32-bits registers.
> 	 *
> 	 * The mutex_table_mod fully represents that by defining the
> number of
> 	 * the mod sequentially, later used as a bit number, which can
> be more
> 	 * than 0..31.
> 	 *
> 	 * In order to retain compatibility with older SoCs, we perform
> R/W on
> 	 * the single 32 bits registers, but this requires us to
> translate the
> 	 * mutex ID bit accordingly.
> 	 */
> 	if (mtx->data->mutex_table_mod[idx] < 32) {
> 		reg_offset = DISP_REG_MUTEX_MOD0(mtx->data-
> >mutex_mod_reg,
> 						 mutex->id);
> 	} else {
> 		reg_offset = DISP_REG_MUTEX_MOD1(mtx->data-
> >mutex_mod_reg,
> 						 mutex->id);
> 		id_offset = 32;
> 	}
> 
> 	reg = readl_relaxed(mtx->regs + offset);
> 	if (clear)
> 		reg &= ~BIT(mtx->data->mutex_table_mod[idx] -
> id_offset);
> 	else
> 		reg |= BIT(mtx->data->mutex_table_mod[idx] -
> id_offset);
> 
> 	writel_relaxed(reg, mtx->regs + offset);
> 
> ...like this, we give good documentation and also keep the code
> "short" :-)
> 
> Regards,
> Angelo
> 
> 

Hi Angelo,

Thanks for helping with outstanding comments and cleaning up the code,
I'll follow this guide to improve accordingly.

Regards,
Moudy

> > +		offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> > +					    mutex->id);
> > +		reg = readl_relaxed(mtx->regs + offset);
> > +		if (clear)
> > +			reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
> > +		else
> > +			reg |= BIT(mtx->data->mutex_table_mod[idx]);
> > +
> > +	} else {
> > +		offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
> > +					     mutex->id);
> > +		reg = readl_relaxed(mtx->regs + offset);
> > +		if (clear)
> > +			reg &= ~BIT(mtx->data->mutex_table_mod[idx] -
> > 32);
> > +		else
> > +			reg |= BIT(mtx->data->mutex_table_mod[idx] -
> > 32);
> > +	}
> >   
> >   	writel_relaxed(reg, mtx->regs + offset);
> >   
> 
> 


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[PATCH v1 6/6] soc: mediatek: mutex: support MT8195 VPPSYS

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Add MT8195 VPPSYS0 and VPPSYS1 mutex info to driver data

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c       | 102 +++++++++++++++++++++++++
 include/linux/soc/mediatek/mtk-mutex.h |  36 +++++++++
 2 files changed, 138 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 5dcbd61fe42c..294ef61ed1cc 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -131,6 +131,53 @@
 #define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
 #define MT8195_MUTEX_MOD_DISP_PWM0		27
 
+/* VPPSYS0 */
+#define MT8195_MUTEX_MOD_MDP_RDMA0             0
+#define MT8195_MUTEX_MOD_MDP_FG0               1
+#define MT8195_MUTEX_MOD_MDP_STITCH0           2
+#define MT8195_MUTEX_MOD_MDP_HDR0              3
+#define MT8195_MUTEX_MOD_MDP_AAL0              4
+#define MT8195_MUTEX_MOD_MDP_RSZ0              5
+#define MT8195_MUTEX_MOD_MDP_TDSHP0            6
+#define MT8195_MUTEX_MOD_MDP_COLOR0            7
+#define MT8195_MUTEX_MOD_MDP_OVL0              8
+#define MT8195_MUTEX_MOD_MDP_PAD0              9
+#define MT8195_MUTEX_MOD_MDP_TCC0              10
+#define MT8195_MUTEX_MOD_MDP_WROT0             11
+
+/* VPPSYS1 */
+#define MT8195_MUTEX_MOD_MDP_TCC1              3
+#define MT8195_MUTEX_MOD_MDP_RDMA1             4
+#define MT8195_MUTEX_MOD_MDP_RDMA2             5
+#define MT8195_MUTEX_MOD_MDP_RDMA3             6
+#define MT8195_MUTEX_MOD_MDP_FG1               7
+#define MT8195_MUTEX_MOD_MDP_FG2               8
+#define MT8195_MUTEX_MOD_MDP_FG3               9
+#define MT8195_MUTEX_MOD_MDP_HDR1              10
+#define MT8195_MUTEX_MOD_MDP_HDR2              11
+#define MT8195_MUTEX_MOD_MDP_HDR3              12
+#define MT8195_MUTEX_MOD_MDP_AAL1              13
+#define MT8195_MUTEX_MOD_MDP_AAL2              14
+#define MT8195_MUTEX_MOD_MDP_AAL3              15
+#define MT8195_MUTEX_MOD_MDP_RSZ1              16
+#define MT8195_MUTEX_MOD_MDP_RSZ2              17
+#define MT8195_MUTEX_MOD_MDP_RSZ3              18
+#define MT8195_MUTEX_MOD_MDP_TDSHP1            19
+#define MT8195_MUTEX_MOD_MDP_TDSHP2            20
+#define MT8195_MUTEX_MOD_MDP_TDSHP3            21
+#define MT8195_MUTEX_MOD_MDP_MERGE2            22
+#define MT8195_MUTEX_MOD_MDP_MERGE3            23
+#define MT8195_MUTEX_MOD_MDP_COLOR1            24
+#define MT8195_MUTEX_MOD_MDP_COLOR2            25
+#define MT8195_MUTEX_MOD_MDP_COLOR3            26
+#define MT8195_MUTEX_MOD_MDP_OVL1              27
+#define MT8195_MUTEX_MOD_MDP_PAD1              28
+#define MT8195_MUTEX_MOD_MDP_PAD2              29
+#define MT8195_MUTEX_MOD_MDP_PAD3              30
+#define MT8195_MUTEX_MOD_MDP_WROT1             31
+#define MT8195_MUTEX_MOD_MDP_WROT2             32
+#define MT8195_MUTEX_MOD_MDP_WROT3             33
+
 #define MT8365_MUTEX_MOD_DISP_OVL0		7
 #define MT8365_MUTEX_MOD_DISP_OVL0_2L		8
 #define MT8365_MUTEX_MOD_DISP_RDMA0		9
@@ -375,6 +422,52 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
 };
 
+static const unsigned int mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
+	[MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0,
+	[MUTEX_MOD_IDX_MDP_RDMA1] = MT8195_MUTEX_MOD_MDP_RDMA1,
+	[MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2,
+	[MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3,
+	[MUTEX_MOD_IDX_MDP_STITCH0] = MT8195_MUTEX_MOD_MDP_STITCH0,
+	[MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0,
+	[MUTEX_MOD_IDX_MDP_FG1] = MT8195_MUTEX_MOD_MDP_FG1,
+	[MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2,
+	[MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3,
+	[MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0,
+	[MUTEX_MOD_IDX_MDP_HDR1] = MT8195_MUTEX_MOD_MDP_HDR1,
+	[MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2,
+	[MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3,
+	[MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0,
+	[MUTEX_MOD_IDX_MDP_AAL1] = MT8195_MUTEX_MOD_MDP_AAL1,
+	[MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2,
+	[MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3,
+	[MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0,
+	[MUTEX_MOD_IDX_MDP_RSZ1] = MT8195_MUTEX_MOD_MDP_RSZ1,
+	[MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2,
+	[MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3,
+	[MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2,
+	[MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3,
+	[MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0,
+	[MUTEX_MOD_IDX_MDP_TDSHP1] = MT8195_MUTEX_MOD_MDP_TDSHP1,
+	[MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2,
+	[MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3,
+	[MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0,
+	[MUTEX_MOD_IDX_MDP_COLOR1] = MT8195_MUTEX_MOD_MDP_COLOR1,
+	[MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2,
+	[MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3,
+	[MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0,
+	[MUTEX_MOD_IDX_MDP_OVL1] = MT8195_MUTEX_MOD_MDP_OVL1,
+	[MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0,
+	[MUTEX_MOD_IDX_MDP_PAD1] = MT8195_MUTEX_MOD_MDP_PAD1,
+	[MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2,
+	[MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3,
+	[MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0,
+	[MUTEX_MOD_IDX_MDP_TCC1] = MT8195_MUTEX_MOD_MDP_TCC1,
+	[MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0,
+	[MUTEX_MOD_IDX_MDP_WROT1] = MT8195_MUTEX_MOD_MDP_WROT1,
+	[MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2,
+	[MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3,
+};
+
 static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
 	[DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
@@ -520,6 +613,13 @@ static const struct mtk_mutex_data mt8195_mutex_driver_data = {
 	.mutex_sof_reg = MT8183_MUTEX0_SOF0,
 };
 
+static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = {
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+	.mutex_table_mod = mt8195_mutex_table_mod,
+};
+
 static const struct mtk_mutex_data mt8365_mutex_driver_data = {
 	.mutex_mod = mt8365_mutex_mod,
 	.mutex_sof = mt8183_mutex_sof,
@@ -869,6 +969,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8192_mutex_driver_data},
 	{ .compatible = "mediatek,mt8195-disp-mutex",
 	  .data = &mt8195_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-vpp-mutex",
+	  .data = &mt8195_vpp_mutex_driver_data},
 	{ .compatible = "mediatek,mt8365-disp-mutex",
 	  .data = &mt8365_mutex_driver_data},
 	{},
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index b335c2837cd8..d8fb92d0a9f8 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -22,6 +22,42 @@ enum mtk_mutex_mod_index {
 	MUTEX_MOD_IDX_MDP_CCORR0,
 	MUTEX_MOD_IDX_MDP_HDR0,
 	MUTEX_MOD_IDX_MDP_COLOR0,
+	MUTEX_MOD_IDX_MDP_RDMA1,
+	MUTEX_MOD_IDX_MDP_RDMA2,
+	MUTEX_MOD_IDX_MDP_RDMA3,
+	MUTEX_MOD_IDX_MDP_STITCH0,
+	MUTEX_MOD_IDX_MDP_FG0,
+	MUTEX_MOD_IDX_MDP_FG1,
+	MUTEX_MOD_IDX_MDP_FG2,
+	MUTEX_MOD_IDX_MDP_FG3,
+	MUTEX_MOD_IDX_MDP_HDR0,
+	MUTEX_MOD_IDX_MDP_HDR1,
+	MUTEX_MOD_IDX_MDP_HDR2,
+	MUTEX_MOD_IDX_MDP_HDR3,
+	MUTEX_MOD_IDX_MDP_AAL1,
+	MUTEX_MOD_IDX_MDP_AAL2,
+	MUTEX_MOD_IDX_MDP_AAL3,
+	MUTEX_MOD_IDX_MDP_RSZ2,
+	MUTEX_MOD_IDX_MDP_RSZ3,
+	MUTEX_MOD_IDX_MDP_MERGE2,
+	MUTEX_MOD_IDX_MDP_MERGE3,
+	MUTEX_MOD_IDX_MDP_TDSHP1,
+	MUTEX_MOD_IDX_MDP_TDSHP2,
+	MUTEX_MOD_IDX_MDP_TDSHP3,
+	MUTEX_MOD_IDX_MDP_COLOR1,
+	MUTEX_MOD_IDX_MDP_COLOR2,
+	MUTEX_MOD_IDX_MDP_COLOR3,
+	MUTEX_MOD_IDX_MDP_OVL0,
+	MUTEX_MOD_IDX_MDP_OVL1,
+	MUTEX_MOD_IDX_MDP_PAD0,
+	MUTEX_MOD_IDX_MDP_PAD1,
+	MUTEX_MOD_IDX_MDP_PAD2,
+	MUTEX_MOD_IDX_MDP_PAD3,
+	MUTEX_MOD_IDX_MDP_TCC0,
+	MUTEX_MOD_IDX_MDP_TCC1,
+	MUTEX_MOD_IDX_MDP_WROT1,
+	MUTEX_MOD_IDX_MDP_WROT2,
+	MUTEX_MOD_IDX_MDP_WROT3,
 
 	MUTEX_MOD_IDX_MAX		/* ALWAYS keep at the end */
 };
-- 
2.18.0

[PATCH v1 6/6] soc: mediatek: mutex: support MT8195 VPPSYS

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>

Add MT8195 VPPSYS0 and VPPSYS1 mutex info to driver data

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c       | 102 +++++++++++++++++++++++++
 include/linux/soc/mediatek/mtk-mutex.h |  36 +++++++++
 2 files changed, 138 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 5dcbd61fe42c..294ef61ed1cc 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -131,6 +131,53 @@
 #define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
 #define MT8195_MUTEX_MOD_DISP_PWM0		27
 
+/* VPPSYS0 */
+#define MT8195_MUTEX_MOD_MDP_RDMA0             0
+#define MT8195_MUTEX_MOD_MDP_FG0               1
+#define MT8195_MUTEX_MOD_MDP_STITCH0           2
+#define MT8195_MUTEX_MOD_MDP_HDR0              3
+#define MT8195_MUTEX_MOD_MDP_AAL0              4
+#define MT8195_MUTEX_MOD_MDP_RSZ0              5
+#define MT8195_MUTEX_MOD_MDP_TDSHP0            6
+#define MT8195_MUTEX_MOD_MDP_COLOR0            7
+#define MT8195_MUTEX_MOD_MDP_OVL0              8
+#define MT8195_MUTEX_MOD_MDP_PAD0              9
+#define MT8195_MUTEX_MOD_MDP_TCC0              10
+#define MT8195_MUTEX_MOD_MDP_WROT0             11
+
+/* VPPSYS1 */
+#define MT8195_MUTEX_MOD_MDP_TCC1              3
+#define MT8195_MUTEX_MOD_MDP_RDMA1             4
+#define MT8195_MUTEX_MOD_MDP_RDMA2             5
+#define MT8195_MUTEX_MOD_MDP_RDMA3             6
+#define MT8195_MUTEX_MOD_MDP_FG1               7
+#define MT8195_MUTEX_MOD_MDP_FG2               8
+#define MT8195_MUTEX_MOD_MDP_FG3               9
+#define MT8195_MUTEX_MOD_MDP_HDR1              10
+#define MT8195_MUTEX_MOD_MDP_HDR2              11
+#define MT8195_MUTEX_MOD_MDP_HDR3              12
+#define MT8195_MUTEX_MOD_MDP_AAL1              13
+#define MT8195_MUTEX_MOD_MDP_AAL2              14
+#define MT8195_MUTEX_MOD_MDP_AAL3              15
+#define MT8195_MUTEX_MOD_MDP_RSZ1              16
+#define MT8195_MUTEX_MOD_MDP_RSZ2              17
+#define MT8195_MUTEX_MOD_MDP_RSZ3              18
+#define MT8195_MUTEX_MOD_MDP_TDSHP1            19
+#define MT8195_MUTEX_MOD_MDP_TDSHP2            20
+#define MT8195_MUTEX_MOD_MDP_TDSHP3            21
+#define MT8195_MUTEX_MOD_MDP_MERGE2            22
+#define MT8195_MUTEX_MOD_MDP_MERGE3            23
+#define MT8195_MUTEX_MOD_MDP_COLOR1            24
+#define MT8195_MUTEX_MOD_MDP_COLOR2            25
+#define MT8195_MUTEX_MOD_MDP_COLOR3            26
+#define MT8195_MUTEX_MOD_MDP_OVL1              27
+#define MT8195_MUTEX_MOD_MDP_PAD1              28
+#define MT8195_MUTEX_MOD_MDP_PAD2              29
+#define MT8195_MUTEX_MOD_MDP_PAD3              30
+#define MT8195_MUTEX_MOD_MDP_WROT1             31
+#define MT8195_MUTEX_MOD_MDP_WROT2             32
+#define MT8195_MUTEX_MOD_MDP_WROT3             33
+
 #define MT8365_MUTEX_MOD_DISP_OVL0		7
 #define MT8365_MUTEX_MOD_DISP_OVL0_2L		8
 #define MT8365_MUTEX_MOD_DISP_RDMA0		9
@@ -375,6 +422,52 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
 };
 
+static const unsigned int mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
+	[MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0,
+	[MUTEX_MOD_IDX_MDP_RDMA1] = MT8195_MUTEX_MOD_MDP_RDMA1,
+	[MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2,
+	[MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3,
+	[MUTEX_MOD_IDX_MDP_STITCH0] = MT8195_MUTEX_MOD_MDP_STITCH0,
+	[MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0,
+	[MUTEX_MOD_IDX_MDP_FG1] = MT8195_MUTEX_MOD_MDP_FG1,
+	[MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2,
+	[MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3,
+	[MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0,
+	[MUTEX_MOD_IDX_MDP_HDR1] = MT8195_MUTEX_MOD_MDP_HDR1,
+	[MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2,
+	[MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3,
+	[MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0,
+	[MUTEX_MOD_IDX_MDP_AAL1] = MT8195_MUTEX_MOD_MDP_AAL1,
+	[MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2,
+	[MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3,
+	[MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0,
+	[MUTEX_MOD_IDX_MDP_RSZ1] = MT8195_MUTEX_MOD_MDP_RSZ1,
+	[MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2,
+	[MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3,
+	[MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2,
+	[MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3,
+	[MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0,
+	[MUTEX_MOD_IDX_MDP_TDSHP1] = MT8195_MUTEX_MOD_MDP_TDSHP1,
+	[MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2,
+	[MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3,
+	[MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0,
+	[MUTEX_MOD_IDX_MDP_COLOR1] = MT8195_MUTEX_MOD_MDP_COLOR1,
+	[MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2,
+	[MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3,
+	[MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0,
+	[MUTEX_MOD_IDX_MDP_OVL1] = MT8195_MUTEX_MOD_MDP_OVL1,
+	[MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0,
+	[MUTEX_MOD_IDX_MDP_PAD1] = MT8195_MUTEX_MOD_MDP_PAD1,
+	[MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2,
+	[MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3,
+	[MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0,
+	[MUTEX_MOD_IDX_MDP_TCC1] = MT8195_MUTEX_MOD_MDP_TCC1,
+	[MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0,
+	[MUTEX_MOD_IDX_MDP_WROT1] = MT8195_MUTEX_MOD_MDP_WROT1,
+	[MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2,
+	[MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3,
+};
+
 static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
 	[DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
@@ -520,6 +613,13 @@ static const struct mtk_mutex_data mt8195_mutex_driver_data = {
 	.mutex_sof_reg = MT8183_MUTEX0_SOF0,
 };
 
+static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = {
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+	.mutex_table_mod = mt8195_mutex_table_mod,
+};
+
 static const struct mtk_mutex_data mt8365_mutex_driver_data = {
 	.mutex_mod = mt8365_mutex_mod,
 	.mutex_sof = mt8183_mutex_sof,
@@ -869,6 +969,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8192_mutex_driver_data},
 	{ .compatible = "mediatek,mt8195-disp-mutex",
 	  .data = &mt8195_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-vpp-mutex",
+	  .data = &mt8195_vpp_mutex_driver_data},
 	{ .compatible = "mediatek,mt8365-disp-mutex",
 	  .data = &mt8365_mutex_driver_data},
 	{},
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index b335c2837cd8..d8fb92d0a9f8 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -22,6 +22,42 @@ enum mtk_mutex_mod_index {
 	MUTEX_MOD_IDX_MDP_CCORR0,
 	MUTEX_MOD_IDX_MDP_HDR0,
 	MUTEX_MOD_IDX_MDP_COLOR0,
+	MUTEX_MOD_IDX_MDP_RDMA1,
+	MUTEX_MOD_IDX_MDP_RDMA2,
+	MUTEX_MOD_IDX_MDP_RDMA3,
+	MUTEX_MOD_IDX_MDP_STITCH0,
+	MUTEX_MOD_IDX_MDP_FG0,
+	MUTEX_MOD_IDX_MDP_FG1,
+	MUTEX_MOD_IDX_MDP_FG2,
+	MUTEX_MOD_IDX_MDP_FG3,
+	MUTEX_MOD_IDX_MDP_HDR0,
+	MUTEX_MOD_IDX_MDP_HDR1,
+	MUTEX_MOD_IDX_MDP_HDR2,
+	MUTEX_MOD_IDX_MDP_HDR3,
+	MUTEX_MOD_IDX_MDP_AAL1,
+	MUTEX_MOD_IDX_MDP_AAL2,
+	MUTEX_MOD_IDX_MDP_AAL3,
+	MUTEX_MOD_IDX_MDP_RSZ2,
+	MUTEX_MOD_IDX_MDP_RSZ3,
+	MUTEX_MOD_IDX_MDP_MERGE2,
+	MUTEX_MOD_IDX_MDP_MERGE3,
+	MUTEX_MOD_IDX_MDP_TDSHP1,
+	MUTEX_MOD_IDX_MDP_TDSHP2,
+	MUTEX_MOD_IDX_MDP_TDSHP3,
+	MUTEX_MOD_IDX_MDP_COLOR1,
+	MUTEX_MOD_IDX_MDP_COLOR2,
+	MUTEX_MOD_IDX_MDP_COLOR3,
+	MUTEX_MOD_IDX_MDP_OVL0,
+	MUTEX_MOD_IDX_MDP_OVL1,
+	MUTEX_MOD_IDX_MDP_PAD0,
+	MUTEX_MOD_IDX_MDP_PAD1,
+	MUTEX_MOD_IDX_MDP_PAD2,
+	MUTEX_MOD_IDX_MDP_PAD3,
+	MUTEX_MOD_IDX_MDP_TCC0,
+	MUTEX_MOD_IDX_MDP_TCC1,
+	MUTEX_MOD_IDX_MDP_WROT1,
+	MUTEX_MOD_IDX_MDP_WROT2,
+	MUTEX_MOD_IDX_MDP_WROT3,
 
 	MUTEX_MOD_IDX_MAX		/* ALWAYS keep at the end */
 };
-- 
2.18.0


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