From: Bjorn Helgaas <helgaas@kernel.org> To: daire.mcnamara@microchip.com Cc: conor.dooley@microchip.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v1 5/9] PCI: microchip: Gather MSI information from hardware config registers Date: Wed, 16 Nov 2022 10:41:35 -0600 [thread overview] Message-ID: <20221116164135.GA1117054@bhelgaas> (raw) In-Reply-To: <20221116135504.258687-6-daire.mcnamara@microchip.com> On Wed, Nov 16, 2022 at 01:55:00PM +0000, daire.mcnamara@microchip.com wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > The PCIe root complex on PolarFire SoC is configured at bitstream creation > time using Libero. Key MSI-related parameters include the number of > MSIs (1/2/4/8/16/32) and the MSI address. In the device driver, extract > this information from hw registers at init time, and use it to configure > MSI system, including configuring MSI capability structure correctly in > configuration space. Minor nits for v2. > + /* fixup msi enable flag */ s/msi/MSI/ here and comments below to match other usage. > + reg = readw_relaxed(ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); > + reg |= PCI_MSI_FLAGS_ENABLE; > + writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); > + > + /* fixup msi queue flags */ > + queue_size = reg & PCI_MSI_FLAGS_QMASK; > + queue_size >>= 1; > + reg &= ~PCI_MSI_FLAGS_QSIZE; > + reg |= queue_size << 4; > + writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); > + > + /* fixup msi addr fields */ > + /* allow enabling msi by disabling msi-x */ s/msi-x/MSI-X/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org> To: daire.mcnamara@microchip.com Cc: conor.dooley@microchip.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v1 5/9] PCI: microchip: Gather MSI information from hardware config registers Date: Wed, 16 Nov 2022 10:41:35 -0600 [thread overview] Message-ID: <20221116164135.GA1117054@bhelgaas> (raw) In-Reply-To: <20221116135504.258687-6-daire.mcnamara@microchip.com> On Wed, Nov 16, 2022 at 01:55:00PM +0000, daire.mcnamara@microchip.com wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > The PCIe root complex on PolarFire SoC is configured at bitstream creation > time using Libero. Key MSI-related parameters include the number of > MSIs (1/2/4/8/16/32) and the MSI address. In the device driver, extract > this information from hw registers at init time, and use it to configure > MSI system, including configuring MSI capability structure correctly in > configuration space. Minor nits for v2. > + /* fixup msi enable flag */ s/msi/MSI/ here and comments below to match other usage. > + reg = readw_relaxed(ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); > + reg |= PCI_MSI_FLAGS_ENABLE; > + writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); > + > + /* fixup msi queue flags */ > + queue_size = reg & PCI_MSI_FLAGS_QMASK; > + queue_size >>= 1; > + reg &= ~PCI_MSI_FLAGS_QSIZE; > + reg |= queue_size << 4; > + writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); > + > + /* fixup msi addr fields */ > + /* allow enabling msi by disabling msi-x */ s/msi-x/MSI-X/
next prev parent reply other threads:[~2022-11-16 16:41 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-16 13:54 [PATCH v1 0/9] PCI: microchip: Partition address translations daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-16 13:54 ` [PATCH v1 1/9] PCI: microchip: Align register, offset, and mask names with hw docs daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-23 21:09 ` Conor Dooley 2022-11-23 21:09 ` Conor Dooley 2022-11-16 13:54 ` [PATCH v1 2/9] PCI: microchip: Correct the DED and SEC interrupt bit offsets daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-16 15:19 ` Conor Dooley 2022-11-16 15:19 ` Conor Dooley 2022-11-23 21:28 ` Conor Dooley 2022-11-23 21:28 ` Conor Dooley 2022-11-16 13:54 ` [PATCH v1 3/9] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-23 21:34 ` Conor Dooley 2022-11-23 21:34 ` Conor Dooley 2022-11-16 13:54 ` [PATCH v1 4/9] PCI: microchip: Clean up initialisation of interrupts daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-16 15:17 ` kernel test robot 2022-11-16 15:17 ` kernel test robot 2022-11-17 18:28 ` kernel test robot 2022-11-17 18:28 ` kernel test robot 2022-11-23 21:58 ` Conor Dooley 2022-11-23 21:58 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 5/9] PCI: microchip: Gather MSI information from hardware config registers daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-16 16:41 ` Bjorn Helgaas [this message] 2022-11-16 16:41 ` Bjorn Helgaas 2022-11-23 22:09 ` Conor Dooley 2022-11-23 22:09 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 6/9] PCI: microchip: Re-partition code between probe() and init() daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-23 22:39 ` Conor Dooley 2022-11-23 22:39 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 7/9] PCI: microchip: Partition outbound address translation daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-23 22:44 ` Conor Dooley 2022-11-23 22:44 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 8/9] PCI: microchip: Partition inbound " daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-16 16:49 ` Bjorn Helgaas 2022-11-16 16:49 ` Bjorn Helgaas 2022-11-16 17:01 ` Conor Dooley 2022-11-16 17:01 ` Conor Dooley 2022-11-16 20:10 ` kernel test robot 2022-11-16 20:10 ` kernel test robot 2022-11-17 6:06 ` kernel test robot 2022-11-17 6:06 ` kernel test robot 2022-11-23 23:05 ` Conor Dooley 2022-11-23 23:05 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 9/9] riscv: dts: microchip: add parent ranges and dma-ranges for IKRD v2022.09 daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-23 22:14 ` Conor Dooley 2022-11-23 22:14 ` Conor Dooley 2022-11-23 23:15 ` [PATCH v1 0/9] PCI: microchip: Partition address translations Conor Dooley 2022-11-23 23:15 ` Conor Dooley
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