From: Conor Dooley <conor@kernel.org> To: daire.mcnamara@microchip.com Cc: conor.dooley@microchip.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v1 3/9] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs Date: Wed, 23 Nov 2022 21:34:10 +0000 [thread overview] Message-ID: <Y36R0jXXx6AwrLub@spud> (raw) In-Reply-To: <20221116135504.258687-4-daire.mcnamara@microchip.com> Hey Daire, On Wed, Nov 16, 2022 at 01:54:58PM +0000, daire.mcnamara@microchip.com wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > Minor re-organisation so that event handlers can access both a pointer > to the bridge area of the PCIe rootport and the ctrl area of the PCIe > rootport. Perhaps explaining why we would want to access both, when we've not needed to so far, would be helpful so that this commit message will make sense in isolation would be nice. The mechanics of the change seem good to me though: Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/pci/controller/pcie-microchip-host.c | 31 ++++++++++---------- > 1 file changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c > index 30153fd1a2b3..a81e6d25e347 100644 > --- a/drivers/pci/controller/pcie-microchip-host.c > +++ b/drivers/pci/controller/pcie-microchip-host.c > @@ -654,9 +654,10 @@ static inline u32 reg_to_event(u32 reg, struct event_map field) > return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; > } > > -static u32 pcie_events(void __iomem *addr) > +static u32 pcie_events(struct mc_pcie *port) > { > - u32 reg = readl_relaxed(addr); > + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; > + u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT); > u32 val = 0; > int i; > > @@ -666,9 +667,10 @@ static u32 pcie_events(void __iomem *addr) > return val; > } > > -static u32 sec_errors(void __iomem *addr) > +static u32 sec_errors(struct mc_pcie *port) > { > - u32 reg = readl_relaxed(addr); > + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; > + u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT); > u32 val = 0; > int i; > > @@ -678,9 +680,10 @@ static u32 sec_errors(void __iomem *addr) > return val; > } > > -static u32 ded_errors(void __iomem *addr) > +static u32 ded_errors(struct mc_pcie *port) > { > - u32 reg = readl_relaxed(addr); > + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; > + u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT); > u32 val = 0; > int i; > > @@ -690,9 +693,10 @@ static u32 ded_errors(void __iomem *addr) > return val; > } > > -static u32 local_events(void __iomem *addr) > +static u32 local_events(struct mc_pcie *port) > { > - u32 reg = readl_relaxed(addr); > + void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; > + u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); > u32 val = 0; > int i; > > @@ -704,15 +708,12 @@ static u32 local_events(void __iomem *addr) > > static u32 get_events(struct mc_pcie *port) > { > - void __iomem *bridge_base_addr = > - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; > - void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; > u32 events = 0; > > - events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT); > - events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT); > - events |= ded_errors(ctrl_base_addr + DED_ERROR_INT); > - events |= local_events(bridge_base_addr + ISTATUS_LOCAL); > + events |= pcie_events(port); > + events |= sec_errors(port); > + events |= ded_errors(port); > + events |= local_events(port); > > return events; > } > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org> To: daire.mcnamara@microchip.com Cc: conor.dooley@microchip.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v1 3/9] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs Date: Wed, 23 Nov 2022 21:34:10 +0000 [thread overview] Message-ID: <Y36R0jXXx6AwrLub@spud> (raw) In-Reply-To: <20221116135504.258687-4-daire.mcnamara@microchip.com> Hey Daire, On Wed, Nov 16, 2022 at 01:54:58PM +0000, daire.mcnamara@microchip.com wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > Minor re-organisation so that event handlers can access both a pointer > to the bridge area of the PCIe rootport and the ctrl area of the PCIe > rootport. Perhaps explaining why we would want to access both, when we've not needed to so far, would be helpful so that this commit message will make sense in isolation would be nice. The mechanics of the change seem good to me though: Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/pci/controller/pcie-microchip-host.c | 31 ++++++++++---------- > 1 file changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c > index 30153fd1a2b3..a81e6d25e347 100644 > --- a/drivers/pci/controller/pcie-microchip-host.c > +++ b/drivers/pci/controller/pcie-microchip-host.c > @@ -654,9 +654,10 @@ static inline u32 reg_to_event(u32 reg, struct event_map field) > return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; > } > > -static u32 pcie_events(void __iomem *addr) > +static u32 pcie_events(struct mc_pcie *port) > { > - u32 reg = readl_relaxed(addr); > + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; > + u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT); > u32 val = 0; > int i; > > @@ -666,9 +667,10 @@ static u32 pcie_events(void __iomem *addr) > return val; > } > > -static u32 sec_errors(void __iomem *addr) > +static u32 sec_errors(struct mc_pcie *port) > { > - u32 reg = readl_relaxed(addr); > + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; > + u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT); > u32 val = 0; > int i; > > @@ -678,9 +680,10 @@ static u32 sec_errors(void __iomem *addr) > return val; > } > > -static u32 ded_errors(void __iomem *addr) > +static u32 ded_errors(struct mc_pcie *port) > { > - u32 reg = readl_relaxed(addr); > + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; > + u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT); > u32 val = 0; > int i; > > @@ -690,9 +693,10 @@ static u32 ded_errors(void __iomem *addr) > return val; > } > > -static u32 local_events(void __iomem *addr) > +static u32 local_events(struct mc_pcie *port) > { > - u32 reg = readl_relaxed(addr); > + void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; > + u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); > u32 val = 0; > int i; > > @@ -704,15 +708,12 @@ static u32 local_events(void __iomem *addr) > > static u32 get_events(struct mc_pcie *port) > { > - void __iomem *bridge_base_addr = > - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; > - void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; > u32 events = 0; > > - events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT); > - events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT); > - events |= ded_errors(ctrl_base_addr + DED_ERROR_INT); > - events |= local_events(bridge_base_addr + ISTATUS_LOCAL); > + events |= pcie_events(port); > + events |= sec_errors(port); > + events |= ded_errors(port); > + events |= local_events(port); > > return events; > } > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-23 21:34 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-16 13:54 [PATCH v1 0/9] PCI: microchip: Partition address translations daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-16 13:54 ` [PATCH v1 1/9] PCI: microchip: Align register, offset, and mask names with hw docs daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-23 21:09 ` Conor Dooley 2022-11-23 21:09 ` Conor Dooley 2022-11-16 13:54 ` [PATCH v1 2/9] PCI: microchip: Correct the DED and SEC interrupt bit offsets daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-16 15:19 ` Conor Dooley 2022-11-16 15:19 ` Conor Dooley 2022-11-23 21:28 ` Conor Dooley 2022-11-23 21:28 ` Conor Dooley 2022-11-16 13:54 ` [PATCH v1 3/9] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-23 21:34 ` Conor Dooley [this message] 2022-11-23 21:34 ` Conor Dooley 2022-11-16 13:54 ` [PATCH v1 4/9] PCI: microchip: Clean up initialisation of interrupts daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-16 15:17 ` kernel test robot 2022-11-16 15:17 ` kernel test robot 2022-11-17 18:28 ` kernel test robot 2022-11-17 18:28 ` kernel test robot 2022-11-23 21:58 ` Conor Dooley 2022-11-23 21:58 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 5/9] PCI: microchip: Gather MSI information from hardware config registers daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-16 16:41 ` Bjorn Helgaas 2022-11-16 16:41 ` Bjorn Helgaas 2022-11-23 22:09 ` Conor Dooley 2022-11-23 22:09 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 6/9] PCI: microchip: Re-partition code between probe() and init() daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-23 22:39 ` Conor Dooley 2022-11-23 22:39 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 7/9] PCI: microchip: Partition outbound address translation daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-23 22:44 ` Conor Dooley 2022-11-23 22:44 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 8/9] PCI: microchip: Partition inbound " daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-16 16:49 ` Bjorn Helgaas 2022-11-16 16:49 ` Bjorn Helgaas 2022-11-16 17:01 ` Conor Dooley 2022-11-16 17:01 ` Conor Dooley 2022-11-16 20:10 ` kernel test robot 2022-11-16 20:10 ` kernel test robot 2022-11-17 6:06 ` kernel test robot 2022-11-17 6:06 ` kernel test robot 2022-11-23 23:05 ` Conor Dooley 2022-11-23 23:05 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 9/9] riscv: dts: microchip: add parent ranges and dma-ranges for IKRD v2022.09 daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-23 22:14 ` Conor Dooley 2022-11-23 22:14 ` Conor Dooley 2022-11-23 23:15 ` [PATCH v1 0/9] PCI: microchip: Partition address translations Conor Dooley 2022-11-23 23:15 ` Conor Dooley
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=Y36R0jXXx6AwrLub@spud \ --to=conor@kernel.org \ --cc=aou@eecs.berkeley.edu \ --cc=bhelgaas@google.com \ --cc=conor.dooley@microchip.com \ --cc=daire.mcnamara@microchip.com \ --cc=devicetree@vger.kernel.org \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=kw@linux.com \ --cc=linux-pci@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=lpieralisi@kernel.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=robh+dt@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.