From: Conor Dooley <conor@kernel.org> To: daire.mcnamara@microchip.com Cc: conor.dooley@microchip.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v1 6/9] PCI: microchip: Re-partition code between probe() and init() Date: Wed, 23 Nov 2022 22:39:46 +0000 [thread overview] Message-ID: <Y36hMtARoGy2YULP@spud> (raw) In-Reply-To: <20221116135504.258687-7-daire.mcnamara@microchip.com> On Wed, Nov 16, 2022 at 01:55:01PM +0000, daire.mcnamara@microchip.com wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > Continuing to use pci_host_common_probe() for the PCIe root complex on > PolarFire SoC was leading to an extremely large _init() function and > some unnatural code flow. Re-partition so some tasks are done in > a _probe() routine, which calls pci_host_common_probe() and then use a > much smaller _init() function, mainly to enable interrupts after address > translation tables are set up. > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/pci/controller/pcie-microchip-host.c | 55 ++++++++++++++------ > 1 file changed, 38 insertions(+), 17 deletions(-) > > diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c > index faecf419ad6f..73856647f321 100644 > --- a/drivers/pci/controller/pcie-microchip-host.c > +++ b/drivers/pci/controller/pcie-microchip-host.c > @@ -381,6 +381,8 @@ static struct { > > static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" }; > > +static struct mc_pcie *port; > + > static void mc_pcie_fixup_ecam(struct mc_pcie *port, void __iomem *ecam) > { > struct mc_msi *msi = &port->msi; > @@ -1095,7 +1097,34 @@ static int mc_platform_init(struct pci_config_window *cfg) > { > struct device *dev = cfg->parent; > struct platform_device *pdev = to_platform_device(dev); > - struct mc_pcie *port; > + void __iomem *bridge_base_addr = > + port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; > + int ret; > + > + /* Configure address translation table 0 for PCIe config space */ > + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, > + cfg->res.start, > + resource_size(&cfg->res)); > + > + /* Need some fixups in config space */ > + mc_pcie_fixup_ecam(port, cfg->win); > + > + /* Configure non-config space outbound ranges */ > + ret = mc_pcie_setup_windows(pdev, port); > + if (ret) > + return ret; > + > + /* address translation is up; safe to enable interrupts */ I think that Bjorn mentioned it elsewhere, but consistent capitalisation would be nice. Otherwise, code movement looks good to me. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > + ret = mc_init_interrupts(pdev, port); > + if (ret) > + return ret; > + > + return 0; > +} > + > +static int mc_host_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > void __iomem *bridge_base_addr; > void __iomem *ctrl_base_addr; > int ret; > @@ -1104,13 +1133,8 @@ static int mc_platform_init(struct pci_config_window *cfg) > port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); > if (!port) > return -ENOMEM; > - port->dev = dev; > > - ret = mc_pcie_init_clks(dev); > - if (ret) { > - dev_err(dev, "failed to get clock resources, error %d\n", ret); > - return -ENODEV; > - } > + port->dev = dev; > > port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); > if (IS_ERR(port->axi_base_addr)) > @@ -1136,16 +1160,13 @@ static int mc_platform_init(struct pci_config_window *cfg) > /* pick vector address from design */ > port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); > > - /* Configure Address Translation Table 0 for PCIe config space */ > - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, > - cfg->res.start, resource_size(&cfg->res)); > - > - ret = mc_pcie_setup_windows(pdev, port); > - if (ret) > - return ret; > + ret = mc_pcie_init_clks(dev); > + if (ret) { > + dev_err(dev, "failed to get clock resources, error %d\n", ret); > + return -ENODEV; > + } > > - /* address translation is up; safe to enable interrupts */ > - return mc_init_interrupts(pdev, port); > + return pci_host_common_probe(pdev); > } > > static const struct pci_ecam_ops mc_ecam_ops = { > @@ -1168,7 +1189,7 @@ static const struct of_device_id mc_pcie_of_match[] = { > MODULE_DEVICE_TABLE(of, mc_pcie_of_match); > > static struct platform_driver mc_pcie_driver = { > - .probe = pci_host_common_probe, > + .probe = mc_host_probe, > .driver = { > .name = "microchip-pcie", > .of_match_table = mc_pcie_of_match, > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org> To: daire.mcnamara@microchip.com Cc: conor.dooley@microchip.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v1 6/9] PCI: microchip: Re-partition code between probe() and init() Date: Wed, 23 Nov 2022 22:39:46 +0000 [thread overview] Message-ID: <Y36hMtARoGy2YULP@spud> (raw) In-Reply-To: <20221116135504.258687-7-daire.mcnamara@microchip.com> On Wed, Nov 16, 2022 at 01:55:01PM +0000, daire.mcnamara@microchip.com wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > Continuing to use pci_host_common_probe() for the PCIe root complex on > PolarFire SoC was leading to an extremely large _init() function and > some unnatural code flow. Re-partition so some tasks are done in > a _probe() routine, which calls pci_host_common_probe() and then use a > much smaller _init() function, mainly to enable interrupts after address > translation tables are set up. > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/pci/controller/pcie-microchip-host.c | 55 ++++++++++++++------ > 1 file changed, 38 insertions(+), 17 deletions(-) > > diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c > index faecf419ad6f..73856647f321 100644 > --- a/drivers/pci/controller/pcie-microchip-host.c > +++ b/drivers/pci/controller/pcie-microchip-host.c > @@ -381,6 +381,8 @@ static struct { > > static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" }; > > +static struct mc_pcie *port; > + > static void mc_pcie_fixup_ecam(struct mc_pcie *port, void __iomem *ecam) > { > struct mc_msi *msi = &port->msi; > @@ -1095,7 +1097,34 @@ static int mc_platform_init(struct pci_config_window *cfg) > { > struct device *dev = cfg->parent; > struct platform_device *pdev = to_platform_device(dev); > - struct mc_pcie *port; > + void __iomem *bridge_base_addr = > + port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; > + int ret; > + > + /* Configure address translation table 0 for PCIe config space */ > + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, > + cfg->res.start, > + resource_size(&cfg->res)); > + > + /* Need some fixups in config space */ > + mc_pcie_fixup_ecam(port, cfg->win); > + > + /* Configure non-config space outbound ranges */ > + ret = mc_pcie_setup_windows(pdev, port); > + if (ret) > + return ret; > + > + /* address translation is up; safe to enable interrupts */ I think that Bjorn mentioned it elsewhere, but consistent capitalisation would be nice. Otherwise, code movement looks good to me. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > + ret = mc_init_interrupts(pdev, port); > + if (ret) > + return ret; > + > + return 0; > +} > + > +static int mc_host_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > void __iomem *bridge_base_addr; > void __iomem *ctrl_base_addr; > int ret; > @@ -1104,13 +1133,8 @@ static int mc_platform_init(struct pci_config_window *cfg) > port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); > if (!port) > return -ENOMEM; > - port->dev = dev; > > - ret = mc_pcie_init_clks(dev); > - if (ret) { > - dev_err(dev, "failed to get clock resources, error %d\n", ret); > - return -ENODEV; > - } > + port->dev = dev; > > port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); > if (IS_ERR(port->axi_base_addr)) > @@ -1136,16 +1160,13 @@ static int mc_platform_init(struct pci_config_window *cfg) > /* pick vector address from design */ > port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); > > - /* Configure Address Translation Table 0 for PCIe config space */ > - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, > - cfg->res.start, resource_size(&cfg->res)); > - > - ret = mc_pcie_setup_windows(pdev, port); > - if (ret) > - return ret; > + ret = mc_pcie_init_clks(dev); > + if (ret) { > + dev_err(dev, "failed to get clock resources, error %d\n", ret); > + return -ENODEV; > + } > > - /* address translation is up; safe to enable interrupts */ > - return mc_init_interrupts(pdev, port); > + return pci_host_common_probe(pdev); > } > > static const struct pci_ecam_ops mc_ecam_ops = { > @@ -1168,7 +1189,7 @@ static const struct of_device_id mc_pcie_of_match[] = { > MODULE_DEVICE_TABLE(of, mc_pcie_of_match); > > static struct platform_driver mc_pcie_driver = { > - .probe = pci_host_common_probe, > + .probe = mc_host_probe, > .driver = { > .name = "microchip-pcie", > .of_match_table = mc_pcie_of_match, > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-23 22:39 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-16 13:54 [PATCH v1 0/9] PCI: microchip: Partition address translations daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-16 13:54 ` [PATCH v1 1/9] PCI: microchip: Align register, offset, and mask names with hw docs daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-23 21:09 ` Conor Dooley 2022-11-23 21:09 ` Conor Dooley 2022-11-16 13:54 ` [PATCH v1 2/9] PCI: microchip: Correct the DED and SEC interrupt bit offsets daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-16 15:19 ` Conor Dooley 2022-11-16 15:19 ` Conor Dooley 2022-11-23 21:28 ` Conor Dooley 2022-11-23 21:28 ` Conor Dooley 2022-11-16 13:54 ` [PATCH v1 3/9] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-23 21:34 ` Conor Dooley 2022-11-23 21:34 ` Conor Dooley 2022-11-16 13:54 ` [PATCH v1 4/9] PCI: microchip: Clean up initialisation of interrupts daire.mcnamara 2022-11-16 13:54 ` daire.mcnamara 2022-11-16 15:17 ` kernel test robot 2022-11-16 15:17 ` kernel test robot 2022-11-17 18:28 ` kernel test robot 2022-11-17 18:28 ` kernel test robot 2022-11-23 21:58 ` Conor Dooley 2022-11-23 21:58 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 5/9] PCI: microchip: Gather MSI information from hardware config registers daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-16 16:41 ` Bjorn Helgaas 2022-11-16 16:41 ` Bjorn Helgaas 2022-11-23 22:09 ` Conor Dooley 2022-11-23 22:09 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 6/9] PCI: microchip: Re-partition code between probe() and init() daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-23 22:39 ` Conor Dooley [this message] 2022-11-23 22:39 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 7/9] PCI: microchip: Partition outbound address translation daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-23 22:44 ` Conor Dooley 2022-11-23 22:44 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 8/9] PCI: microchip: Partition inbound " daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-16 16:49 ` Bjorn Helgaas 2022-11-16 16:49 ` Bjorn Helgaas 2022-11-16 17:01 ` Conor Dooley 2022-11-16 17:01 ` Conor Dooley 2022-11-16 20:10 ` kernel test robot 2022-11-16 20:10 ` kernel test robot 2022-11-17 6:06 ` kernel test robot 2022-11-17 6:06 ` kernel test robot 2022-11-23 23:05 ` Conor Dooley 2022-11-23 23:05 ` Conor Dooley 2022-11-16 13:55 ` [PATCH v1 9/9] riscv: dts: microchip: add parent ranges and dma-ranges for IKRD v2022.09 daire.mcnamara 2022-11-16 13:55 ` daire.mcnamara 2022-11-23 22:14 ` Conor Dooley 2022-11-23 22:14 ` Conor Dooley 2022-11-23 23:15 ` [PATCH v1 0/9] PCI: microchip: Partition address translations Conor Dooley 2022-11-23 23:15 ` Conor Dooley
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=Y36hMtARoGy2YULP@spud \ --to=conor@kernel.org \ --cc=aou@eecs.berkeley.edu \ --cc=bhelgaas@google.com \ --cc=conor.dooley@microchip.com \ --cc=daire.mcnamara@microchip.com \ --cc=devicetree@vger.kernel.org \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=kw@linux.com \ --cc=linux-pci@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=lpieralisi@kernel.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=robh+dt@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.