From: Conor Dooley <conor@kernel.org> To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com Cc: Conor Dooley <conor.dooley@microchip.com>, ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org Subject: [RFC v5.1 0/9] Generic function based cache management operations (was Re: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC) Date: Tue, 3 Jan 2023 21:03:52 +0000 [thread overview] Message-ID: <20230103210400.3500626-1-conor@kernel.org> (raw) In-Reply-To: <Y62nOqzyuUKqYDpq@spud> From: Conor Dooley <conor.dooley@microchip.com> Hey all, hopefully the $subject arrived intact! See here for prior discussion: https://lore.kernel.org/linux-riscv/Y62nOqzyuUKqYDpq@spud/#R Rather than continue that back and forth about where these drivers belonged, I've gone and created a mock-up for what it would look like if we picked drivers/cache. IMO, doing drivers/cache for the detail of vendor behaviour makes sense as it'll keep 'em out of arch/riscv while keeping the drivers together. I've taken v5 of Prabhakar's patchset & hacked at it a bit, so here is a tyre-kicked (more) generic implementation of cache management stuff via functions. I initially went and moved both the ax45mp and ccache drivers to drivers/cache & created a "subsystem" like interface, but quickly realised it was all far too trivial to exist & was intrinsically tied to the ALT_CMO_OP alternative setup on RISC-V. I trashed that so, and instead copied the interface currently used by riscv_set_cacheinfo_ops(), and created a corollary which registers cache management operations. Or maintenance, IDC which. Instead of having the vendor specific cache controller function in the errata, the generic one is there instead, which then calls the one registered by the vendor driver. I figure that even if no other non-coherent implementation ends up making it upstream, ax45mp is not going to be the only Andestech product that has a "no-iocp" variant... I sent this over the Prabhakar the other day & it works for him, so I am now sending this here as RFC. I've not yet tested it on PolarFire SoC, as we have to sort out some "fun" where archid etc are all zero. We'll require some massaging before we can use the alternatives framework as is, so that'll have to come at a later date. I included a patch, but it's marked "DON'T APPLY" for a reason ;) Notably, I have not fixed up any comments which were left against v5, bar a rebase on top of riscv/for-next. I blindly "fixed" the pmem issue, so that needs to be fixed properly for a v6, alongside the other couple bits. The other thing that is missing, and I could not think immediately of a way to do it, is a way to add additional users of this type of CMO to the alternative without having to add a specific entry for each vendor. I had first thought about using archid of 0, but that runs into problems pretty quickly as that "archid" is what we use for enabling CPU_FEATURE stuff, like Zicbom itself. Since archid uses the JEDEC IDs, perhaps we could squat on either a continuation code (or some vendor that won't make a RISC-V CPU, like Actel *cough*). I didn't go through with mocking that up, as until we sort out PolarFire SoC, there's only one user for this that I, at least, would like to have supported properly. So if anyone has ideas that are in any way less hacky than that, I am all ears. Thanks, Conor. Conor Dooley (2): cache,soc: Move SiFive CCache driver & create drivers/cache RISC-V: create a function based cache management interface Daire McNamara (1): [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Lad Prabhakar (6): riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro riscv: asm: vendorid_list: Add Andes Technology to the vendors list riscv: errata: Add Andes alternative ports riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller soc: renesas: Add L2 cache management for RZ/Five SoC .../cache/andestech,ax45mp-cache.yaml | 81 ++++++ MAINTAINERS | 15 +- arch/riscv/Kconfig.erratas | 26 ++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/andes/Makefile | 1 + arch/riscv/errata/andes/errata.c | 93 +++++++ arch/riscv/include/asm/alternative-macros.h | 46 +++- arch/riscv/include/asm/alternative.h | 3 + arch/riscv/include/asm/cacheflush.h | 23 ++ arch/riscv/include/asm/errata_list.h | 41 ++- arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/alternative.c | 5 + arch/riscv/mm/dma-noncoherent.c | 36 ++- arch/riscv/mm/pmem.c | 4 +- drivers/Kconfig | 2 + drivers/Makefile | 2 + drivers/cache/Kconfig | 25 ++ drivers/{soc/sifive => cache}/Makefile | 2 + drivers/cache/ax45mp_cache.c | 253 ++++++++++++++++++ drivers/{soc/sifive => cache}/sifive_ccache.c | 47 +++- drivers/edac/sifive_edac.c | 2 +- drivers/soc/Kconfig | 1 - drivers/soc/Makefile | 1 - drivers/soc/renesas/Kconfig | 4 + drivers/soc/sifive/Kconfig | 10 - include/{soc/sifive => cache}/sifive_ccache.h | 0 26 files changed, 684 insertions(+), 41 deletions(-) create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml create mode 100644 arch/riscv/errata/andes/Makefile create mode 100644 arch/riscv/errata/andes/errata.c create mode 100644 drivers/cache/Kconfig rename drivers/{soc/sifive => cache}/Makefile (62%) create mode 100644 drivers/cache/ax45mp_cache.c rename drivers/{soc/sifive => cache}/sifive_ccache.c (86%) delete mode 100644 drivers/soc/sifive/Kconfig rename include/{soc/sifive => cache}/sifive_ccache.h (100%) base-commit: b07de94d4501c61a3015cb0035227e449c51d87e -- 2.39.0
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org> To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com Cc: Conor Dooley <conor.dooley@microchip.com>, ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org Subject: [RFC v5.1 0/9] Generic function based cache management operations (was Re: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC) Date: Tue, 3 Jan 2023 21:03:52 +0000 [thread overview] Message-ID: <20230103210400.3500626-1-conor@kernel.org> (raw) In-Reply-To: <Y62nOqzyuUKqYDpq@spud> From: Conor Dooley <conor.dooley@microchip.com> Hey all, hopefully the $subject arrived intact! See here for prior discussion: https://lore.kernel.org/linux-riscv/Y62nOqzyuUKqYDpq@spud/#R Rather than continue that back and forth about where these drivers belonged, I've gone and created a mock-up for what it would look like if we picked drivers/cache. IMO, doing drivers/cache for the detail of vendor behaviour makes sense as it'll keep 'em out of arch/riscv while keeping the drivers together. I've taken v5 of Prabhakar's patchset & hacked at it a bit, so here is a tyre-kicked (more) generic implementation of cache management stuff via functions. I initially went and moved both the ax45mp and ccache drivers to drivers/cache & created a "subsystem" like interface, but quickly realised it was all far too trivial to exist & was intrinsically tied to the ALT_CMO_OP alternative setup on RISC-V. I trashed that so, and instead copied the interface currently used by riscv_set_cacheinfo_ops(), and created a corollary which registers cache management operations. Or maintenance, IDC which. Instead of having the vendor specific cache controller function in the errata, the generic one is there instead, which then calls the one registered by the vendor driver. I figure that even if no other non-coherent implementation ends up making it upstream, ax45mp is not going to be the only Andestech product that has a "no-iocp" variant... I sent this over the Prabhakar the other day & it works for him, so I am now sending this here as RFC. I've not yet tested it on PolarFire SoC, as we have to sort out some "fun" where archid etc are all zero. We'll require some massaging before we can use the alternatives framework as is, so that'll have to come at a later date. I included a patch, but it's marked "DON'T APPLY" for a reason ;) Notably, I have not fixed up any comments which were left against v5, bar a rebase on top of riscv/for-next. I blindly "fixed" the pmem issue, so that needs to be fixed properly for a v6, alongside the other couple bits. The other thing that is missing, and I could not think immediately of a way to do it, is a way to add additional users of this type of CMO to the alternative without having to add a specific entry for each vendor. I had first thought about using archid of 0, but that runs into problems pretty quickly as that "archid" is what we use for enabling CPU_FEATURE stuff, like Zicbom itself. Since archid uses the JEDEC IDs, perhaps we could squat on either a continuation code (or some vendor that won't make a RISC-V CPU, like Actel *cough*). I didn't go through with mocking that up, as until we sort out PolarFire SoC, there's only one user for this that I, at least, would like to have supported properly. So if anyone has ideas that are in any way less hacky than that, I am all ears. Thanks, Conor. Conor Dooley (2): cache,soc: Move SiFive CCache driver & create drivers/cache RISC-V: create a function based cache management interface Daire McNamara (1): [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Lad Prabhakar (6): riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro riscv: asm: vendorid_list: Add Andes Technology to the vendors list riscv: errata: Add Andes alternative ports riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller soc: renesas: Add L2 cache management for RZ/Five SoC .../cache/andestech,ax45mp-cache.yaml | 81 ++++++ MAINTAINERS | 15 +- arch/riscv/Kconfig.erratas | 26 ++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/andes/Makefile | 1 + arch/riscv/errata/andes/errata.c | 93 +++++++ arch/riscv/include/asm/alternative-macros.h | 46 +++- arch/riscv/include/asm/alternative.h | 3 + arch/riscv/include/asm/cacheflush.h | 23 ++ arch/riscv/include/asm/errata_list.h | 41 ++- arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/alternative.c | 5 + arch/riscv/mm/dma-noncoherent.c | 36 ++- arch/riscv/mm/pmem.c | 4 +- drivers/Kconfig | 2 + drivers/Makefile | 2 + drivers/cache/Kconfig | 25 ++ drivers/{soc/sifive => cache}/Makefile | 2 + drivers/cache/ax45mp_cache.c | 253 ++++++++++++++++++ drivers/{soc/sifive => cache}/sifive_ccache.c | 47 +++- drivers/edac/sifive_edac.c | 2 +- drivers/soc/Kconfig | 1 - drivers/soc/Makefile | 1 - drivers/soc/renesas/Kconfig | 4 + drivers/soc/sifive/Kconfig | 10 - include/{soc/sifive => cache}/sifive_ccache.h | 0 26 files changed, 684 insertions(+), 41 deletions(-) create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml create mode 100644 arch/riscv/errata/andes/Makefile create mode 100644 arch/riscv/errata/andes/errata.c create mode 100644 drivers/cache/Kconfig rename drivers/{soc/sifive => cache}/Makefile (62%) create mode 100644 drivers/cache/ax45mp_cache.c rename drivers/{soc/sifive => cache}/sifive_ccache.c (86%) delete mode 100644 drivers/soc/sifive/Kconfig rename include/{soc/sifive => cache}/sifive_ccache.h (100%) base-commit: b07de94d4501c61a3015cb0035227e449c51d87e -- 2.39.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-03 21:04 UTC|newest] Thread overview: 132+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-12 11:54 [PATCH v5 0/6] AX45MP: Add support to non-coherent DMA Prabhakar 2022-12-12 11:54 ` Prabhakar 2022-12-12 11:55 ` [PATCH v5 1/6] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-12 12:32 ` Heiko Stuebner 2022-12-12 12:32 ` Heiko Stuebner 2022-12-13 17:21 ` Geert Uytterhoeven 2022-12-13 17:21 ` Geert Uytterhoeven 2022-12-13 17:49 ` Lad, Prabhakar 2022-12-13 17:49 ` Lad, Prabhakar 2022-12-14 14:34 ` Andrew Jones 2022-12-14 14:34 ` Andrew Jones 2022-12-17 21:41 ` Conor Dooley 2022-12-17 21:41 ` Conor Dooley 2022-12-19 11:15 ` Lad, Prabhakar 2022-12-19 11:15 ` Lad, Prabhakar 2022-12-19 16:22 ` Conor Dooley 2022-12-19 16:22 ` Conor Dooley 2022-12-19 16:24 ` Lad, Prabhakar 2022-12-19 16:24 ` Lad, Prabhakar 2022-12-12 11:55 ` [PATCH v5 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-12 11:55 ` [PATCH v5 3/6] riscv: errata: Add Andes alternative ports Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-17 21:19 ` Conor Dooley 2022-12-17 21:19 ` Conor Dooley 2022-12-19 11:19 ` Lad, Prabhakar 2022-12-19 11:19 ` Lad, Prabhakar 2022-12-19 16:20 ` Conor Dooley 2022-12-19 16:20 ` Conor Dooley 2022-12-21 0:31 ` Lad, Prabhakar 2022-12-21 0:31 ` Lad, Prabhakar 2022-12-12 11:55 ` [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-13 17:14 ` Geert Uytterhoeven 2022-12-13 17:14 ` Geert Uytterhoeven 2022-12-13 17:57 ` Lad, Prabhakar 2022-12-13 17:57 ` Lad, Prabhakar 2022-12-17 20:52 ` Conor Dooley 2022-12-17 20:52 ` Conor Dooley 2022-12-19 11:21 ` Lad, Prabhakar 2022-12-19 11:21 ` Lad, Prabhakar 2022-12-12 11:55 ` [PATCH v5 5/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-12 17:28 ` Rob Herring 2022-12-12 17:28 ` Rob Herring 2022-12-12 11:55 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-15 10:34 ` Geert Uytterhoeven 2022-12-15 10:34 ` Geert Uytterhoeven 2022-12-15 11:03 ` Lad, Prabhakar 2022-12-15 11:03 ` Lad, Prabhakar 2022-12-15 11:10 ` Geert Uytterhoeven 2022-12-15 11:10 ` Geert Uytterhoeven 2022-12-15 17:46 ` Lad, Prabhakar 2022-12-15 17:46 ` Lad, Prabhakar 2022-12-15 19:54 ` Conor Dooley 2022-12-15 19:54 ` Conor Dooley 2022-12-15 20:17 ` Geert Uytterhoeven 2022-12-15 20:17 ` Geert Uytterhoeven 2022-12-15 20:32 ` Conor Dooley 2022-12-15 20:32 ` Conor Dooley 2022-12-15 21:40 ` Palmer Dabbelt 2022-12-15 21:40 ` Palmer Dabbelt 2022-12-16 7:02 ` Christoph Hellwig 2022-12-16 7:02 ` Christoph Hellwig 2022-12-16 16:32 ` Palmer Dabbelt 2022-12-16 16:32 ` Palmer Dabbelt 2022-12-16 20:04 ` Arnd Bergmann 2022-12-16 20:04 ` Arnd Bergmann 2022-12-17 22:52 ` Conor Dooley 2022-12-17 22:52 ` Conor Dooley 2022-12-19 12:43 ` Lad, Prabhakar 2022-12-19 12:43 ` Lad, Prabhakar 2022-12-19 16:08 ` Conor Dooley 2022-12-19 16:08 ` Conor Dooley 2022-12-29 14:05 ` Arnd Bergmann 2022-12-29 14:05 ` Arnd Bergmann 2022-12-29 14:42 ` Conor Dooley 2022-12-29 14:42 ` Conor Dooley 2023-01-03 21:03 ` Conor Dooley [this message] 2023-01-03 21:03 ` [RFC v5.1 0/9] Generic function based cache management operations (was Re: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC) Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 1/9] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 2/9] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 3/9] riscv: errata: Add Andes alternative ports Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 4/9] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 5/9] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 6/9] cache,soc: Move SiFive CCache driver & create drivers/cache Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-04 9:50 ` Ben Dooks 2023-01-04 9:50 ` Ben Dooks 2023-01-04 10:18 ` Conor Dooley 2023-01-04 10:18 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 7/9] RISC-V: create a function based cache management interface Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:04 ` [RFC v5.1 8/9] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley 2023-01-03 21:04 ` Conor Dooley 2023-01-03 21:04 ` [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Conor Dooley 2023-01-03 21:04 ` Conor Dooley 2023-01-03 21:25 ` Palmer Dabbelt 2023-01-03 21:25 ` Palmer Dabbelt 2023-01-03 21:28 ` Arnd Bergmann 2023-01-03 21:28 ` Arnd Bergmann 2023-01-04 0:00 ` Conor Dooley 2023-01-04 0:00 ` Conor Dooley 2023-01-04 8:17 ` Arnd Bergmann 2023-01-04 8:17 ` Arnd Bergmann 2023-01-04 9:23 ` Conor Dooley 2023-01-04 9:23 ` Conor Dooley 2023-01-04 10:19 ` Arnd Bergmann 2023-01-04 10:19 ` Arnd Bergmann 2023-01-04 11:56 ` Conor Dooley 2023-01-04 11:56 ` Conor Dooley 2023-01-04 12:18 ` Arnd Bergmann 2023-01-04 12:18 ` Arnd Bergmann 2023-01-04 13:20 ` Conor Dooley 2023-01-04 13:20 ` Conor Dooley 2023-01-04 14:15 ` Arnd Bergmann 2023-01-04 14:15 ` Arnd Bergmann 2023-01-04 9:45 ` Ben Dooks 2023-01-04 9:45 ` Ben Dooks 2023-01-04 9:57 ` Conor Dooley 2023-01-04 9:57 ` Conor Dooley 2022-12-17 21:35 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley 2022-12-17 21:35 ` Conor Dooley 2022-12-28 3:16 ` Samuel Holland 2022-12-28 3:16 ` Samuel Holland
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