From: Ben Dooks <ben.dooks@codethink.co.uk> To: Conor Dooley <conor@kernel.org>, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com Cc: Conor Dooley <conor.dooley@microchip.com>, ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org, Daire McNamara <daire.mcnamara@microchip.com> Subject: Re: [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Date: Wed, 4 Jan 2023 09:45:30 +0000 [thread overview] Message-ID: <6ef122f6-12fa-777f-b4e7-a02531380391@codethink.co.uk> (raw) In-Reply-To: <20230103210400.3500626-10-conor@kernel.org> On 03/01/2023 21:04, Conor Dooley wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > SiFive L2 cache controller can flush L2 cache. Expose this capability via > driver. > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > [Conor: rebase on top of move to cache subsystem] > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > This commit needs more work, and a way to enable it from errata. I've > not gone and done this as PolarFire SoC has archid etc all set to zero. > So we need to go figure out a workaround for this, before adding in > errata enabling code for this. I've included it here as a second user of > the cache management stuff, since what's currently upstream for the > ccache driver does not do any cache management. I think errata isn't the right word here, it's more of a system requirement for anything that isn't coherent. All the SiFive systems I have are coherent so won't need this. > --- > drivers/cache/sifive_ccache.c | 45 +++++++++++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c > index 47e7d6557f85..3c00f205bace 100644 > --- a/drivers/cache/sifive_ccache.c > +++ b/drivers/cache/sifive_ccache.c > @@ -9,12 +9,14 @@ > #define pr_fmt(fmt) "CCACHE: " fmt > > #include <linux/debugfs.h> > +#include <linux/dma-direction.h> > #include <linux/interrupt.h> > #include <linux/of_irq.h> > #include <linux/of_address.h> > #include <linux/device.h> > #include <linux/bitfield.h> > #include <asm/cacheinfo.h> > +#include <asm/cacheflush.h> > #include <cache/sifive_ccache.h> > > #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 > @@ -42,11 +44,15 @@ > #define SIFIVE_CCACHE_WAYENABLE 0x08 > #define SIFIVE_CCACHE_ECCINJECTERR 0x40 > > +#define SIFIVE_CCACHE_FLUSH64 0x200 > +#define SIFIVE_CCACHE_FLUSH32 0x240 > + > #define SIFIVE_CCACHE_MAX_ECCINTR 4 > > static void __iomem *ccache_base; > static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; > static struct riscv_cacheinfo_ops ccache_cache_ops; > +static struct riscv_cache_maint_ops ccache_cmos; > static int level; > > enum { > @@ -205,6 +211,42 @@ static irqreturn_t ccache_int_handler(int irq, void *device) > return IRQ_HANDLED; > } > > +static void sifive_ccache_dma_wback_inv(void* vaddr, unsigned long size) > +{ > + void * __iomem flush = ccache_base + SIFIVE_CCACHE_FLUSH64; > + phys_addr_t start = virt_to_phys(vaddr); > + phys_addr_t aligned_start = start & ~0x3f; > + u64 addr; > + u64 end; > + u64 aligned_end; > + > + size += start - aligned_start; > + end = start + size; > + aligned_end = end += 0x3f; I think you meant + 0x3f here. There is an align macro in the kernel headers, and I'm not sure by inspection if you'd miss the last line with this code. > + aligned_end &= ~0x3f; > + > + for (addr = aligned_start; addr < aligned_end; addr += 64) > + writeq(addr, flush); > +} The p550 manual states that the zero device flush method is quicker for any large area flush. However not sure what that level is and whether it is worth dealing with here? If so we need to have the L3 zero are mapped. > + > +static void sifive_ccache_cmo(unsigned int cache_size, void *vaddr, size_t size, > + int dir, int ops) > +{ technically dir should have been of type "enum dma_data_direction" > + switch (dir) { > + case DMA_TO_DEVICE: > + sifive_ccache_dma_wback_inv(vaddr, size); > + break; > + case DMA_FROM_DEVICE: > + sifive_ccache_dma_wback_inv(vaddr, size); > + break; > + case DMA_BIDIRECTIONAL: > + sifive_ccache_dma_wback_inv(vaddr, size); > + break; > + default: > + break; > + } > +} I'm not sure why you'd bother checking the dir here, the cache can only be flushed (I hope DMA_FROM_DEVICE is done /before/ the DMA op). You could have saved yourself an include if just ignoring dir. > + > static int __init sifive_ccache_init(void) > { > struct device_node *np; > @@ -254,6 +296,9 @@ static int __init sifive_ccache_init(void) > ccache_cache_ops.get_priv_group = ccache_get_priv_group; > riscv_set_cacheinfo_ops(&ccache_cache_ops); > > + ccache_cmos.cmo_patchfunc = sifive_ccache_cmo; > + riscv_set_cache_maint_ops(&ccache_cmos); > + > #ifdef CONFIG_DEBUG_FS > setup_sifive_debug(); > #endif -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html
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From: Ben Dooks <ben.dooks@codethink.co.uk> To: Conor Dooley <conor@kernel.org>, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com Cc: Conor Dooley <conor.dooley@microchip.com>, ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org, Daire McNamara <daire.mcnamara@microchip.com> Subject: Re: [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Date: Wed, 4 Jan 2023 09:45:30 +0000 [thread overview] Message-ID: <6ef122f6-12fa-777f-b4e7-a02531380391@codethink.co.uk> (raw) In-Reply-To: <20230103210400.3500626-10-conor@kernel.org> On 03/01/2023 21:04, Conor Dooley wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > SiFive L2 cache controller can flush L2 cache. Expose this capability via > driver. > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > [Conor: rebase on top of move to cache subsystem] > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > This commit needs more work, and a way to enable it from errata. I've > not gone and done this as PolarFire SoC has archid etc all set to zero. > So we need to go figure out a workaround for this, before adding in > errata enabling code for this. I've included it here as a second user of > the cache management stuff, since what's currently upstream for the > ccache driver does not do any cache management. I think errata isn't the right word here, it's more of a system requirement for anything that isn't coherent. All the SiFive systems I have are coherent so won't need this. > --- > drivers/cache/sifive_ccache.c | 45 +++++++++++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c > index 47e7d6557f85..3c00f205bace 100644 > --- a/drivers/cache/sifive_ccache.c > +++ b/drivers/cache/sifive_ccache.c > @@ -9,12 +9,14 @@ > #define pr_fmt(fmt) "CCACHE: " fmt > > #include <linux/debugfs.h> > +#include <linux/dma-direction.h> > #include <linux/interrupt.h> > #include <linux/of_irq.h> > #include <linux/of_address.h> > #include <linux/device.h> > #include <linux/bitfield.h> > #include <asm/cacheinfo.h> > +#include <asm/cacheflush.h> > #include <cache/sifive_ccache.h> > > #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 > @@ -42,11 +44,15 @@ > #define SIFIVE_CCACHE_WAYENABLE 0x08 > #define SIFIVE_CCACHE_ECCINJECTERR 0x40 > > +#define SIFIVE_CCACHE_FLUSH64 0x200 > +#define SIFIVE_CCACHE_FLUSH32 0x240 > + > #define SIFIVE_CCACHE_MAX_ECCINTR 4 > > static void __iomem *ccache_base; > static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; > static struct riscv_cacheinfo_ops ccache_cache_ops; > +static struct riscv_cache_maint_ops ccache_cmos; > static int level; > > enum { > @@ -205,6 +211,42 @@ static irqreturn_t ccache_int_handler(int irq, void *device) > return IRQ_HANDLED; > } > > +static void sifive_ccache_dma_wback_inv(void* vaddr, unsigned long size) > +{ > + void * __iomem flush = ccache_base + SIFIVE_CCACHE_FLUSH64; > + phys_addr_t start = virt_to_phys(vaddr); > + phys_addr_t aligned_start = start & ~0x3f; > + u64 addr; > + u64 end; > + u64 aligned_end; > + > + size += start - aligned_start; > + end = start + size; > + aligned_end = end += 0x3f; I think you meant + 0x3f here. There is an align macro in the kernel headers, and I'm not sure by inspection if you'd miss the last line with this code. > + aligned_end &= ~0x3f; > + > + for (addr = aligned_start; addr < aligned_end; addr += 64) > + writeq(addr, flush); > +} The p550 manual states that the zero device flush method is quicker for any large area flush. However not sure what that level is and whether it is worth dealing with here? If so we need to have the L3 zero are mapped. > + > +static void sifive_ccache_cmo(unsigned int cache_size, void *vaddr, size_t size, > + int dir, int ops) > +{ technically dir should have been of type "enum dma_data_direction" > + switch (dir) { > + case DMA_TO_DEVICE: > + sifive_ccache_dma_wback_inv(vaddr, size); > + break; > + case DMA_FROM_DEVICE: > + sifive_ccache_dma_wback_inv(vaddr, size); > + break; > + case DMA_BIDIRECTIONAL: > + sifive_ccache_dma_wback_inv(vaddr, size); > + break; > + default: > + break; > + } > +} I'm not sure why you'd bother checking the dir here, the cache can only be flushed (I hope DMA_FROM_DEVICE is done /before/ the DMA op). You could have saved yourself an include if just ignoring dir. > + > static int __init sifive_ccache_init(void) > { > struct device_node *np; > @@ -254,6 +296,9 @@ static int __init sifive_ccache_init(void) > ccache_cache_ops.get_priv_group = ccache_get_priv_group; > riscv_set_cacheinfo_ops(&ccache_cache_ops); > > + ccache_cmos.cmo_patchfunc = sifive_ccache_cmo; > + riscv_set_cache_maint_ops(&ccache_cmos); > + > #ifdef CONFIG_DEBUG_FS > setup_sifive_debug(); > #endif -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-04 9:57 UTC|newest] Thread overview: 132+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-12 11:54 [PATCH v5 0/6] AX45MP: Add support to non-coherent DMA Prabhakar 2022-12-12 11:54 ` Prabhakar 2022-12-12 11:55 ` [PATCH v5 1/6] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-12 12:32 ` Heiko Stuebner 2022-12-12 12:32 ` Heiko Stuebner 2022-12-13 17:21 ` Geert Uytterhoeven 2022-12-13 17:21 ` Geert Uytterhoeven 2022-12-13 17:49 ` Lad, Prabhakar 2022-12-13 17:49 ` Lad, Prabhakar 2022-12-14 14:34 ` Andrew Jones 2022-12-14 14:34 ` Andrew Jones 2022-12-17 21:41 ` Conor Dooley 2022-12-17 21:41 ` Conor Dooley 2022-12-19 11:15 ` Lad, Prabhakar 2022-12-19 11:15 ` Lad, Prabhakar 2022-12-19 16:22 ` Conor Dooley 2022-12-19 16:22 ` Conor Dooley 2022-12-19 16:24 ` Lad, Prabhakar 2022-12-19 16:24 ` Lad, Prabhakar 2022-12-12 11:55 ` [PATCH v5 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-12 11:55 ` [PATCH v5 3/6] riscv: errata: Add Andes alternative ports Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-17 21:19 ` Conor Dooley 2022-12-17 21:19 ` Conor Dooley 2022-12-19 11:19 ` Lad, Prabhakar 2022-12-19 11:19 ` Lad, Prabhakar 2022-12-19 16:20 ` Conor Dooley 2022-12-19 16:20 ` Conor Dooley 2022-12-21 0:31 ` Lad, Prabhakar 2022-12-21 0:31 ` Lad, Prabhakar 2022-12-12 11:55 ` [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-13 17:14 ` Geert Uytterhoeven 2022-12-13 17:14 ` Geert Uytterhoeven 2022-12-13 17:57 ` Lad, Prabhakar 2022-12-13 17:57 ` Lad, Prabhakar 2022-12-17 20:52 ` Conor Dooley 2022-12-17 20:52 ` Conor Dooley 2022-12-19 11:21 ` Lad, Prabhakar 2022-12-19 11:21 ` Lad, Prabhakar 2022-12-12 11:55 ` [PATCH v5 5/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-12 17:28 ` Rob Herring 2022-12-12 17:28 ` Rob Herring 2022-12-12 11:55 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-15 10:34 ` Geert Uytterhoeven 2022-12-15 10:34 ` Geert Uytterhoeven 2022-12-15 11:03 ` Lad, Prabhakar 2022-12-15 11:03 ` Lad, Prabhakar 2022-12-15 11:10 ` Geert Uytterhoeven 2022-12-15 11:10 ` Geert Uytterhoeven 2022-12-15 17:46 ` Lad, Prabhakar 2022-12-15 17:46 ` Lad, Prabhakar 2022-12-15 19:54 ` Conor Dooley 2022-12-15 19:54 ` Conor Dooley 2022-12-15 20:17 ` Geert Uytterhoeven 2022-12-15 20:17 ` Geert Uytterhoeven 2022-12-15 20:32 ` Conor Dooley 2022-12-15 20:32 ` Conor Dooley 2022-12-15 21:40 ` Palmer Dabbelt 2022-12-15 21:40 ` Palmer Dabbelt 2022-12-16 7:02 ` Christoph Hellwig 2022-12-16 7:02 ` Christoph Hellwig 2022-12-16 16:32 ` Palmer Dabbelt 2022-12-16 16:32 ` Palmer Dabbelt 2022-12-16 20:04 ` Arnd Bergmann 2022-12-16 20:04 ` Arnd Bergmann 2022-12-17 22:52 ` Conor Dooley 2022-12-17 22:52 ` Conor Dooley 2022-12-19 12:43 ` Lad, Prabhakar 2022-12-19 12:43 ` Lad, Prabhakar 2022-12-19 16:08 ` Conor Dooley 2022-12-19 16:08 ` Conor Dooley 2022-12-29 14:05 ` Arnd Bergmann 2022-12-29 14:05 ` Arnd Bergmann 2022-12-29 14:42 ` Conor Dooley 2022-12-29 14:42 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 0/9] Generic function based cache management operations (was Re: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC) Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 1/9] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 2/9] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 3/9] riscv: errata: Add Andes alternative ports Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 4/9] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 5/9] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 6/9] cache,soc: Move SiFive CCache driver & create drivers/cache Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-04 9:50 ` Ben Dooks 2023-01-04 9:50 ` Ben Dooks 2023-01-04 10:18 ` Conor Dooley 2023-01-04 10:18 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 7/9] RISC-V: create a function based cache management interface Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:04 ` [RFC v5.1 8/9] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley 2023-01-03 21:04 ` Conor Dooley 2023-01-03 21:04 ` [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Conor Dooley 2023-01-03 21:04 ` Conor Dooley 2023-01-03 21:25 ` Palmer Dabbelt 2023-01-03 21:25 ` Palmer Dabbelt 2023-01-03 21:28 ` Arnd Bergmann 2023-01-03 21:28 ` Arnd Bergmann 2023-01-04 0:00 ` Conor Dooley 2023-01-04 0:00 ` Conor Dooley 2023-01-04 8:17 ` Arnd Bergmann 2023-01-04 8:17 ` Arnd Bergmann 2023-01-04 9:23 ` Conor Dooley 2023-01-04 9:23 ` Conor Dooley 2023-01-04 10:19 ` Arnd Bergmann 2023-01-04 10:19 ` Arnd Bergmann 2023-01-04 11:56 ` Conor Dooley 2023-01-04 11:56 ` Conor Dooley 2023-01-04 12:18 ` Arnd Bergmann 2023-01-04 12:18 ` Arnd Bergmann 2023-01-04 13:20 ` Conor Dooley 2023-01-04 13:20 ` Conor Dooley 2023-01-04 14:15 ` Arnd Bergmann 2023-01-04 14:15 ` Arnd Bergmann 2023-01-04 9:45 ` Ben Dooks [this message] 2023-01-04 9:45 ` Ben Dooks 2023-01-04 9:57 ` Conor Dooley 2023-01-04 9:57 ` Conor Dooley 2022-12-17 21:35 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley 2022-12-17 21:35 ` Conor Dooley 2022-12-28 3:16 ` Samuel Holland 2022-12-28 3:16 ` Samuel Holland
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