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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Albert Ou <aou@eecs.berkeley.edu>,
	Magnus Damm <magnus.damm@gmail.com>,
	 Heiko Stuebner <heiko@sntech.de>,
	Conor Dooley <conor.dooley@microchip.com>,
	 Samuel Holland <samuel@sholland.org>,
	Guo Ren <guoren@kernel.org>,  Rob Herring <robh+dt@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Jisheng Zhang <jszhang@kernel.org>,
	 Atish Patra <atishp@rivosinc.com>,
	Anup Patel <apatel@ventanamicro.com>,
	 Andrew Jones <ajones@ventanamicro.com>,
	Nathan Chancellor <nathan@kernel.org>,
	 Philipp Tomsich <philipp.tomsich@vrull.eu>,
	devicetree@vger.kernel.org,  linux-riscv@lists.infradead.org,
	linux-renesas-soc@vger.kernel.org,  linux-kernel@vger.kernel.org,
	Biju Das <biju.das.jz@bp.renesas.com>,
	 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v5 1/6] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro
Date: Tue, 13 Dec 2022 18:21:07 +0100	[thread overview]
Message-ID: <CAMuHMdXXXN9g8o1j7k-TC=F-kuyf-KngFSKi7z9z0SY9BLxmHA@mail.gmail.com> (raw)
In-Reply-To: <20221212115505.36770-2-prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi Prabhakar,

On Mon, Dec 12, 2022 at 12:58 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Introduce ALTERNATIVE_3() macro.
>
> A vendor wants to replace an old_content, but another vendor has used
> ALTERNATIVE_2() to patch its customized content at the same location.
> In this case, this vendor can use macro ALTERNATIVE_3() and then replace
> ALTERNATIVE_2() with ALTERNATIVE_3() to append its customized content.
>
> While at it update comment above ALTERNATIVE_2() macro and make it generic
> so that the comment holds good for any new addition of ALTERNATIVE_X()
> macros.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4->v5
> * Rebased the patch on top of Andrew's series (now in Palmers for next-branch)
> * Updated comment for ALTERNATIVE_x() as suggested by Heiko

Thanks for the update!

> --- a/arch/riscv/include/asm/alternative-macros.h
> +++ b/arch/riscv/include/asm/alternative-macros.h
> @@ -50,8 +50,17 @@
>         ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
>  .endm
>
> +.macro ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1,   \
> +                               new_c_2, vendor_id_2, errata_id_2, enable_2,    \
> +                               new_c_3, vendor_id_3, errata_id_3, enable_3
> +       ALTERNATIVE_CFG_2 \old_c, \new_c_1, \vendor_id_1, \errata_id_1, \enable_1,      \
> +                                 \new_c_2, \vendor_id_2, \errata_id_2, \enable_2
> +       ALT_NEW_CONTENT \vendor_id_3, \errata_id_3, \enable_3, \new_c_3
> +.endm
> +
>  #define __ALTERNATIVE_CFG(...)         ALTERNATIVE_CFG __VA_ARGS__
>  #define __ALTERNATIVE_CFG_2(...)       ALTERNATIVE_CFG_2 __VA_ARGS__
> +#define __ALTERNATIVE_CFG_3(...)       ALTERNATIVE_CFG_3 __VA_ARGS__
>
>  #else /* !__ASSEMBLY__ */
>
> @@ -98,6 +107,13 @@
>         __ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1)   \
>         ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
>
> +#define __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1,        \
> +                                  new_c_2, vendor_id_2, errata_id_2, enable_2, \
> +                                  new_c_3, vendor_id_3, errata_id_3, enable_3) \
> +       __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
> +                                   new_c_2, vendor_id_2, errata_id_2, enable_2)        \
> +       ALT_NEW_CONTENT(vendor_id_3, errata_id_3, enable_3, new_c_3)
> +
>  #endif /* __ASSEMBLY__ */
>
>  #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
> @@ -108,6 +124,13 @@
>         __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),   \
>                                    new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2))
>
> +#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1,               \
> +                                 new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2,                \
> +                                 new_c_3, vendor_id_3, errata_id_3, CONFIG_k_3)                \
> +       __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),   \
> +                                  new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2),   \
> +                                  new_c_3, vendor_id_3, errata_id_3, IS_ENABLED(CONFIG_k_3))
> +
>  #else /* CONFIG_RISCV_ALTERNATIVE */

To avoid breaking the build for K210 (and VexRiscv), you need to provide
_ALTERNATIVE_CFG_3() for the !CONFIG_RISCV_ALTERNATIVE case, too:

@@ -144,6 +144,9 @@
 #define _ALTERNATIVE_CFG_2(old_c, ...) \
        ALTERNATIVE_CFG old_c

+#define _ALTERNATIVE_CFG_3(old_c, ...) \
+       ALTERNATIVE_CFG old_c
+
 #else /* !__ASSEMBLY__ */

 #define __ALTERNATIVE_CFG(old_c)       \
@@ -155,6 +158,9 @@
 #define _ALTERNATIVE_CFG_2(old_c, ...) \
        __ALTERNATIVE_CFG(old_c)

+#define _ALTERNATIVE_CFG_3(old_c, ...) \
+       __ALTERNATIVE_CFG(old_c)
+
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_RISCV_ALTERNATIVE */

Else it fails (on riscv/for-next) with:

arch/riscv/mm/pmem.c: In function ‘arch_wb_cache_pmem’:
arch/riscv/include/asm/alternative-macros.h:198:8: error: expected
string literal before ‘_ALTERNATIVE_CFG_3’
  198 |        _ALTERNATIVE_CFG_3(old_content, new_content_1,
vendor_id_1, errata_id_1, CONFIG_k_1, \
      |        ^~~~~~~~~~~~~~~~~~
arch/riscv/include/asm/errata_list.h:128:14: note: in expansion of
macro ‘ALTERNATIVE_3’
  128 | asm volatile(ALTERNATIVE_3(      \
      |              ^~~~~~~~~~~~~
arch/riscv/mm/pmem.c:13:2: note: in expansion of macro ‘ALT_CMO_OP’
   13 |  ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size, 0, 0);
      |  ^~~~~~~~~~

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Magnus Damm <magnus.damm@gmail.com>,
	Heiko Stuebner <heiko@sntech.de>,
	Conor Dooley <conor.dooley@microchip.com>,
	Samuel Holland <samuel@sholland.org>, Guo Ren <guoren@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Jisheng Zhang <jszhang@kernel.org>,
	Atish Patra <atishp@rivosinc.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Nathan Chancellor <nathan@kernel.org>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v5 1/6] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro
Date: Tue, 13 Dec 2022 18:21:07 +0100	[thread overview]
Message-ID: <CAMuHMdXXXN9g8o1j7k-TC=F-kuyf-KngFSKi7z9z0SY9BLxmHA@mail.gmail.com> (raw)
In-Reply-To: <20221212115505.36770-2-prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi Prabhakar,

On Mon, Dec 12, 2022 at 12:58 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Introduce ALTERNATIVE_3() macro.
>
> A vendor wants to replace an old_content, but another vendor has used
> ALTERNATIVE_2() to patch its customized content at the same location.
> In this case, this vendor can use macro ALTERNATIVE_3() and then replace
> ALTERNATIVE_2() with ALTERNATIVE_3() to append its customized content.
>
> While at it update comment above ALTERNATIVE_2() macro and make it generic
> so that the comment holds good for any new addition of ALTERNATIVE_X()
> macros.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4->v5
> * Rebased the patch on top of Andrew's series (now in Palmers for next-branch)
> * Updated comment for ALTERNATIVE_x() as suggested by Heiko

Thanks for the update!

> --- a/arch/riscv/include/asm/alternative-macros.h
> +++ b/arch/riscv/include/asm/alternative-macros.h
> @@ -50,8 +50,17 @@
>         ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
>  .endm
>
> +.macro ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1,   \
> +                               new_c_2, vendor_id_2, errata_id_2, enable_2,    \
> +                               new_c_3, vendor_id_3, errata_id_3, enable_3
> +       ALTERNATIVE_CFG_2 \old_c, \new_c_1, \vendor_id_1, \errata_id_1, \enable_1,      \
> +                                 \new_c_2, \vendor_id_2, \errata_id_2, \enable_2
> +       ALT_NEW_CONTENT \vendor_id_3, \errata_id_3, \enable_3, \new_c_3
> +.endm
> +
>  #define __ALTERNATIVE_CFG(...)         ALTERNATIVE_CFG __VA_ARGS__
>  #define __ALTERNATIVE_CFG_2(...)       ALTERNATIVE_CFG_2 __VA_ARGS__
> +#define __ALTERNATIVE_CFG_3(...)       ALTERNATIVE_CFG_3 __VA_ARGS__
>
>  #else /* !__ASSEMBLY__ */
>
> @@ -98,6 +107,13 @@
>         __ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1)   \
>         ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
>
> +#define __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1,        \
> +                                  new_c_2, vendor_id_2, errata_id_2, enable_2, \
> +                                  new_c_3, vendor_id_3, errata_id_3, enable_3) \
> +       __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
> +                                   new_c_2, vendor_id_2, errata_id_2, enable_2)        \
> +       ALT_NEW_CONTENT(vendor_id_3, errata_id_3, enable_3, new_c_3)
> +
>  #endif /* __ASSEMBLY__ */
>
>  #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
> @@ -108,6 +124,13 @@
>         __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),   \
>                                    new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2))
>
> +#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1,               \
> +                                 new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2,                \
> +                                 new_c_3, vendor_id_3, errata_id_3, CONFIG_k_3)                \
> +       __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),   \
> +                                  new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2),   \
> +                                  new_c_3, vendor_id_3, errata_id_3, IS_ENABLED(CONFIG_k_3))
> +
>  #else /* CONFIG_RISCV_ALTERNATIVE */

To avoid breaking the build for K210 (and VexRiscv), you need to provide
_ALTERNATIVE_CFG_3() for the !CONFIG_RISCV_ALTERNATIVE case, too:

@@ -144,6 +144,9 @@
 #define _ALTERNATIVE_CFG_2(old_c, ...) \
        ALTERNATIVE_CFG old_c

+#define _ALTERNATIVE_CFG_3(old_c, ...) \
+       ALTERNATIVE_CFG old_c
+
 #else /* !__ASSEMBLY__ */

 #define __ALTERNATIVE_CFG(old_c)       \
@@ -155,6 +158,9 @@
 #define _ALTERNATIVE_CFG_2(old_c, ...) \
        __ALTERNATIVE_CFG(old_c)

+#define _ALTERNATIVE_CFG_3(old_c, ...) \
+       __ALTERNATIVE_CFG(old_c)
+
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_RISCV_ALTERNATIVE */

Else it fails (on riscv/for-next) with:

arch/riscv/mm/pmem.c: In function ‘arch_wb_cache_pmem’:
arch/riscv/include/asm/alternative-macros.h:198:8: error: expected
string literal before ‘_ALTERNATIVE_CFG_3’
  198 |        _ALTERNATIVE_CFG_3(old_content, new_content_1,
vendor_id_1, errata_id_1, CONFIG_k_1, \
      |        ^~~~~~~~~~~~~~~~~~
arch/riscv/include/asm/errata_list.h:128:14: note: in expansion of
macro ‘ALTERNATIVE_3’
  128 | asm volatile(ALTERNATIVE_3(      \
      |              ^~~~~~~~~~~~~
arch/riscv/mm/pmem.c:13:2: note: in expansion of macro ‘ALT_CMO_OP’
   13 |  ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size, 0, 0);
      |  ^~~~~~~~~~

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  parent reply	other threads:[~2022-12-13 17:21 UTC|newest]

Thread overview: 132+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-12 11:54 [PATCH v5 0/6] AX45MP: Add support to non-coherent DMA Prabhakar
2022-12-12 11:54 ` Prabhakar
2022-12-12 11:55 ` [PATCH v5 1/6] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2022-12-12 11:55   ` Prabhakar
2022-12-12 12:32   ` Heiko Stuebner
2022-12-12 12:32     ` Heiko Stuebner
2022-12-13 17:21   ` Geert Uytterhoeven [this message]
2022-12-13 17:21     ` Geert Uytterhoeven
2022-12-13 17:49     ` Lad, Prabhakar
2022-12-13 17:49       ` Lad, Prabhakar
2022-12-14 14:34       ` Andrew Jones
2022-12-14 14:34         ` Andrew Jones
2022-12-17 21:41   ` Conor Dooley
2022-12-17 21:41     ` Conor Dooley
2022-12-19 11:15     ` Lad, Prabhakar
2022-12-19 11:15       ` Lad, Prabhakar
2022-12-19 16:22       ` Conor Dooley
2022-12-19 16:22         ` Conor Dooley
2022-12-19 16:24         ` Lad, Prabhakar
2022-12-19 16:24           ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-12-12 11:55   ` Prabhakar
2022-12-12 11:55 ` [PATCH v5 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2022-12-12 11:55   ` Prabhakar
2022-12-17 21:19   ` Conor Dooley
2022-12-17 21:19     ` Conor Dooley
2022-12-19 11:19     ` Lad, Prabhakar
2022-12-19 11:19       ` Lad, Prabhakar
2022-12-19 16:20       ` Conor Dooley
2022-12-19 16:20         ` Conor Dooley
2022-12-21  0:31         ` Lad, Prabhakar
2022-12-21  0:31           ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-12-12 11:55   ` Prabhakar
2022-12-13 17:14   ` Geert Uytterhoeven
2022-12-13 17:14     ` Geert Uytterhoeven
2022-12-13 17:57     ` Lad, Prabhakar
2022-12-13 17:57       ` Lad, Prabhakar
2022-12-17 20:52   ` Conor Dooley
2022-12-17 20:52     ` Conor Dooley
2022-12-19 11:21     ` Lad, Prabhakar
2022-12-19 11:21       ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 5/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-12-12 11:55   ` Prabhakar
2022-12-12 17:28   ` Rob Herring
2022-12-12 17:28     ` Rob Herring
2022-12-12 11:55 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-12-12 11:55   ` Prabhakar
2022-12-15 10:34   ` Geert Uytterhoeven
2022-12-15 10:34     ` Geert Uytterhoeven
2022-12-15 11:03     ` Lad, Prabhakar
2022-12-15 11:03       ` Lad, Prabhakar
2022-12-15 11:10       ` Geert Uytterhoeven
2022-12-15 11:10         ` Geert Uytterhoeven
2022-12-15 17:46         ` Lad, Prabhakar
2022-12-15 17:46           ` Lad, Prabhakar
2022-12-15 19:54           ` Conor Dooley
2022-12-15 19:54             ` Conor Dooley
2022-12-15 20:17             ` Geert Uytterhoeven
2022-12-15 20:17               ` Geert Uytterhoeven
2022-12-15 20:32               ` Conor Dooley
2022-12-15 20:32                 ` Conor Dooley
2022-12-15 21:40               ` Palmer Dabbelt
2022-12-15 21:40                 ` Palmer Dabbelt
2022-12-16  7:02                 ` Christoph Hellwig
2022-12-16  7:02                   ` Christoph Hellwig
2022-12-16 16:32                   ` Palmer Dabbelt
2022-12-16 16:32                     ` Palmer Dabbelt
2022-12-16 20:04                     ` Arnd Bergmann
2022-12-16 20:04                       ` Arnd Bergmann
2022-12-17 22:52                       ` Conor Dooley
2022-12-17 22:52                         ` Conor Dooley
2022-12-19 12:43                         ` Lad, Prabhakar
2022-12-19 12:43                           ` Lad, Prabhakar
2022-12-19 16:08                           ` Conor Dooley
2022-12-19 16:08                             ` Conor Dooley
2022-12-29 14:05                         ` Arnd Bergmann
2022-12-29 14:05                           ` Arnd Bergmann
2022-12-29 14:42                           ` Conor Dooley
2022-12-29 14:42                             ` Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 0/9] Generic function based cache management operations (was Re: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC) Conor Dooley
2023-01-03 21:03                               ` Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 1/9] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Conor Dooley
2023-01-03 21:03                               ` Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 2/9] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Conor Dooley
2023-01-03 21:03                               ` Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 3/9] riscv: errata: Add Andes alternative ports Conor Dooley
2023-01-03 21:03                               ` Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 4/9] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Conor Dooley
2023-01-03 21:03                               ` Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 5/9] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Conor Dooley
2023-01-03 21:03                               ` Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 6/9] cache,soc: Move SiFive CCache driver & create drivers/cache Conor Dooley
2023-01-03 21:03                               ` Conor Dooley
2023-01-04  9:50                               ` Ben Dooks
2023-01-04  9:50                                 ` Ben Dooks
2023-01-04 10:18                                 ` Conor Dooley
2023-01-04 10:18                                   ` Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 7/9] RISC-V: create a function based cache management interface Conor Dooley
2023-01-03 21:03                               ` Conor Dooley
2023-01-03 21:04                             ` [RFC v5.1 8/9] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley
2023-01-03 21:04                               ` Conor Dooley
2023-01-03 21:04                             ` [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Conor Dooley
2023-01-03 21:04                               ` Conor Dooley
2023-01-03 21:25                               ` Palmer Dabbelt
2023-01-03 21:25                                 ` Palmer Dabbelt
2023-01-03 21:28                               ` Arnd Bergmann
2023-01-03 21:28                                 ` Arnd Bergmann
2023-01-04  0:00                                 ` Conor Dooley
2023-01-04  0:00                                   ` Conor Dooley
2023-01-04  8:17                                   ` Arnd Bergmann
2023-01-04  8:17                                     ` Arnd Bergmann
2023-01-04  9:23                                     ` Conor Dooley
2023-01-04  9:23                                       ` Conor Dooley
2023-01-04 10:19                                       ` Arnd Bergmann
2023-01-04 10:19                                         ` Arnd Bergmann
2023-01-04 11:56                                         ` Conor Dooley
2023-01-04 11:56                                           ` Conor Dooley
2023-01-04 12:18                                           ` Arnd Bergmann
2023-01-04 12:18                                             ` Arnd Bergmann
2023-01-04 13:20                                             ` Conor Dooley
2023-01-04 13:20                                               ` Conor Dooley
2023-01-04 14:15                                               ` Arnd Bergmann
2023-01-04 14:15                                                 ` Arnd Bergmann
2023-01-04  9:45                               ` Ben Dooks
2023-01-04  9:45                                 ` Ben Dooks
2023-01-04  9:57                                 ` Conor Dooley
2023-01-04  9:57                                   ` Conor Dooley
2022-12-17 21:35   ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley
2022-12-17 21:35     ` Conor Dooley
2022-12-28  3:16   ` Samuel Holland
2022-12-28  3:16     ` Samuel Holland

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