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From: Michael Walle <michael@walle.cc>
To: jszhang@kernel.org
Cc: aou@eecs.berkeley.edu, conor@kernel.org,
	devicetree@vger.kernel.org, gregkh@linuxfoundation.org,
	ilpo.jarvinen@linux.intel.com, jirislaby@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
	palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org,
	Michael Walle <michael@walle.cc>
Subject: Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree
Date: Wed,  4 Jan 2023 09:32:04 +0100	[thread overview]
Message-ID: <20230104083204.1865526-1-michael@walle.cc> (raw)
In-Reply-To: <20221127132448.4034-7-jszhang@kernel.org>

Hi,

> +		uart0: serial@30002000 {

According to the reference manual of the bl808, this is uart3. Can we also
use that name here?

> +			compatible = "bouffalolab,bl808-uart";
> +			reg = <0x30002000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&xtal>;

This is a shortcut and is likely to change in the future. The xtal
isn't really connected to the uart block, but instead there is a
clock mux and clock gate in between.

> +			status = "disabled";
> +		};

Thanks,
-michael

WARNING: multiple messages have this Message-ID (diff)
From: Michael Walle <michael@walle.cc>
To: jszhang@kernel.org
Cc: aou@eecs.berkeley.edu, conor@kernel.org,
	devicetree@vger.kernel.org, gregkh@linuxfoundation.org,
	ilpo.jarvinen@linux.intel.com, jirislaby@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
	palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org,
	Michael Walle <michael@walle.cc>
Subject: Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree
Date: Wed,  4 Jan 2023 09:32:04 +0100	[thread overview]
Message-ID: <20230104083204.1865526-1-michael@walle.cc> (raw)
In-Reply-To: <20221127132448.4034-7-jszhang@kernel.org>

Hi,

> +		uart0: serial@30002000 {

According to the reference manual of the bl808, this is uart3. Can we also
use that name here?

> +			compatible = "bouffalolab,bl808-uart";
> +			reg = <0x30002000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&xtal>;

This is a shortcut and is likely to change in the future. The xtal
isn't really connected to the uart block, but instead there is a
clock mux and clock gate in between.

> +			status = "disabled";
> +		};

Thanks,
-michael

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2023-01-04  8:32 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-27 13:24 [PATCH v2 0/9] riscv: add Bouffalolab bl808 support Jisheng Zhang
2022-11-27 13:24 ` Jisheng Zhang
2022-11-27 13:24 ` [PATCH v2 1/9] dt-bindings: serial: add documentation for Bouffalolab UART Driver Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-30  5:45   ` Samuel Holland
2022-11-30  5:45     ` Samuel Holland
2022-12-01 11:02   ` Krzysztof Kozlowski
2022-12-01 11:02     ` Krzysztof Kozlowski
2022-11-27 13:24 ` [PATCH v2 2/9] serial: bflb_uart: add " Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-28  6:10   ` Jiri Slaby
2022-11-28  6:10     ` Jiri Slaby
2022-11-28 14:21     ` Jisheng Zhang
2022-11-28 14:21       ` Jisheng Zhang
2022-11-28 16:01       ` Ilpo Järvinen
2022-11-28 16:01         ` Ilpo Järvinen
2022-11-28 23:20         ` Jisheng Zhang
2022-11-28 23:20           ` Jisheng Zhang
2022-11-29  6:32           ` Jiri Slaby
2022-11-29  6:32             ` Jiri Slaby
2022-12-05 20:03   ` kernel test robot
2022-12-05 20:03     ` kernel test robot
2022-11-27 13:24 ` [PATCH v2 3/9] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-30  6:48   ` Samuel Holland
2022-11-30  6:48     ` Samuel Holland
2022-11-27 13:24 ` [PATCH v2 4/9] dt-bindings: vendor-prefixes: add bouffalolab Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 17:23   ` Conor Dooley
2022-11-27 17:23     ` Conor Dooley
2022-12-01 11:03   ` Krzysztof Kozlowski
2022-12-01 11:03     ` Krzysztof Kozlowski
2022-11-27 13:24 ` [PATCH v2 5/9] dt-bindings: riscv: Add bouffalolab bl808 board compatibles Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 16:25   ` Rob Herring
2022-11-27 16:25     ` Rob Herring
2022-11-27 17:29   ` Conor Dooley
2022-11-27 17:29     ` Conor Dooley
2022-12-01 11:05   ` Krzysztof Kozlowski
2022-12-01 11:05     ` Krzysztof Kozlowski
2022-12-01 11:14     ` Conor Dooley
2022-12-01 11:14       ` Conor Dooley
2022-12-01 11:41       ` Krzysztof Kozlowski
2022-12-01 11:41         ` Krzysztof Kozlowski
2022-11-27 13:24 ` [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 17:21   ` Conor Dooley
2022-11-27 17:21     ` Conor Dooley
2022-11-28  9:52     ` Icenowy Zheng
2022-11-28  9:52       ` Icenowy Zheng
2022-11-28 14:52       ` Conor Dooley
2022-11-28 14:52         ` Conor Dooley
2022-11-30  7:21   ` Samuel Holland
2022-11-30  7:21     ` Samuel Holland
2022-12-05  8:17     ` Icenowy Zheng
2022-12-05  8:17       ` Icenowy Zheng
2022-12-05 10:29       ` Conor Dooley
2022-12-05 10:29         ` Conor Dooley
2023-01-04  8:32   ` Michael Walle [this message]
2023-01-04  8:32     ` Michael Walle
2022-11-27 13:24 ` [PATCH v2 7/9] riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 17:32   ` Conor Dooley
2022-11-27 17:32     ` Conor Dooley
2022-11-30  7:25   ` Samuel Holland
2022-11-30  7:25     ` Samuel Holland
2022-12-05  8:15     ` Icenowy Zheng
2022-12-05  8:15       ` Icenowy Zheng
2022-11-27 13:24 ` [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 17:35   ` Conor Dooley
2022-11-27 17:35     ` Conor Dooley
2022-11-27 17:36     ` Conor Dooley
2022-11-27 17:36       ` Conor Dooley
2022-11-28 14:30       ` Jisheng Zhang
2022-11-28 14:30         ` Jisheng Zhang
2022-11-28 14:34         ` Jisheng Zhang
2022-11-28 14:34           ` Jisheng Zhang
2022-11-28 14:50         ` Conor Dooley
2022-11-28 14:50           ` Conor Dooley
2022-11-30  7:27   ` Samuel Holland
2022-11-30  7:27     ` Samuel Holland
2022-11-27 13:24 ` [PATCH v2 9/9] riscv: defconfig: enable BOUFFALOLAB SoC Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 17:36   ` Conor Dooley
2022-11-27 17:36     ` Conor Dooley
2022-12-02 17:54 ` [PATCH v2 0/9] riscv: add Bouffalolab bl808 support Palmer Dabbelt
2022-12-02 17:54   ` Palmer Dabbelt

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