From: Conor Dooley <conor.dooley@microchip.com> To: Icenowy Zheng <uwu@icenowy.me> Cc: "Conor Dooley" <conor@kernel.org>, "Jisheng Zhang" <jszhang@kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Jiri Slaby" <jirislaby@kernel.org>, "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree Date: Mon, 28 Nov 2022 14:52:32 +0000 [thread overview] Message-ID: <Y4TLMLKDG5SVNoJ7@wendy> (raw) In-Reply-To: <3ad94a3fc3558da2da80d238d26f29e2c42db5c1.camel@icenowy.me> On Mon, Nov 28, 2022 at 05:52:51PM +0800, Icenowy Zheng wrote: > 在 2022-11-27星期日的 17:21 +0000,Conor Dooley写道: > > +CC Icenowy > > > > On Sun, Nov 27, 2022 at 09:24:45PM +0800, Jisheng Zhang wrote: > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > > --- > > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > > + plic: interrupt-controller@e0000000 { > > > + compatible = "thead,c900-plic"; > > > > Hmm, @Icenowy - should this use your new open-c906-plic compatible > > from > > 20221121041757.418645-4-uwu@icenowy.me ? > > I am against using openc906-plic. > > Maybe I will add "thead,c906-plic", "thead,c900-plic" as an valid > compatible, as there seems to be few options related to PLIC/CLINT for > C906/C910 (at least as the open document of them say). You two know this a lot better than I do, I'll leave it up to you two to sort out :) Either way, we need something changed here to satisfy the bindings. > > As is, dtbs_check gives a: > > bl808-sipeed-m1s-dock.dtb: interrupt-controller@e0000000: compatible: > > 'oneOf' conditional failed, one must be fixed: > > ['thead,c900-plic'] is too short > > > > > + reg = <0xe0000000 0x4000000>; > > > + interrupts-extended = <&cpu0_intc > > > 0xffffffff>, > > > + <&cpu0_intc 9>; > > > + interrupt-controller; > > > + #address-cells = <0>; > > > + #interrupt-cells = <2>; > > > + riscv,ndev = <64>; > > > + }; > > > + }; > > > +};
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com> To: Icenowy Zheng <uwu@icenowy.me> Cc: "Conor Dooley" <conor@kernel.org>, "Jisheng Zhang" <jszhang@kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Jiri Slaby" <jirislaby@kernel.org>, "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree Date: Mon, 28 Nov 2022 14:52:32 +0000 [thread overview] Message-ID: <Y4TLMLKDG5SVNoJ7@wendy> (raw) In-Reply-To: <3ad94a3fc3558da2da80d238d26f29e2c42db5c1.camel@icenowy.me> On Mon, Nov 28, 2022 at 05:52:51PM +0800, Icenowy Zheng wrote: > 在 2022-11-27星期日的 17:21 +0000,Conor Dooley写道: > > +CC Icenowy > > > > On Sun, Nov 27, 2022 at 09:24:45PM +0800, Jisheng Zhang wrote: > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > > --- > > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > > + plic: interrupt-controller@e0000000 { > > > + compatible = "thead,c900-plic"; > > > > Hmm, @Icenowy - should this use your new open-c906-plic compatible > > from > > 20221121041757.418645-4-uwu@icenowy.me ? > > I am against using openc906-plic. > > Maybe I will add "thead,c906-plic", "thead,c900-plic" as an valid > compatible, as there seems to be few options related to PLIC/CLINT for > C906/C910 (at least as the open document of them say). You two know this a lot better than I do, I'll leave it up to you two to sort out :) Either way, we need something changed here to satisfy the bindings. > > As is, dtbs_check gives a: > > bl808-sipeed-m1s-dock.dtb: interrupt-controller@e0000000: compatible: > > 'oneOf' conditional failed, one must be fixed: > > ['thead,c900-plic'] is too short > > > > > + reg = <0xe0000000 0x4000000>; > > > + interrupts-extended = <&cpu0_intc > > > 0xffffffff>, > > > + <&cpu0_intc 9>; > > > + interrupt-controller; > > > + #address-cells = <0>; > > > + #interrupt-cells = <2>; > > > + riscv,ndev = <64>; > > > + }; > > > + }; > > > +}; _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-28 14:52 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-27 13:24 [PATCH v2 0/9] riscv: add Bouffalolab bl808 support Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 13:24 ` [PATCH v2 1/9] dt-bindings: serial: add documentation for Bouffalolab UART Driver Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-30 5:45 ` Samuel Holland 2022-11-30 5:45 ` Samuel Holland 2022-12-01 11:02 ` Krzysztof Kozlowski 2022-12-01 11:02 ` Krzysztof Kozlowski 2022-11-27 13:24 ` [PATCH v2 2/9] serial: bflb_uart: add " Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-28 6:10 ` Jiri Slaby 2022-11-28 6:10 ` Jiri Slaby 2022-11-28 14:21 ` Jisheng Zhang 2022-11-28 14:21 ` Jisheng Zhang 2022-11-28 16:01 ` Ilpo Järvinen 2022-11-28 16:01 ` Ilpo Järvinen 2022-11-28 23:20 ` Jisheng Zhang 2022-11-28 23:20 ` Jisheng Zhang 2022-11-29 6:32 ` Jiri Slaby 2022-11-29 6:32 ` Jiri Slaby 2022-12-05 20:03 ` kernel test robot 2022-12-05 20:03 ` kernel test robot 2022-11-27 13:24 ` [PATCH v2 3/9] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-30 6:48 ` Samuel Holland 2022-11-30 6:48 ` Samuel Holland 2022-11-27 13:24 ` [PATCH v2 4/9] dt-bindings: vendor-prefixes: add bouffalolab Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 17:23 ` Conor Dooley 2022-11-27 17:23 ` Conor Dooley 2022-12-01 11:03 ` Krzysztof Kozlowski 2022-12-01 11:03 ` Krzysztof Kozlowski 2022-11-27 13:24 ` [PATCH v2 5/9] dt-bindings: riscv: Add bouffalolab bl808 board compatibles Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 16:25 ` Rob Herring 2022-11-27 16:25 ` Rob Herring 2022-11-27 17:29 ` Conor Dooley 2022-11-27 17:29 ` Conor Dooley 2022-12-01 11:05 ` Krzysztof Kozlowski 2022-12-01 11:05 ` Krzysztof Kozlowski 2022-12-01 11:14 ` Conor Dooley 2022-12-01 11:14 ` Conor Dooley 2022-12-01 11:41 ` Krzysztof Kozlowski 2022-12-01 11:41 ` Krzysztof Kozlowski 2022-11-27 13:24 ` [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 17:21 ` Conor Dooley 2022-11-27 17:21 ` Conor Dooley 2022-11-28 9:52 ` Icenowy Zheng 2022-11-28 9:52 ` Icenowy Zheng 2022-11-28 14:52 ` Conor Dooley [this message] 2022-11-28 14:52 ` Conor Dooley 2022-11-30 7:21 ` Samuel Holland 2022-11-30 7:21 ` Samuel Holland 2022-12-05 8:17 ` Icenowy Zheng 2022-12-05 8:17 ` Icenowy Zheng 2022-12-05 10:29 ` Conor Dooley 2022-12-05 10:29 ` Conor Dooley 2023-01-04 8:32 ` Michael Walle 2023-01-04 8:32 ` Michael Walle 2022-11-27 13:24 ` [PATCH v2 7/9] riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 17:32 ` Conor Dooley 2022-11-27 17:32 ` Conor Dooley 2022-11-30 7:25 ` Samuel Holland 2022-11-30 7:25 ` Samuel Holland 2022-12-05 8:15 ` Icenowy Zheng 2022-12-05 8:15 ` Icenowy Zheng 2022-11-27 13:24 ` [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 17:35 ` Conor Dooley 2022-11-27 17:35 ` Conor Dooley 2022-11-27 17:36 ` Conor Dooley 2022-11-27 17:36 ` Conor Dooley 2022-11-28 14:30 ` Jisheng Zhang 2022-11-28 14:30 ` Jisheng Zhang 2022-11-28 14:34 ` Jisheng Zhang 2022-11-28 14:34 ` Jisheng Zhang 2022-11-28 14:50 ` Conor Dooley 2022-11-28 14:50 ` Conor Dooley 2022-11-30 7:27 ` Samuel Holland 2022-11-30 7:27 ` Samuel Holland 2022-11-27 13:24 ` [PATCH v2 9/9] riscv: defconfig: enable BOUFFALOLAB SoC Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 17:36 ` Conor Dooley 2022-11-27 17:36 ` Conor Dooley 2022-12-02 17:54 ` [PATCH v2 0/9] riscv: add Bouffalolab bl808 support Palmer Dabbelt 2022-12-02 17:54 ` Palmer Dabbelt
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=Y4TLMLKDG5SVNoJ7@wendy \ --to=conor.dooley@microchip.com \ --cc=aou@eecs.berkeley.edu \ --cc=conor@kernel.org \ --cc=devicetree@vger.kernel.org \ --cc=gregkh@linuxfoundation.org \ --cc=ilpo.jarvinen@linux.intel.com \ --cc=jirislaby@kernel.org \ --cc=jszhang@kernel.org \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=linux-serial@vger.kernel.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=robh+dt@kernel.org \ --cc=uwu@icenowy.me \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.