From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sergey Matyukevich <sergey.matyukevich@syntacore.com>, Will Deacon <will@kernel.org> Subject: [PATCH v3 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Date: Fri, 27 Jan 2023 10:25:54 -0800 [thread overview] Message-ID: <20230127182558.2416400-11-atishp@rivosinc.com> (raw) In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> Any guest must not get access to any hpmcounter including cycle/instret without any checks. We achieve that by disabling all the bits except TM bit in hcounteren. However, instret and cycle access for guest user space can be enabled upon explicit request (via ONE REG) or on first trap from VU mode to maintain ABI requirement in the future. This patch doesn't support that as ONE REG interface is not settled yet. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/kvm/main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 58c5489..c5d400f 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -49,7 +49,8 @@ int kvm_arch_hardware_enable(void) hideleg |= (1UL << IRQ_VS_EXT); csr_write(CSR_HIDELEG, hideleg); - csr_write(CSR_HCOUNTEREN, -1UL); + /* VS should access only the time counter directly. Everything else should trap */ + csr_write(CSR_HCOUNTEREN, 0x02); csr_write(CSR_HVIP, 0); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sergey Matyukevich <sergey.matyukevich@syntacore.com>, Will Deacon <will@kernel.org> Subject: [PATCH v3 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Date: Fri, 27 Jan 2023 10:25:54 -0800 [thread overview] Message-ID: <20230127182558.2416400-11-atishp@rivosinc.com> (raw) In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> Any guest must not get access to any hpmcounter including cycle/instret without any checks. We achieve that by disabling all the bits except TM bit in hcounteren. However, instret and cycle access for guest user space can be enabled upon explicit request (via ONE REG) or on first trap from VU mode to maintain ABI requirement in the future. This patch doesn't support that as ONE REG interface is not settled yet. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/kvm/main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 58c5489..c5d400f 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -49,7 +49,8 @@ int kvm_arch_hardware_enable(void) hideleg |= (1UL << IRQ_VS_EXT); csr_write(CSR_HIDELEG, hideleg); - csr_write(CSR_HCOUNTEREN, -1UL); + /* VS should access only the time counter directly. Everything else should trap */ + csr_write(CSR_HCOUNTEREN, 0x02); csr_write(CSR_HVIP, 0); -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-27 18:26 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-27 18:25 [PATCH v3 00/14] KVM perf support Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-27 18:25 ` [PATCH v3 01/14] perf: RISC-V: Define helper functions expose hpm counter width and count Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-28 14:44 ` Anup Patel 2023-01-28 14:44 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 02/14] perf: RISC-V: Improve privilege mode filtering for perf Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-28 14:47 ` Anup Patel 2023-01-28 14:47 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 03/14] RISC-V: Improve SBI PMU extension related definitions Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-27 22:53 ` Conor Dooley 2023-01-27 22:53 ` Conor Dooley 2023-01-31 19:30 ` Atish Patra 2023-01-31 19:30 ` Atish Patra 2023-01-27 18:25 ` [PATCH v3 04/14] RISC-V: KVM: Define a probe function for SBI extension data structures Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-28 14:50 ` Anup Patel 2023-01-28 14:50 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 05/14] RISC-V: KVM: Return correct code for hsm stop function Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-28 14:52 ` Anup Patel 2023-01-28 14:52 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 06/14] RISC-V: KVM: Modify SBI extension handler to return SBI error code Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-29 12:16 ` Anup Patel 2023-01-29 12:16 ` Anup Patel 2023-01-31 20:38 ` Atish Patra 2023-01-31 20:38 ` Atish Patra 2023-01-27 18:25 ` [PATCH v3 07/14] RISC-V: KVM: Add skeleton support for perf Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-29 12:30 ` Anup Patel 2023-01-29 12:30 ` Anup Patel 2023-01-31 22:35 ` Atish Patra 2023-01-31 22:35 ` Atish Patra 2023-02-01 3:48 ` Anup Patel 2023-02-01 3:48 ` Anup Patel 2023-02-01 8:41 ` Atish Patra 2023-02-01 8:41 ` Atish Patra 2023-02-01 9:05 ` Anup Patel 2023-02-01 9:05 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 08/14] RISC-V: KVM: Add SBI PMU extension support Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-29 12:34 ` Anup Patel 2023-01-29 12:34 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 09/14] RISC-V: KVM: Make PMU functionality depend on Sscofpmf Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-29 12:35 ` Anup Patel 2023-01-29 12:35 ` Anup Patel 2023-01-27 18:25 ` Atish Patra [this message] 2023-01-27 18:25 ` [PATCH v3 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Atish Patra 2023-01-29 12:37 ` Anup Patel 2023-01-29 12:37 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 11/14] RISC-V: KVM: Implement trap & emulate for hpmcounters Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-29 12:44 ` Anup Patel 2023-01-29 12:44 ` Anup Patel 2023-01-31 22:46 ` Atish Patra 2023-01-31 22:46 ` Atish Patra 2023-02-01 8:58 ` Atish Patra 2023-02-01 8:58 ` Atish Patra 2023-02-01 9:09 ` Anup Patel 2023-02-01 9:09 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 12/14] RISC-V: KVM: Implement perf support without sampling Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-30 15:40 ` Anup Patel 2023-01-30 15:40 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 13/14] RISC-V: KVM: Support firmware events Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-30 15:47 ` Anup Patel 2023-01-30 15:47 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 14/14] RISC-V: KVM: Increment firmware pmu events Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-30 15:48 ` Anup Patel 2023-01-30 15:48 ` Anup Patel
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