From: Anup Patel <anup@brainfault.org> To: Atish Patra <atishp@rivosinc.com> Cc: linux-kernel@vger.kernel.org, Andrew Jones <ajones@ventanamicro.com>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sergey Matyukevich <sergey.matyukevich@syntacore.com>, Will Deacon <will@kernel.org> Subject: Re: [PATCH v3 14/14] RISC-V: KVM: Increment firmware pmu events Date: Mon, 30 Jan 2023 21:18:10 +0530 [thread overview] Message-ID: <CAAhSdy1C1wKDBwRbyx=i63_AyGBsgN881_E-fxR=8qqYgwUtGw@mail.gmail.com> (raw) In-Reply-To: <20230127182558.2416400-15-atishp@rivosinc.com> On Fri, Jan 27, 2023 at 11:56 PM Atish Patra <atishp@rivosinc.com> wrote: > > KVM supports firmware events now. Invoke the firmware event increment > function from appropriate places. > > Signed-off-by: Atish Patra <atishp@rivosinc.com> Looks good to me. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > arch/riscv/kvm/tlb.c | 4 ++++ > arch/riscv/kvm/vcpu_sbi_replace.c | 7 +++++++ > 2 files changed, 11 insertions(+) > > diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c > index 309d79b..b797f7c 100644 > --- a/arch/riscv/kvm/tlb.c > +++ b/arch/riscv/kvm/tlb.c > @@ -181,6 +181,7 @@ void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu) > > void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu) > { > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_RCVD); > local_flush_icache_all(); > } > > @@ -264,15 +265,18 @@ void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu) > d.addr, d.size, d.order); > break; > case KVM_RISCV_HFENCE_VVMA_ASID_GVA: > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD); > kvm_riscv_local_hfence_vvma_asid_gva( > READ_ONCE(v->vmid), d.asid, > d.addr, d.size, d.order); > break; > case KVM_RISCV_HFENCE_VVMA_ASID_ALL: > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD); > kvm_riscv_local_hfence_vvma_asid_all( > READ_ONCE(v->vmid), d.asid); > break; > case KVM_RISCV_HFENCE_VVMA_GVA: > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_RCVD); > kvm_riscv_local_hfence_vvma_gva( > READ_ONCE(v->vmid), > d.addr, d.size, d.order); > diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c > index abeb55f..71a671e 100644 > --- a/arch/riscv/kvm/vcpu_sbi_replace.c > +++ b/arch/riscv/kvm/vcpu_sbi_replace.c > @@ -11,6 +11,7 @@ > #include <linux/kvm_host.h> > #include <asm/sbi.h> > #include <asm/kvm_vcpu_timer.h> > +#include <asm/kvm_vcpu_pmu.h> > #include <asm/kvm_vcpu_sbi.h> > > static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > @@ -25,6 +26,7 @@ static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > return 0; > } > > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_SET_TIMER); > #if __riscv_xlen == 32 > next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0; > #else > @@ -57,6 +59,7 @@ static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > return 0; > } > > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_IPI_SENT); > kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > if (hbase != -1UL) { > if (tmp->vcpu_id < hbase) > @@ -67,6 +70,7 @@ static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > ret = kvm_riscv_vcpu_set_interrupt(tmp, IRQ_VS_SOFT); > if (ret < 0) > break; > + kvm_riscv_vcpu_pmu_incr_fw(tmp, SBI_PMU_FW_IPI_RECVD); > } > > return ret; > @@ -90,6 +94,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run > switch (funcid) { > case SBI_EXT_RFENCE_REMOTE_FENCE_I: > kvm_riscv_fence_i(vcpu->kvm, hbase, hmask); > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_SENT); > break; > case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA: > if (cp->a2 == 0 && cp->a3 == 0) > @@ -97,6 +102,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run > else > kvm_riscv_hfence_vvma_gva(vcpu->kvm, hbase, hmask, > cp->a2, cp->a3, PAGE_SHIFT); > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_SENT); > break; > case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID: > if (cp->a2 == 0 && cp->a3 == 0) > @@ -107,6 +113,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run > hbase, hmask, > cp->a2, cp->a3, > PAGE_SHIFT, cp->a4); > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_SENT); > break; > case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA: > case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID: > -- > 2.25.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org> To: Atish Patra <atishp@rivosinc.com> Cc: linux-kernel@vger.kernel.org, Andrew Jones <ajones@ventanamicro.com>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sergey Matyukevich <sergey.matyukevich@syntacore.com>, Will Deacon <will@kernel.org> Subject: Re: [PATCH v3 14/14] RISC-V: KVM: Increment firmware pmu events Date: Mon, 30 Jan 2023 21:18:10 +0530 [thread overview] Message-ID: <CAAhSdy1C1wKDBwRbyx=i63_AyGBsgN881_E-fxR=8qqYgwUtGw@mail.gmail.com> (raw) In-Reply-To: <20230127182558.2416400-15-atishp@rivosinc.com> On Fri, Jan 27, 2023 at 11:56 PM Atish Patra <atishp@rivosinc.com> wrote: > > KVM supports firmware events now. Invoke the firmware event increment > function from appropriate places. > > Signed-off-by: Atish Patra <atishp@rivosinc.com> Looks good to me. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > arch/riscv/kvm/tlb.c | 4 ++++ > arch/riscv/kvm/vcpu_sbi_replace.c | 7 +++++++ > 2 files changed, 11 insertions(+) > > diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c > index 309d79b..b797f7c 100644 > --- a/arch/riscv/kvm/tlb.c > +++ b/arch/riscv/kvm/tlb.c > @@ -181,6 +181,7 @@ void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu) > > void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu) > { > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_RCVD); > local_flush_icache_all(); > } > > @@ -264,15 +265,18 @@ void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu) > d.addr, d.size, d.order); > break; > case KVM_RISCV_HFENCE_VVMA_ASID_GVA: > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD); > kvm_riscv_local_hfence_vvma_asid_gva( > READ_ONCE(v->vmid), d.asid, > d.addr, d.size, d.order); > break; > case KVM_RISCV_HFENCE_VVMA_ASID_ALL: > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD); > kvm_riscv_local_hfence_vvma_asid_all( > READ_ONCE(v->vmid), d.asid); > break; > case KVM_RISCV_HFENCE_VVMA_GVA: > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_RCVD); > kvm_riscv_local_hfence_vvma_gva( > READ_ONCE(v->vmid), > d.addr, d.size, d.order); > diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c > index abeb55f..71a671e 100644 > --- a/arch/riscv/kvm/vcpu_sbi_replace.c > +++ b/arch/riscv/kvm/vcpu_sbi_replace.c > @@ -11,6 +11,7 @@ > #include <linux/kvm_host.h> > #include <asm/sbi.h> > #include <asm/kvm_vcpu_timer.h> > +#include <asm/kvm_vcpu_pmu.h> > #include <asm/kvm_vcpu_sbi.h> > > static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > @@ -25,6 +26,7 @@ static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > return 0; > } > > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_SET_TIMER); > #if __riscv_xlen == 32 > next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0; > #else > @@ -57,6 +59,7 @@ static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > return 0; > } > > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_IPI_SENT); > kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > if (hbase != -1UL) { > if (tmp->vcpu_id < hbase) > @@ -67,6 +70,7 @@ static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > ret = kvm_riscv_vcpu_set_interrupt(tmp, IRQ_VS_SOFT); > if (ret < 0) > break; > + kvm_riscv_vcpu_pmu_incr_fw(tmp, SBI_PMU_FW_IPI_RECVD); > } > > return ret; > @@ -90,6 +94,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run > switch (funcid) { > case SBI_EXT_RFENCE_REMOTE_FENCE_I: > kvm_riscv_fence_i(vcpu->kvm, hbase, hmask); > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_SENT); > break; > case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA: > if (cp->a2 == 0 && cp->a3 == 0) > @@ -97,6 +102,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run > else > kvm_riscv_hfence_vvma_gva(vcpu->kvm, hbase, hmask, > cp->a2, cp->a3, PAGE_SHIFT); > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_SENT); > break; > case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID: > if (cp->a2 == 0 && cp->a3 == 0) > @@ -107,6 +113,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run > hbase, hmask, > cp->a2, cp->a3, > PAGE_SHIFT, cp->a4); > + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_SENT); > break; > case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA: > case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID: > -- > 2.25.1 >
next prev parent reply other threads:[~2023-01-30 15:48 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-27 18:25 [PATCH v3 00/14] KVM perf support Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-27 18:25 ` [PATCH v3 01/14] perf: RISC-V: Define helper functions expose hpm counter width and count Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-28 14:44 ` Anup Patel 2023-01-28 14:44 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 02/14] perf: RISC-V: Improve privilege mode filtering for perf Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-28 14:47 ` Anup Patel 2023-01-28 14:47 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 03/14] RISC-V: Improve SBI PMU extension related definitions Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-27 22:53 ` Conor Dooley 2023-01-27 22:53 ` Conor Dooley 2023-01-31 19:30 ` Atish Patra 2023-01-31 19:30 ` Atish Patra 2023-01-27 18:25 ` [PATCH v3 04/14] RISC-V: KVM: Define a probe function for SBI extension data structures Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-28 14:50 ` Anup Patel 2023-01-28 14:50 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 05/14] RISC-V: KVM: Return correct code for hsm stop function Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-28 14:52 ` Anup Patel 2023-01-28 14:52 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 06/14] RISC-V: KVM: Modify SBI extension handler to return SBI error code Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-29 12:16 ` Anup Patel 2023-01-29 12:16 ` Anup Patel 2023-01-31 20:38 ` Atish Patra 2023-01-31 20:38 ` Atish Patra 2023-01-27 18:25 ` [PATCH v3 07/14] RISC-V: KVM: Add skeleton support for perf Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-29 12:30 ` Anup Patel 2023-01-29 12:30 ` Anup Patel 2023-01-31 22:35 ` Atish Patra 2023-01-31 22:35 ` Atish Patra 2023-02-01 3:48 ` Anup Patel 2023-02-01 3:48 ` Anup Patel 2023-02-01 8:41 ` Atish Patra 2023-02-01 8:41 ` Atish Patra 2023-02-01 9:05 ` Anup Patel 2023-02-01 9:05 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 08/14] RISC-V: KVM: Add SBI PMU extension support Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-29 12:34 ` Anup Patel 2023-01-29 12:34 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 09/14] RISC-V: KVM: Make PMU functionality depend on Sscofpmf Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-29 12:35 ` Anup Patel 2023-01-29 12:35 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-29 12:37 ` Anup Patel 2023-01-29 12:37 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 11/14] RISC-V: KVM: Implement trap & emulate for hpmcounters Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-29 12:44 ` Anup Patel 2023-01-29 12:44 ` Anup Patel 2023-01-31 22:46 ` Atish Patra 2023-01-31 22:46 ` Atish Patra 2023-02-01 8:58 ` Atish Patra 2023-02-01 8:58 ` Atish Patra 2023-02-01 9:09 ` Anup Patel 2023-02-01 9:09 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 12/14] RISC-V: KVM: Implement perf support without sampling Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-30 15:40 ` Anup Patel 2023-01-30 15:40 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 13/14] RISC-V: KVM: Support firmware events Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-30 15:47 ` Anup Patel 2023-01-30 15:47 ` Anup Patel 2023-01-27 18:25 ` [PATCH v3 14/14] RISC-V: KVM: Increment firmware pmu events Atish Patra 2023-01-27 18:25 ` Atish Patra 2023-01-30 15:48 ` Anup Patel [this message] 2023-01-30 15:48 ` Anup Patel
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