All of lore.kernel.org
 help / color / mirror / Atom feed
From: Conor Dooley <conor@kernel.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: linux-kernel@vger.kernel.org,
	Andrew Jones <ajones@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Mark Rutland <mark.rutland@arm.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Sergey Matyukevich <sergey.matyukevich@syntacore.com>,
	Will Deacon <will@kernel.org>
Subject: Re: [PATCH v3 03/14] RISC-V: Improve SBI PMU extension related definitions
Date: Fri, 27 Jan 2023 22:53:05 +0000	[thread overview]
Message-ID: <Y9RV0cOMld20EFBI@spud> (raw)
In-Reply-To: <20230127182558.2416400-4-atishp@rivosinc.com>

[-- Attachment #1: Type: text/plain, Size: 685 bytes --]

Yo Atish,

On Fri, Jan 27, 2023 at 10:25:47AM -0800, Atish Patra wrote:
> This patch fixes/improve few minor things in SBI PMU extension
> definition.
> 
> 1. Align all the firmware event names.

> @@ -171,7 +171,7 @@ enum sbi_pmu_fw_generic_events_t {
>  	SBI_PMU_FW_IPI_RECVD		= 7,
> -	SBI_PMU_FW_FENCE_I_RECVD	= 9,
> +	SBI_PMU_FW_FENCE_I_RCVD		= 9,
>  	SBI_PMU_FW_SFENCE_VMA_RCVD	= 11,

Alignment looks incomplete to me! Looks like you went from 2 RECVD and
1 RCVD to 2 RCVD and 1 RECVD! FWIW, the spec uses RECEIVED for all of
these:
https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc#114-event-firmware-events-type-15

Thanks,
Conor.


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: linux-kernel@vger.kernel.org,
	Andrew Jones <ajones@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Mark Rutland <mark.rutland@arm.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Sergey Matyukevich <sergey.matyukevich@syntacore.com>,
	Will Deacon <will@kernel.org>
Subject: Re: [PATCH v3 03/14] RISC-V: Improve SBI PMU extension related definitions
Date: Fri, 27 Jan 2023 22:53:05 +0000	[thread overview]
Message-ID: <Y9RV0cOMld20EFBI@spud> (raw)
In-Reply-To: <20230127182558.2416400-4-atishp@rivosinc.com>


[-- Attachment #1.1: Type: text/plain, Size: 685 bytes --]

Yo Atish,

On Fri, Jan 27, 2023 at 10:25:47AM -0800, Atish Patra wrote:
> This patch fixes/improve few minor things in SBI PMU extension
> definition.
> 
> 1. Align all the firmware event names.

> @@ -171,7 +171,7 @@ enum sbi_pmu_fw_generic_events_t {
>  	SBI_PMU_FW_IPI_RECVD		= 7,
> -	SBI_PMU_FW_FENCE_I_RECVD	= 9,
> +	SBI_PMU_FW_FENCE_I_RCVD		= 9,
>  	SBI_PMU_FW_SFENCE_VMA_RCVD	= 11,

Alignment looks incomplete to me! Looks like you went from 2 RECVD and
1 RCVD to 2 RCVD and 1 RECVD! FWIW, the spec uses RECEIVED for all of
these:
https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc#114-event-firmware-events-type-15

Thanks,
Conor.


[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2023-01-27 22:53 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-27 18:25 [PATCH v3 00/14] KVM perf support Atish Patra
2023-01-27 18:25 ` Atish Patra
2023-01-27 18:25 ` [PATCH v3 01/14] perf: RISC-V: Define helper functions expose hpm counter width and count Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-28 14:44   ` Anup Patel
2023-01-28 14:44     ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 02/14] perf: RISC-V: Improve privilege mode filtering for perf Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-28 14:47   ` Anup Patel
2023-01-28 14:47     ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 03/14] RISC-V: Improve SBI PMU extension related definitions Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-27 22:53   ` Conor Dooley [this message]
2023-01-27 22:53     ` Conor Dooley
2023-01-31 19:30     ` Atish Patra
2023-01-31 19:30       ` Atish Patra
2023-01-27 18:25 ` [PATCH v3 04/14] RISC-V: KVM: Define a probe function for SBI extension data structures Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-28 14:50   ` Anup Patel
2023-01-28 14:50     ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 05/14] RISC-V: KVM: Return correct code for hsm stop function Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-28 14:52   ` Anup Patel
2023-01-28 14:52     ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 06/14] RISC-V: KVM: Modify SBI extension handler to return SBI error code Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-29 12:16   ` Anup Patel
2023-01-29 12:16     ` Anup Patel
2023-01-31 20:38     ` Atish Patra
2023-01-31 20:38       ` Atish Patra
2023-01-27 18:25 ` [PATCH v3 07/14] RISC-V: KVM: Add skeleton support for perf Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-29 12:30   ` Anup Patel
2023-01-29 12:30     ` Anup Patel
2023-01-31 22:35     ` Atish Patra
2023-01-31 22:35       ` Atish Patra
2023-02-01  3:48       ` Anup Patel
2023-02-01  3:48         ` Anup Patel
2023-02-01  8:41         ` Atish Patra
2023-02-01  8:41           ` Atish Patra
2023-02-01  9:05           ` Anup Patel
2023-02-01  9:05             ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 08/14] RISC-V: KVM: Add SBI PMU extension support Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-29 12:34   ` Anup Patel
2023-01-29 12:34     ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 09/14] RISC-V: KVM: Make PMU functionality depend on Sscofpmf Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-29 12:35   ` Anup Patel
2023-01-29 12:35     ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-29 12:37   ` Anup Patel
2023-01-29 12:37     ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 11/14] RISC-V: KVM: Implement trap & emulate for hpmcounters Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-29 12:44   ` Anup Patel
2023-01-29 12:44     ` Anup Patel
2023-01-31 22:46     ` Atish Patra
2023-01-31 22:46       ` Atish Patra
2023-02-01  8:58       ` Atish Patra
2023-02-01  8:58         ` Atish Patra
2023-02-01  9:09         ` Anup Patel
2023-02-01  9:09           ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 12/14] RISC-V: KVM: Implement perf support without sampling Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-30 15:40   ` Anup Patel
2023-01-30 15:40     ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 13/14] RISC-V: KVM: Support firmware events Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-30 15:47   ` Anup Patel
2023-01-30 15:47     ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 14/14] RISC-V: KVM: Increment firmware pmu events Atish Patra
2023-01-27 18:25   ` Atish Patra
2023-01-30 15:48   ` Anup Patel
2023-01-30 15:48     ` Anup Patel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=Y9RV0cOMld20EFBI@spud \
    --to=conor@kernel.org \
    --cc=ajones@ventanamicro.com \
    --cc=anup@brainfault.org \
    --cc=atishp@atishpatra.org \
    --cc=atishp@rivosinc.com \
    --cc=guoren@kernel.org \
    --cc=heiko@sntech.de \
    --cc=kvm-riscv@lists.infradead.org \
    --cc=kvm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=mark.rutland@arm.com \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=sergey.matyukevich@syntacore.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.