From: Hal Feng <hal.feng@starfivetech.com> To: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org> Cc: Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, "Daniel Lezcano" <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Hal Feng <hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v5 12/21] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator Date: Sat, 11 Mar 2023 17:07:24 +0800 [thread overview] Message-ID: <20230311090733.56918-13-hal.feng@starfivetech.com> (raw) In-Reply-To: <20230311090733.56918-1-hal.feng@starfivetech.com> From: Emil Renner Berthing <kernel@esmil.dk> Add bindings for the always-on clock and reset generator (AONCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- .../clock/starfive,jh7110-aoncrg.yaml | 107 ++++++++++++++++++ .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++ .../dt-bindings/reset/starfive,jh7110-crg.h | 12 ++ 3 files changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml new file mode 100644 index 000000000000..923680a44aef --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Always-On Clock and Reset Generator + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + +properties: + compatible: + const: starfive,jh7110-aoncrg + + reg: + maxItems: 1 + + clocks: + oneOf: + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference or GMAC0 RGMII RX + - description: STG AXI/AHB + - description: APB Bus + - description: GMAC0 GTX + + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference or GMAC0 RGMII RX + - description: STG AXI/AHB or GMAC0 RGMII RX + - description: APB Bus or STG AXI/AHB + - description: GMAC0 GTX or APB Bus + - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX + + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference + - description: GMAC0 RGMII RX + - description: STG AXI/AHB + - description: APB Bus + - description: GMAC0 GTX + - description: RTC Oscillator (32.768 kHz) + + clock-names: + oneOf: + - minItems: 5 + items: + - const: osc + - enum: + - gmac0_rmii_refin + - gmac0_rgmii_rxin + - const: stg_axiahb + - const: apb_bus + - const: gmac0_gtxclk + - const: rtc_osc + + - minItems: 6 + items: + - const: osc + - const: gmac0_rmii_refin + - const: gmac0_rgmii_rxin + - const: stg_axiahb + - const: apb_bus + - const: gmac0_gtxclk + - const: rtc_osc + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + + clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x17000000 0x10000>; + clocks = <&osc>, <&gmac0_rmii_refin>, + <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, + <&rtc_osc>; + clock-names = "osc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus", "gmac0_gtxclk", + "rtc_osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index fdd1852e34cc..06257bfd9ac1 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -200,4 +200,22 @@ #define JH7110_SYSCLK_END 190 +/* AONCRG clocks */ +#define JH7110_AONCLK_OSC_DIV4 0 +#define JH7110_AONCLK_APB_FUNC 1 +#define JH7110_AONCLK_GMAC0_AHB 2 +#define JH7110_AONCLK_GMAC0_AXI 3 +#define JH7110_AONCLK_GMAC0_RMII_RTX 4 +#define JH7110_AONCLK_GMAC0_TX 5 +#define JH7110_AONCLK_GMAC0_TX_INV 6 +#define JH7110_AONCLK_GMAC0_RX 7 +#define JH7110_AONCLK_GMAC0_RX_INV 8 +#define JH7110_AONCLK_OTPC_APB 9 +#define JH7110_AONCLK_RTC_APB 10 +#define JH7110_AONCLK_RTC_INTERNAL 11 +#define JH7110_AONCLK_RTC_32K 12 +#define JH7110_AONCLK_RTC_CAL 13 + +#define JH7110_AONCLK_END 14 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h index b88216a4fe40..d78e38690ceb 100644 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -139,4 +139,16 @@ #define JH7110_SYSRST_END 126 +/* AONCRG resets */ +#define JH7110_AONRST_GMAC0_AXI 0 +#define JH7110_AONRST_GMAC0_AHB 1 +#define JH7110_AONRST_IOMUX 2 +#define JH7110_AONRST_PMU_APB 3 +#define JH7110_AONRST_PMU_WKUP 4 +#define JH7110_AONRST_RTC_APB 5 +#define JH7110_AONRST_RTC_CAL 6 +#define JH7110_AONRST_RTC_32K 7 + +#define JH7110_AONRST_END 8 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ -- 2.38.1
WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@starfivetech.com> To: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org> Cc: Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, "Daniel Lezcano" <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Hal Feng <hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v5 12/21] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator Date: Sat, 11 Mar 2023 17:07:24 +0800 [thread overview] Message-ID: <20230311090733.56918-13-hal.feng@starfivetech.com> (raw) In-Reply-To: <20230311090733.56918-1-hal.feng@starfivetech.com> From: Emil Renner Berthing <kernel@esmil.dk> Add bindings for the always-on clock and reset generator (AONCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- .../clock/starfive,jh7110-aoncrg.yaml | 107 ++++++++++++++++++ .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++ .../dt-bindings/reset/starfive,jh7110-crg.h | 12 ++ 3 files changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml new file mode 100644 index 000000000000..923680a44aef --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Always-On Clock and Reset Generator + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + +properties: + compatible: + const: starfive,jh7110-aoncrg + + reg: + maxItems: 1 + + clocks: + oneOf: + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference or GMAC0 RGMII RX + - description: STG AXI/AHB + - description: APB Bus + - description: GMAC0 GTX + + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference or GMAC0 RGMII RX + - description: STG AXI/AHB or GMAC0 RGMII RX + - description: APB Bus or STG AXI/AHB + - description: GMAC0 GTX or APB Bus + - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX + + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference + - description: GMAC0 RGMII RX + - description: STG AXI/AHB + - description: APB Bus + - description: GMAC0 GTX + - description: RTC Oscillator (32.768 kHz) + + clock-names: + oneOf: + - minItems: 5 + items: + - const: osc + - enum: + - gmac0_rmii_refin + - gmac0_rgmii_rxin + - const: stg_axiahb + - const: apb_bus + - const: gmac0_gtxclk + - const: rtc_osc + + - minItems: 6 + items: + - const: osc + - const: gmac0_rmii_refin + - const: gmac0_rgmii_rxin + - const: stg_axiahb + - const: apb_bus + - const: gmac0_gtxclk + - const: rtc_osc + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + + clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x17000000 0x10000>; + clocks = <&osc>, <&gmac0_rmii_refin>, + <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, + <&rtc_osc>; + clock-names = "osc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus", "gmac0_gtxclk", + "rtc_osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index fdd1852e34cc..06257bfd9ac1 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -200,4 +200,22 @@ #define JH7110_SYSCLK_END 190 +/* AONCRG clocks */ +#define JH7110_AONCLK_OSC_DIV4 0 +#define JH7110_AONCLK_APB_FUNC 1 +#define JH7110_AONCLK_GMAC0_AHB 2 +#define JH7110_AONCLK_GMAC0_AXI 3 +#define JH7110_AONCLK_GMAC0_RMII_RTX 4 +#define JH7110_AONCLK_GMAC0_TX 5 +#define JH7110_AONCLK_GMAC0_TX_INV 6 +#define JH7110_AONCLK_GMAC0_RX 7 +#define JH7110_AONCLK_GMAC0_RX_INV 8 +#define JH7110_AONCLK_OTPC_APB 9 +#define JH7110_AONCLK_RTC_APB 10 +#define JH7110_AONCLK_RTC_INTERNAL 11 +#define JH7110_AONCLK_RTC_32K 12 +#define JH7110_AONCLK_RTC_CAL 13 + +#define JH7110_AONCLK_END 14 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h index b88216a4fe40..d78e38690ceb 100644 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -139,4 +139,16 @@ #define JH7110_SYSRST_END 126 +/* AONCRG resets */ +#define JH7110_AONRST_GMAC0_AXI 0 +#define JH7110_AONRST_GMAC0_AHB 1 +#define JH7110_AONRST_IOMUX 2 +#define JH7110_AONRST_PMU_APB 3 +#define JH7110_AONRST_PMU_WKUP 4 +#define JH7110_AONRST_RTC_APB 5 +#define JH7110_AONRST_RTC_CAL 6 +#define JH7110_AONRST_RTC_32K 7 + +#define JH7110_AONRST_END 8 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ -- 2.38.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-03-11 9:09 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-11 9:07 [PATCH v5 00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 01/21] clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 12:56 ` Conor Dooley 2023-03-11 12:56 ` Conor Dooley 2023-03-11 9:07 ` [PATCH v5 02/21] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 03/21] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-12 14:00 ` Conor Dooley 2023-03-12 14:00 ` Conor Dooley 2023-03-13 2:37 ` Hal Feng 2023-03-13 2:37 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 04/21] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-16 19:05 ` Tommaso Merciai 2023-03-16 19:05 ` Tommaso Merciai 2023-03-18 4:19 ` Hal Feng 2023-03-18 4:19 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 05/21] reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 12:56 ` Conor Dooley 2023-03-11 12:56 ` Conor Dooley 2023-03-14 14:34 ` Philipp Zabel 2023-03-14 14:34 ` Philipp Zabel 2023-03-20 11:51 ` Emil Renner Berthing 2023-03-20 11:51 ` Emil Renner Berthing 2023-03-11 9:07 ` [PATCH v5 06/21] reset: Create subdirectory for StarFive drivers Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-14 14:34 ` Philipp Zabel 2023-03-14 14:34 ` Philipp Zabel 2023-03-17 8:17 ` Hal Feng 2023-03-17 8:17 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 07/21] reset: starfive: Factor out common JH71X0 reset code Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 08/21] reset: starfive: Extract the " Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 09/21] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 10/21] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 11/21] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 13:11 ` Conor Dooley 2023-03-11 13:11 ` Conor Dooley 2023-03-13 3:22 ` Hal Feng 2023-03-13 3:22 ` Hal Feng 2023-03-13 8:53 ` Emil Renner Berthing 2023-03-13 8:53 ` Emil Renner Berthing 2023-03-14 14:09 ` Hal Feng 2023-03-14 14:09 ` Hal Feng 2023-03-11 14:17 ` Rob Herring 2023-03-11 14:17 ` Rob Herring 2023-03-13 2:47 ` Hal Feng 2023-03-13 2:47 ` Hal Feng 2023-03-13 7:51 ` Krzysztof Kozlowski 2023-03-13 7:51 ` Krzysztof Kozlowski 2023-03-14 14:18 ` Hal Feng 2023-03-14 14:18 ` Hal Feng 2023-03-11 9:07 ` Hal Feng [this message] 2023-03-11 9:07 ` [PATCH v5 12/21] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng 2023-03-11 13:14 ` Conor Dooley 2023-03-11 13:14 ` Conor Dooley 2023-03-19 13:28 ` Hal Feng 2023-03-19 13:28 ` Hal Feng 2023-03-11 14:18 ` Rob Herring 2023-03-11 14:18 ` Rob Herring 2023-03-13 2:49 ` Hal Feng 2023-03-13 2:49 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 13/21] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 14/21] clk: starfive: Add StarFive JH7110 always-on " Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 15/21] reset: starfive: Add StarFive JH7110 reset driver Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 16/21] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 17/21] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 18/21] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 19/21] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 20/21] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng 2023-03-11 9:07 ` Hal Feng 2023-03-11 9:07 ` [PATCH v5 21/21] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng 2023-03-11 9:07 ` Hal Feng
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