* [PATCH 0/5] soc: qcom: Add support for SM4450
@ 2023-07-19 10:01 Tengfei Fan
2023-07-19 10:01 ` [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI Tengfei Fan
` (4 more replies)
0 siblings, 5 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-19 10:01 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel, Tengfei Fan
This series adds CPU, SoC and board compatible support for SM4450.
Tengfei Fan (5):
arm64: dts: qcom: Add base SM4450 DTSI
arm64: dts: qcom: Add base SM4450 QRD DTS
dt-bindings: firmware: scm: Add SM4450
dt-bindings: arm: qcom: Document SM4450 SoC and boards
soc: qcom: socinfo: add SM4450 ID
.../devicetree/bindings/arm/qcom.yaml | 6 +
.../bindings/firmware/qcom,scm.yaml | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 +
arch/arm64/boot/dts/qcom/sm4450.dtsi | 435 ++++++++++++++++++
drivers/soc/qcom/socinfo.c | 1 +
include/dt-bindings/arm/qcom,ids.h | 2 +
7 files changed, 464 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm4450-qrd.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm4450.dtsi
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI
2023-07-19 10:01 [PATCH 0/5] soc: qcom: Add support for SM4450 Tengfei Fan
@ 2023-07-19 10:01 ` Tengfei Fan
2023-07-19 10:14 ` Dmitry Baryshkov
` (2 more replies)
2023-07-19 10:01 ` [PATCH 2/5] arm64: dts: qcom: Add base SM4450 QRD DTS Tengfei Fan
` (3 subsequent siblings)
4 siblings, 3 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-19 10:01 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel, Tengfei Fan
This add based DTSI for SM4450 SoC and includes base description of
CPUs and interrupt-controller which helps to boot to shell with
console on boards with this SoC.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm4450.dtsi | 435 +++++++++++++++++++++++++++
1 file changed, 435 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm4450.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
new file mode 100644
index 000000000000..ab14aecbdcea
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -0,0 +1,435 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks{
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_100>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_300>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&L2_400>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&L2_500>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ next-level-cache = <&L2_600>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ next-level-cache = <&L2_700>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+ };
+
+ cluster1 {
+ core6 {
+ cpu = <&CPU6>;
+ };
+
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "silver-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <800>;
+ exit-latency-us = <750>;
+ min-residency-us = <4090>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <600>;
+ exit-latency-us = <1550>;
+ min-residency-us = <4791>;
+ local-timer-stop;
+ };
+ };
+
+ domain-idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <1050>;
+ exit-latency-us = <2500>;
+ min-residency-us = <5309>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ idle-state-name = "cluster-power-collapse";
+ arm,psci-suspend-param = <0x41003344>;
+ entry-latency-us = <1561>;
+ exit-latency-us = <2801>;
+ min-residency-us = <8550>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-sm4450", "qcom,scm";
+ #reset-cells = <1>;
+ };
+ };
+
+ memory@a0000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0xa0000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CLUSTER_PD: power-domain-cpu-cluster0 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
+ };
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sm4450-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
+ qcom,pdc-ranges = <0 480 94>, <94 494 31>, <125 63 1>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ intc: interrupt-controller@17200000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
+ <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ timer@17420000 {
+ compatible = "arm,armv7-timer-mem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x20000000>;
+ reg = <0x0 0x17420000 0x0 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17421000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17421000 0x1000>,
+ <0x17422000 0x1000>;
+ };
+
+ frame@17423000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17423000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17425000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17425000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17427000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17427000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17429000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17429000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@1742b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1742b000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@1742d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1742d000 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 2/5] arm64: dts: qcom: Add base SM4450 QRD DTS
2023-07-19 10:01 [PATCH 0/5] soc: qcom: Add support for SM4450 Tengfei Fan
2023-07-19 10:01 ` [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI Tengfei Fan
@ 2023-07-19 10:01 ` Tengfei Fan
2023-07-19 10:17 ` Dmitry Baryshkov
2023-07-19 10:23 ` Krzysztof Kozlowski
2023-07-19 10:01 ` [PATCH 3/5] dt-bindings: firmware: scm: Add SM4450 Tengfei Fan
` (2 subsequent siblings)
4 siblings, 2 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-19 10:01 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel, Tengfei Fan
Add DTS for Qualcomm QRD platform which uses SM4450 SoC.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 ++++++++++++++++++
2 files changed, 19 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm4450-qrd.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 337abc4ceb17..a0cfd37e674b 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -215,3 +215,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
new file mode 100644
index 000000000000..851a6761a6ea
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sm4450.dtsi"
+/ {
+ model = "Qualcomm Technologies, Inc. SM4450 QRD";
+ compatible = "qcom,sm4450-qrd", "qcom,sm4450";
+
+ aliases { };
+
+ chosen {
+ bootargs = " ";
+ };
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 3/5] dt-bindings: firmware: scm: Add SM4450
2023-07-19 10:01 [PATCH 0/5] soc: qcom: Add support for SM4450 Tengfei Fan
2023-07-19 10:01 ` [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI Tengfei Fan
2023-07-19 10:01 ` [PATCH 2/5] arm64: dts: qcom: Add base SM4450 QRD DTS Tengfei Fan
@ 2023-07-19 10:01 ` Tengfei Fan
2023-07-19 10:16 ` Dmitry Baryshkov
2023-07-19 10:24 ` Krzysztof Kozlowski
2023-07-19 10:01 ` [PATCH 4/5] dt-bindings: arm: qcom: Document SM4450 SoC and boards Tengfei Fan
2023-07-19 10:01 ` [PATCH 5/5] soc: qcom: socinfo: add SM4450 ID Tengfei Fan
4 siblings, 2 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-19 10:01 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel, Tengfei Fan
Add compatible for SM4450 SoCs.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index bdbee58a542b..f02f0815bece 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -62,6 +62,7 @@ properties:
- qcom,scm-sm8450
- qcom,scm-sm8550
- qcom,scm-qcs404
+ - qcom,scm-sm4450
- const: qcom,scm
clocks:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 4/5] dt-bindings: arm: qcom: Document SM4450 SoC and boards
2023-07-19 10:01 [PATCH 0/5] soc: qcom: Add support for SM4450 Tengfei Fan
` (2 preceding siblings ...)
2023-07-19 10:01 ` [PATCH 3/5] dt-bindings: firmware: scm: Add SM4450 Tengfei Fan
@ 2023-07-19 10:01 ` Tengfei Fan
2023-07-19 10:15 ` Dmitry Baryshkov
2023-07-19 10:24 ` Krzysztof Kozlowski
2023-07-19 10:01 ` [PATCH 5/5] soc: qcom: socinfo: add SM4450 ID Tengfei Fan
4 siblings, 2 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-19 10:01 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel, Tengfei Fan
Document the SM8450 SoC binding and also the boards using it.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 450f616774e0..691e66612872 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -83,6 +83,7 @@ description: |
sm8350
sm8450
sm8550
+ sm4450
The 'board' element must be one of the following strings:
@@ -976,6 +977,11 @@ properties:
- qcom,sm8550-qrd
- const: qcom,sm8550
+ - items:
+ - enum:
+ - qcom,sm4450-qrd
+ - const: qcom,sm4450
+
# Board compatibles go above
qcom,msm-id:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 5/5] soc: qcom: socinfo: add SM4450 ID
2023-07-19 10:01 [PATCH 0/5] soc: qcom: Add support for SM4450 Tengfei Fan
` (3 preceding siblings ...)
2023-07-19 10:01 ` [PATCH 4/5] dt-bindings: arm: qcom: Document SM4450 SoC and boards Tengfei Fan
@ 2023-07-19 10:01 ` Tengfei Fan
2023-07-19 10:15 ` Dmitry Baryshkov
2023-07-19 10:25 ` Krzysztof Kozlowski
4 siblings, 2 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-19 10:01 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel, Tengfei Fan
Add the ID for the Qualcomm SM4450 SoC.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
drivers/soc/qcom/socinfo.c | 1 +
include/dt-bindings/arm/qcom,ids.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
index 4d49945b3a35..fa5e4c54207a 100644
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -415,6 +415,7 @@ static const struct soc_id soc_id[] = {
{ qcom_board_id(IPQ5312) },
{ qcom_board_id(IPQ5302) },
{ qcom_board_id(IPQ5300) },
+ { qcom_board_id(SM4450) },
};
static const char *socinfo_machine(struct device *dev, unsigned int id)
diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index bcbe9ee2cdaf..6201bfb1405e 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -2,6 +2,7 @@
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Linaro Ltd
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Author: Krzysztof Kozlowski <krzk@kernel.org> based on previous work of Kumar Gala.
*/
#ifndef _DT_BINDINGS_ARM_QCOM_IDS_H
@@ -259,6 +260,7 @@
#define QCOM_ID_IPQ5312 594
#define QCOM_ID_IPQ5302 595
#define QCOM_ID_IPQ5300 624
+#define QCOM_ID_SM4450 568
/*
* The board type and revision information, used by Qualcomm bootloaders and
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI
2023-07-19 10:01 ` [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI Tengfei Fan
@ 2023-07-19 10:14 ` Dmitry Baryshkov
2023-07-21 1:53 ` Tengfei Fan
2023-07-19 10:22 ` Krzysztof Kozlowski
2023-07-20 7:54 ` Konrad Dybcio
2 siblings, 1 reply; 29+ messages in thread
From: Dmitry Baryshkov @ 2023-07-19 10:14 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19/07/2023 13:01, Tengfei Fan wrote:
> This add based DTSI for SM4450 SoC and includes base description of
> CPUs and interrupt-controller which helps to boot to shell with
> console on boards with this SoC.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sm4450.dtsi | 435 +++++++++++++++++++++++++++
> 1 file changed, 435 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm4450.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> new file mode 100644
> index 000000000000..ab14aecbdcea
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> @@ -0,0 +1,435 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + clocks{
> + xo_board: xo_board {
no underscores in node names.
> + compatible = "fixed-clock";
> + clock-frequency = <76800000>;
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + #cooling-cells = <2>;
empty lines before child nodes, please (here and further in the patch).
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
> + compatible = "cache";
> + cache-level = <3>;
> + cache-unified;
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_100>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + #cooling-cells = <2>;
> + L2_100: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + next-level-cache = <&L2_200>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + #cooling-cells = <2>;
> + L2_200: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + next-level-cache = <&L2_300>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + #cooling-cells = <2>;
> + L2_300: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU4: cpu@400 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x400>;
> + enable-method = "psci";
> + next-level-cache = <&L2_400>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + #cooling-cells = <2>;
> + L2_400: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU5: cpu@500 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x500>;
> + enable-method = "psci";
> + next-level-cache = <&L2_500>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + #cooling-cells = <2>;
> + L2_500: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU6: cpu@600 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x600>;
> + enable-method = "psci";
> + next-level-cache = <&L2_600>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + #cooling-cells = <2>;
> + L2_600: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU7: cpu@700 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x700>;
> + enable-method = "psci";
> + next-level-cache = <&L2_700>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + #cooling-cells = <2>;
> + L2_700: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> +
> + core2 {
> + cpu = <&CPU2>;
> + };
> +
> + core3 {
> + cpu = <&CPU3>;
> + };
> +
> + core4 {
> + cpu = <&CPU4>;
> + };
> +
> + core5 {
> + cpu = <&CPU5>;
> + };
> + };
> +
> + cluster1 {
If this SoC implements Dynamiq architecture, you don't need separate
clusters.
> + core6 {
> + cpu = <&CPU6>;
> + };
> +
> + core7 {
> + cpu = <&CPU7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "silver-rail-power-collapse";
> + arm,psci-suspend-param = <0x40000004>;
> + entry-latency-us = <800>;
> + exit-latency-us = <750>;
> + min-residency-us = <4090>;
> + local-timer-stop;
> + };
> +
> + BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "gold-rail-power-collapse";
> + arm,psci-suspend-param = <0x40000004>;
> + entry-latency-us = <600>;
> + exit-latency-us = <1550>;
> + min-residency-us = <4791>;
> + local-timer-stop;
> + };
> + };
> +
> + domain-idle-states {
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x41000044>;
> + entry-latency-us = <1050>;
> + exit-latency-us = <2500>;
> + min-residency-us = <5309>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "domain-idle-state";
> + idle-state-name = "cluster-power-collapse";
> + arm,psci-suspend-param = <0x41003344>;
> + entry-latency-us = <1561>;
> + exit-latency-us = <2801>;
> + min-residency-us = <8550>;
> + };
> + };
> + };
> +
> + firmware {
> + scm: scm {
> + compatible = "qcom,scm-sm4450", "qcom,scm";
> + #reset-cells = <1>;
Does the SCM need the core clock?
> + };
> + };
> +
> + memory@a0000000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0x0 0xa0000000 0x0 0x0>;
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> +
> + CPU_PD0: power-domain-cpu0 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD1: power-domain-cpu1 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD2: power-domain-cpu2 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD3: power-domain-cpu3 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD4: power-domain-cpu4 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD5: power-domain-cpu5 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD6: power-domain-cpu6 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD7: power-domain-cpu7 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CLUSTER_PD: power-domain-cpu-cluster0 {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
> + };
> + };
> +
> + soc: soc@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0 0x10 0>;
> + dma-ranges = <0 0 0 0 0x10 0>;
> + compatible = "simple-bus";
> +
> + tcsr_mutex: hwlock@1f40000 {
> + compatible = "qcom,tcsr-mutex";
> + reg = <0x0 0x01f40000 0x0 0x40000>;
> + #hwlock-cells = <1>;
> + };
> +
> + pdc: interrupt-controller@b220000 {
> + compatible = "qcom,sm4450-pdc", "qcom,pdc";
Missing binding update
> + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
> + qcom,pdc-ranges = <0 480 94>, <94 494 31>, <125 63 1>;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
> +
> + intc: interrupt-controller@17200000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + #redistributor-regions = <1>;
> + redistributor-stride = <0x0 0x20000>;
> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
> + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
Please align vertically.
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + timer@17420000 {
> + compatible = "arm,armv7-timer-mem";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0x20000000>;
> + reg = <0x0 0x17420000 0x0 0x1000>;
> + clock-frequency = <19200000>;
> +
> + frame@17421000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
Please align vertically.
> + reg = <0x17421000 0x1000>,
> + <0x17422000 0x1000>;
> + };
> +
> + frame@17423000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17423000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17425000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17425000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17427000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17427000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17429000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17429000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@1742b000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x1742b000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@1742d000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x1742d000 0x1000>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
Please align vertically.
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <19200000>;
> + };
> +};
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 5/5] soc: qcom: socinfo: add SM4450 ID
2023-07-19 10:01 ` [PATCH 5/5] soc: qcom: socinfo: add SM4450 ID Tengfei Fan
@ 2023-07-19 10:15 ` Dmitry Baryshkov
2023-07-19 10:26 ` Krzysztof Kozlowski
2023-07-19 10:25 ` Krzysztof Kozlowski
1 sibling, 1 reply; 29+ messages in thread
From: Dmitry Baryshkov @ 2023-07-19 10:15 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19/07/2023 13:01, Tengfei Fan wrote:
> Add the ID for the Qualcomm SM4450 SoC.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> drivers/soc/qcom/socinfo.c | 1 +
> include/dt-bindings/arm/qcom,ids.h | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
> index 4d49945b3a35..fa5e4c54207a 100644
> --- a/drivers/soc/qcom/socinfo.c
> +++ b/drivers/soc/qcom/socinfo.c
> @@ -415,6 +415,7 @@ static const struct soc_id soc_id[] = {
> { qcom_board_id(IPQ5312) },
> { qcom_board_id(IPQ5302) },
> { qcom_board_id(IPQ5300) },
> + { qcom_board_id(SM4450) },
> };
>
> static const char *socinfo_machine(struct device *dev, unsigned int id)
> diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
> index bcbe9ee2cdaf..6201bfb1405e 100644
> --- a/include/dt-bindings/arm/qcom,ids.h
> +++ b/include/dt-bindings/arm/qcom,ids.h
> @@ -2,6 +2,7 @@
> /*
> * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> * Copyright (c) 2022 Linaro Ltd
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
I wonder whether a single define is copyrightable.
> * Author: Krzysztof Kozlowski <krzk@kernel.org> based on previous work of Kumar Gala.
> */
> #ifndef _DT_BINDINGS_ARM_QCOM_IDS_H
> @@ -259,6 +260,7 @@
> #define QCOM_ID_IPQ5312 594
> #define QCOM_ID_IPQ5302 595
> #define QCOM_ID_IPQ5300 624
> +#define QCOM_ID_SM4450 568
>
> /*
> * The board type and revision information, used by Qualcomm bootloaders and
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 4/5] dt-bindings: arm: qcom: Document SM4450 SoC and boards
2023-07-19 10:01 ` [PATCH 4/5] dt-bindings: arm: qcom: Document SM4450 SoC and boards Tengfei Fan
@ 2023-07-19 10:15 ` Dmitry Baryshkov
2023-07-21 2:20 ` Tengfei Fan
2023-07-19 10:24 ` Krzysztof Kozlowski
1 sibling, 1 reply; 29+ messages in thread
From: Dmitry Baryshkov @ 2023-07-19 10:15 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19/07/2023 13:01, Tengfei Fan wrote:
> Document the SM8450 SoC binding and also the boards using it.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 450f616774e0..691e66612872 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -83,6 +83,7 @@ description: |
> sm8350
> sm8450
> sm8550
> + sm4450
Please sort properly
>
> The 'board' element must be one of the following strings:
>
> @@ -976,6 +977,11 @@ properties:
> - qcom,sm8550-qrd
> - const: qcom,sm8550
>
> + - items:
> + - enum:
> + - qcom,sm4450-qrd
> + - const: qcom,sm4450
> +
And here
> # Board compatibles go above
>
> qcom,msm-id:
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/5] dt-bindings: firmware: scm: Add SM4450
2023-07-19 10:01 ` [PATCH 3/5] dt-bindings: firmware: scm: Add SM4450 Tengfei Fan
@ 2023-07-19 10:16 ` Dmitry Baryshkov
2023-07-21 2:19 ` Tengfei Fan
2023-07-19 10:24 ` Krzysztof Kozlowski
1 sibling, 1 reply; 29+ messages in thread
From: Dmitry Baryshkov @ 2023-07-19 10:16 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19/07/2023 13:01, Tengfei Fan wrote:
> Add compatible for SM4450 SoCs.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
> index bdbee58a542b..f02f0815bece 100644
> --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
> +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
> @@ -62,6 +62,7 @@ properties:
> - qcom,scm-sm8450
> - qcom,scm-sm8550
> - qcom,scm-qcs404
> + - qcom,scm-sm4450
Please keep this list sorted.
> - const: qcom,scm
>
> clocks:
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/5] arm64: dts: qcom: Add base SM4450 QRD DTS
2023-07-19 10:01 ` [PATCH 2/5] arm64: dts: qcom: Add base SM4450 QRD DTS Tengfei Fan
@ 2023-07-19 10:17 ` Dmitry Baryshkov
2023-07-21 2:07 ` Tengfei Fan
2023-07-19 10:23 ` Krzysztof Kozlowski
1 sibling, 1 reply; 29+ messages in thread
From: Dmitry Baryshkov @ 2023-07-19 10:17 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19/07/2023 13:01, Tengfei Fan wrote:
> Add DTS for Qualcomm QRD platform which uses SM4450 SoC.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 ++++++++++++++++++
> 2 files changed, 19 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 337abc4ceb17..a0cfd37e674b 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -215,3 +215,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
You guess, this should be sorted.
> diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> new file mode 100644
> index 000000000000..851a6761a6ea
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "sm4450.dtsi"
> +/ {
> + model = "Qualcomm Technologies, Inc. SM4450 QRD";
> + compatible = "qcom,sm4450-qrd", "qcom,sm4450";
> +
> + aliases { };
> +
> + chosen {
> + bootargs = " ";
Do you need this?
> + };
> +};
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI
2023-07-19 10:01 ` [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI Tengfei Fan
2023-07-19 10:14 ` Dmitry Baryshkov
@ 2023-07-19 10:22 ` Krzysztof Kozlowski
2023-07-21 1:59 ` Tengfei Fan
2023-07-20 7:54 ` Konrad Dybcio
2 siblings, 1 reply; 29+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-19 10:22 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19/07/2023 12:01, Tengfei Fan wrote:
> This add based DTSI for SM4450 SoC and includes base description of
> CPUs and interrupt-controller which helps to boot to shell with
> console on boards with this SoC.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Thank you for your patch. There is something to discuss/improve.
> ---
> arch/arm64/boot/dts/qcom/sm4450.dtsi | 435 +++++++++++++++++++++++++++
> 1 file changed, 435 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm4450.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> new file mode 100644
> index 000000000000..ab14aecbdcea
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> @@ -0,0 +1,435 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + clocks{
> + xo_board: xo_board {
Please start your work from scratch from mainline SoC, so we won't have
to point you all these obvious issues which we fixed long time ago. Just
pick the most recent SoC, like SM8550.
> + compatible = "fixed-clock";
> + clock-frequency = <76800000>;
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> + };
...
> + };
> + };
> +
> + firmware {
> + scm: scm {
> + compatible = "qcom,scm-sm4450", "qcom,scm";
Undocumented compatible. If you plan to document it further, then please
check if your patches are correctly ordered. Bindings are always before
their users.
> + #reset-cells = <1>;
> + };
> + };
> +
> + memory@a0000000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0x0 0xa0000000 0x0 0x0>;
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> +
> + CPU_PD0: power-domain-cpu0 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD1: power-domain-cpu1 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD2: power-domain-cpu2 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD3: power-domain-cpu3 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD4: power-domain-cpu4 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD5: power-domain-cpu5 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD6: power-domain-cpu6 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD7: power-domain-cpu7 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CLUSTER_PD: power-domain-cpu-cluster0 {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
> + };
> + };
> +
> + soc: soc@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0 0x10 0>;
> + dma-ranges = <0 0 0 0 0x10 0>;
> + compatible = "simple-bus";
> +
> + tcsr_mutex: hwlock@1f40000 {
> + compatible = "qcom,tcsr-mutex";
> + reg = <0x0 0x01f40000 0x0 0x40000>;
> + #hwlock-cells = <1>;
> + };
> +
> + pdc: interrupt-controller@b220000 {
> + compatible = "qcom,sm4450-pdc", "qcom,pdc";
> + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
> + qcom,pdc-ranges = <0 480 94>, <94 494 31>, <125 63 1>;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
> +
> + intc: interrupt-controller@17200000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + #redistributor-regions = <1>;
> + redistributor-stride = <0x0 0x20000>;
> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
> + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
reg is always after compatible. Then ranges follow.
Also, indentation looks not aligned here.
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + timer@17420000 {
> + compatible = "arm,armv7-timer-mem";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0x20000000>;
> + reg = <0x0 0x17420000 0x0 0x1000>;
Same problem... some weird ordering.
> + clock-frequency = <19200000>;
Are you sure this property is allowed in new designs?
> +
> + frame@17421000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17421000 0x1000>,
> + <0x17422000 0x1000>;
> + };
> +
> + frame@17423000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17423000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17425000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17425000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17427000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17427000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17429000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17429000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@1742b000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x1742b000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@1742d000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x1742d000 0x1000>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <19200000>;
Are you sure this property is allowed in new designs?
> + };
> +};
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/5] arm64: dts: qcom: Add base SM4450 QRD DTS
2023-07-19 10:01 ` [PATCH 2/5] arm64: dts: qcom: Add base SM4450 QRD DTS Tengfei Fan
2023-07-19 10:17 ` Dmitry Baryshkov
@ 2023-07-19 10:23 ` Krzysztof Kozlowski
2023-07-21 2:18 ` Tengfei Fan
1 sibling, 1 reply; 29+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-19 10:23 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19/07/2023 12:01, Tengfei Fan wrote:
> Add DTS for Qualcomm QRD platform which uses SM4450 SoC.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 ++++++++++++++++++
> 2 files changed, 19 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 337abc4ceb17..a0cfd37e674b 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -215,3 +215,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
Messed order.
> diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> new file mode 100644
> index 000000000000..851a6761a6ea
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "sm4450.dtsi"
> +/ {
> + model = "Qualcomm Technologies, Inc. SM4450 QRD";
> + compatible = "qcom,sm4450-qrd", "qcom,sm4450";
Missing bindings.
> +
> + aliases { };
> +
> + chosen {
> + bootargs = " ";
Drop, useless.
OTOH, you miss here several properties. This is not even a basic board -
nothing works here, right? Please submit when you have at least serial
working.
> + };
> +};
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/5] dt-bindings: firmware: scm: Add SM4450
2023-07-19 10:01 ` [PATCH 3/5] dt-bindings: firmware: scm: Add SM4450 Tengfei Fan
2023-07-19 10:16 ` Dmitry Baryshkov
@ 2023-07-19 10:24 ` Krzysztof Kozlowski
2023-07-21 2:19 ` Tengfei Fan
1 sibling, 1 reply; 29+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-19 10:24 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19/07/2023 12:01, Tengfei Fan wrote:
> Add compatible for SM4450 SoCs.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
> index bdbee58a542b..f02f0815bece 100644
> --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
> +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
> @@ -62,6 +62,7 @@ properties:
> - qcom,scm-sm8450
> - qcom,scm-sm8550
> - qcom,scm-qcs404
> + - qcom,scm-sm4450
Please keep things sorted...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 4/5] dt-bindings: arm: qcom: Document SM4450 SoC and boards
2023-07-19 10:01 ` [PATCH 4/5] dt-bindings: arm: qcom: Document SM4450 SoC and boards Tengfei Fan
2023-07-19 10:15 ` Dmitry Baryshkov
@ 2023-07-19 10:24 ` Krzysztof Kozlowski
2023-07-21 2:24 ` Tengfei Fan
1 sibling, 1 reply; 29+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-19 10:24 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19/07/2023 12:01, Tengfei Fan wrote:
> Document the SM8450 SoC binding and also the boards using it.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 450f616774e0..691e66612872 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -83,6 +83,7 @@ description: |
> sm8350
> sm8450
> sm8550
> + sm4450
>
> The 'board' element must be one of the following strings:
>
> @@ -976,6 +977,11 @@ properties:
> - qcom,sm8550-qrd
> - const: qcom,sm8550
>
> + - items:
> + - enum:
> + - qcom,sm4450-qrd
> + - const: qcom,sm4450
No, really...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 5/5] soc: qcom: socinfo: add SM4450 ID
2023-07-19 10:01 ` [PATCH 5/5] soc: qcom: socinfo: add SM4450 ID Tengfei Fan
2023-07-19 10:15 ` Dmitry Baryshkov
@ 2023-07-19 10:25 ` Krzysztof Kozlowski
2023-07-21 2:27 ` Tengfei Fan
1 sibling, 1 reply; 29+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-19 10:25 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19/07/2023 12:01, Tengfei Fan wrote:
> Add the ID for the Qualcomm SM4450 SoC.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> drivers/soc/qcom/socinfo.c | 1 +
> include/dt-bindings/arm/qcom,ids.h | 2 ++
Bindings are always separate patches.
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
> index 4d49945b3a35..fa5e4c54207a 100644
> --- a/drivers/soc/qcom/socinfo.c
> +++ b/drivers/soc/qcom/socinfo.c
> @@ -415,6 +415,7 @@ static const struct soc_id soc_id[] = {
> { qcom_board_id(IPQ5312) },
> { qcom_board_id(IPQ5302) },
> { qcom_board_id(IPQ5300) },
> + { qcom_board_id(SM4450) },
> };
>
> static const char *socinfo_machine(struct device *dev, unsigned int id)
> diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
> index bcbe9ee2cdaf..6201bfb1405e 100644
> --- a/include/dt-bindings/arm/qcom,ids.h
> +++ b/include/dt-bindings/arm/qcom,ids.h
> @@ -2,6 +2,7 @@
> /*
> * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> * Copyright (c) 2022 Linaro Ltd
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> * Author: Krzysztof Kozlowski <krzk@kernel.org> based on previous work of Kumar Gala.
> */
> #ifndef _DT_BINDINGS_ARM_QCOM_IDS_H
> @@ -259,6 +260,7 @@
> #define QCOM_ID_IPQ5312 594
> #define QCOM_ID_IPQ5302 595
> #define QCOM_ID_IPQ5300 624
> +#define QCOM_ID_SM4450 568
No, come on...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 5/5] soc: qcom: socinfo: add SM4450 ID
2023-07-19 10:15 ` Dmitry Baryshkov
@ 2023-07-19 10:26 ` Krzysztof Kozlowski
2023-07-21 2:26 ` Tengfei Fan
0 siblings, 1 reply; 29+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-19 10:26 UTC (permalink / raw)
To: Dmitry Baryshkov, Tengfei Fan, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19/07/2023 12:15, Dmitry Baryshkov wrote:
> On 19/07/2023 13:01, Tengfei Fan wrote:
>> Add the ID for the Qualcomm SM4450 SoC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> drivers/soc/qcom/socinfo.c | 1 +
>> include/dt-bindings/arm/qcom,ids.h | 2 ++
>> 2 files changed, 3 insertions(+)
>>
>> diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
>> index 4d49945b3a35..fa5e4c54207a 100644
>> --- a/drivers/soc/qcom/socinfo.c
>> +++ b/drivers/soc/qcom/socinfo.c
>> @@ -415,6 +415,7 @@ static const struct soc_id soc_id[] = {
>> { qcom_board_id(IPQ5312) },
>> { qcom_board_id(IPQ5302) },
>> { qcom_board_id(IPQ5300) },
>> + { qcom_board_id(SM4450) },
>> };
>>
>> static const char *socinfo_machine(struct device *dev, unsigned int id)
>> diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
>> index bcbe9ee2cdaf..6201bfb1405e 100644
>> --- a/include/dt-bindings/arm/qcom,ids.h
>> +++ b/include/dt-bindings/arm/qcom,ids.h
>> @@ -2,6 +2,7 @@
>> /*
>> * Copyright (c) 2015, The Linux Foundation. All rights reserved.
>> * Copyright (c) 2022 Linaro Ltd
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>
> I wonder whether a single define is copyrightable.
If you carefully choose a place, like out of order, then probably it is
a creative work. :)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI
2023-07-19 10:01 ` [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI Tengfei Fan
2023-07-19 10:14 ` Dmitry Baryshkov
2023-07-19 10:22 ` Krzysztof Kozlowski
@ 2023-07-20 7:54 ` Konrad Dybcio
2023-07-21 2:03 ` Tengfei Fan
2 siblings, 1 reply; 29+ messages in thread
From: Konrad Dybcio @ 2023-07-20 7:54 UTC (permalink / raw)
To: Tengfei Fan, andersson, robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
On 19.07.2023 12:01, Tengfei Fan wrote:
> This add based DTSI for SM4450 SoC and includes base description of
> CPUs and interrupt-controller which helps to boot to shell with
> console on boards with this SoC.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
[...]
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/gpio/gpio.h>
Please sort them alphabetically
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
[...]
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
Please post dmesg | grep '\[', this is probably a standard ARM core.
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + #cooling-cells = <2>;
> + L2_0: l2-cache {
Missing a newline before subnodes
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
Ditto
> + compatible = "cache";
> + cache-level = <3>;
> + cache-unified;
> + };
> + };
> + };
[...]
> +
> + intc: interrupt-controller@17200000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + #redistributor-regions = <1>;
> + redistributor-stride = <0x0 0x20000>;
> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
> + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
Misasligned
also, please move reg and interrupts after compatible
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + timer@17420000 {
> + compatible = "arm,armv7-timer-mem";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0x20000000>;
> + reg = <0x0 0x17420000 0x0 0x1000>;
> + clock-frequency = <19200000>;
Drop clock-frequency
[...]
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
Misaligned
> + clock-frequency = <19200000>;
Drop
Konrad
> + };
> +};
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI
2023-07-19 10:14 ` Dmitry Baryshkov
@ 2023-07-21 1:53 ` Tengfei Fan
0 siblings, 0 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-21 1:53 UTC (permalink / raw)
To: Dmitry Baryshkov, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
在 7/19/2023 6:14 PM, Dmitry Baryshkov 写道:
> On 19/07/2023 13:01, Tengfei Fan wrote:
>> This add based DTSI for SM4450 SoC and includes base description of
>> CPUs and interrupt-controller which helps to boot to shell with
>> console on boards with this SoC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm4450.dtsi | 435 +++++++++++++++++++++++++++
>> 1 file changed, 435 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sm4450.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi
>> b/arch/arm64/boot/dts/qcom/sm4450.dtsi
>> new file mode 100644
>> index 000000000000..ab14aecbdcea
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
>> @@ -0,0 +1,435 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen { };
>> +
>> + clocks{
>> + xo_board: xo_board {
>
> no underscores in node names.
V2 patch will update "xo_board: xo_board" to "xo_board: xo-board", also
"sleep_clk: sleep_clk" to "sleep_clk: sleep-clk".
>
>> + compatible = "fixed-clock";
>> + clock-frequency = <76800000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + sleep_clk: sleep_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <32000>;
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + CPU0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo";
>> + reg = <0x0 0x0>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_0>;
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + #cooling-cells = <2>;
>
> empty lines before child nodes, please (here and further in the patch).
sure, V2 patch will add empty lines before child nodes(this and other
child nodes).
>
>> + L2_0: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + L3_0: l3-cache {
>> + compatible = "cache";
>> + cache-level = <3>;
>> + cache-unified;
>> + };
>> + };
>> + };
>> +
>> + CPU1: cpu@100 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo";
>> + reg = <0x0 0x100>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_100>;
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + #cooling-cells = <2>;
>> + L2_100: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU2: cpu@200 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo";
>> + reg = <0x0 0x200>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_200>;
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + #cooling-cells = <2>;
>> + L2_200: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU3: cpu@300 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo";
>> + reg = <0x0 0x300>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_300>;
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + #cooling-cells = <2>;
>> + L2_300: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU4: cpu@400 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo";
>> + reg = <0x0 0x400>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_400>;
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + #cooling-cells = <2>;
>> + L2_400: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU5: cpu@500 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo";
>> + reg = <0x0 0x500>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_500>;
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + #cooling-cells = <2>;
>> + L2_500: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU6: cpu@600 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo";
>> + reg = <0x0 0x600>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_600>;
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + #cooling-cells = <2>;
>> + L2_600: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU7: cpu@700 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo";
>> + reg = <0x0 0x700>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_700>;
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + #cooling-cells = <2>;
>> + L2_700: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&CPU0>;
>> + };
>> +
>> + core1 {
>> + cpu = <&CPU1>;
>> + };
>> +
>> + core2 {
>> + cpu = <&CPU2>;
>> + };
>> +
>> + core3 {
>> + cpu = <&CPU3>;
>> + };
>> +
>> + core4 {
>> + cpu = <&CPU4>;
>> + };
>> +
>> + core5 {
>> + cpu = <&CPU5>;
>> + };
>> + };
>> +
>> + cluster1 {
>
> If this SoC implements Dynamiq architecture, you don't need separate
> clusters.
V2 patch will not separate clusters.
>
>> + core6 {
>> + cpu = <&CPU6>;
>> + };
>> +
>> + core7 {
>> + cpu = <&CPU7>;
>> + };
>> + };
>> + };
>> +
>> + idle-states {
>> + entry-method = "psci";
>> +
>> + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
>> + compatible = "arm,idle-state";
>> + idle-state-name = "silver-rail-power-collapse";
>> + arm,psci-suspend-param = <0x40000004>;
>> + entry-latency-us = <800>;
>> + exit-latency-us = <750>;
>> + min-residency-us = <4090>;
>> + local-timer-stop;
>> + };
>> +
>> + BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
>> + compatible = "arm,idle-state";
>> + idle-state-name = "gold-rail-power-collapse";
>> + arm,psci-suspend-param = <0x40000004>;
>> + entry-latency-us = <600>;
>> + exit-latency-us = <1550>;
>> + min-residency-us = <4791>;
>> + local-timer-stop;
>> + };
>> + };
>> +
>> + domain-idle-states {
>> + CLUSTER_SLEEP_0: cluster-sleep-0 {
>> + compatible = "domain-idle-state";
>> + arm,psci-suspend-param = <0x41000044>;
>> + entry-latency-us = <1050>;
>> + exit-latency-us = <2500>;
>> + min-residency-us = <5309>;
>> + };
>> +
>> + CLUSTER_SLEEP_1: cluster-sleep-1 {
>> + compatible = "domain-idle-state";
>> + idle-state-name = "cluster-power-collapse";
>> + arm,psci-suspend-param = <0x41003344>;
>> + entry-latency-us = <1561>;
>> + exit-latency-us = <2801>;
>> + min-residency-us = <8550>;
>> + };
>> + };
>> + };
>> +
>> + firmware {
>> + scm: scm {
>> + compatible = "qcom,scm-sm4450", "qcom,scm";
>> + #reset-cells = <1>;
>
> Does the SCM need the core clock?
V2 patch will remove this SCM node due to it haven't useful currently.
>
>> + };
>> + };
>> +
>> + memory@a0000000 {
>> + device_type = "memory";
>> + /* We expect the bootloader to fill in the size */
>> + reg = <0x0 0xa0000000 0x0 0x0>;
>> + };
>> +
>> + pmu {
>> + compatible = "arm,armv8-pmuv3";
>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-1.0";
>> + method = "smc";
>> +
>> + CPU_PD0: power-domain-cpu0 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD1: power-domain-cpu1 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD2: power-domain-cpu2 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD3: power-domain-cpu3 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD4: power-domain-cpu4 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD5: power-domain-cpu5 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD6: power-domain-cpu6 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD7: power-domain-cpu7 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> + };
>> +
>> + CLUSTER_PD: power-domain-cpu-cluster0 {
>> + #power-domain-cells = <0>;
>> + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
>> + };
>> + };
>> +
>> + soc: soc@0 {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0 0 0 0 0x10 0>;
>> + dma-ranges = <0 0 0 0 0x10 0>;
>> + compatible = "simple-bus";
>> +
>> + tcsr_mutex: hwlock@1f40000 {
>> + compatible = "qcom,tcsr-mutex";
>> + reg = <0x0 0x01f40000 0x0 0x40000>;
>> + #hwlock-cells = <1>;
>> + };
>> +
>> + pdc: interrupt-controller@b220000 {
>> + compatible = "qcom,sm4450-pdc", "qcom,pdc";
>
> Missing binding update
V2 patch will update binding.
>
>> + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
>> + qcom,pdc-ranges = <0 480 94>, <94 494 31>, <125 63 1>;
>> + #interrupt-cells = <2>;
>> + interrupt-parent = <&intc>;
>> + interrupt-controller;
>> + };
>> +
>> + intc: interrupt-controller@17200000 {
>> + compatible = "arm,gic-v3";
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + #redistributor-regions = <1>;
>> + redistributor-stride = <0x0 0x20000>;
>> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
>> + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
>
> Please align vertically.
V2 patch will align.
>
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
>> + };
>> +
>> + timer@17420000 {
>> + compatible = "arm,armv7-timer-mem";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0 0 0x20000000>;
>> + reg = <0x0 0x17420000 0x0 0x1000>;
>> + clock-frequency = <19200000>;
>> +
>> + frame@17421000 {
>> + frame-number = <0>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
>
> Please align vertically.
V2 patch will align.
>
>> + reg = <0x17421000 0x1000>,
>> + <0x17422000 0x1000>;
>> + };
>> +
>> + frame@17423000 {
>> + frame-number = <1>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x17423000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@17425000 {
>> + frame-number = <2>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x17425000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@17427000 {
>> + frame-number = <3>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x17427000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@17429000 {
>> + frame-number = <4>;
>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x17429000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@1742b000 {
>> + frame-number = <5>;
>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x1742b000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@1742d000 {
>> + frame-number = <6>;
>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x1742d000 0x1000>;
>> + status = "disabled";
>> + };
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
>> IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
>> IRQ_TYPE_LEVEL_LOW)>,
>
> Please align vertically.
V2 patch will align.
>
>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
>> IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
>> IRQ_TYPE_LEVEL_LOW)>;
>> + clock-frequency = <19200000>;
>> + };
>> +};
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI
2023-07-19 10:22 ` Krzysztof Kozlowski
@ 2023-07-21 1:59 ` Tengfei Fan
0 siblings, 0 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-21 1:59 UTC (permalink / raw)
To: Krzysztof Kozlowski, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
在 7/19/2023 6:22 PM, Krzysztof Kozlowski 写道:
> On 19/07/2023 12:01, Tengfei Fan wrote:
>> This add based DTSI for SM4450 SoC and includes base description of
>> CPUs and interrupt-controller which helps to boot to shell with
>> console on boards with this SoC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>
> Thank you for your patch. There is something to discuss/improve.
>
>
>> ---
>> arch/arm64/boot/dts/qcom/sm4450.dtsi | 435 +++++++++++++++++++++++++++
>> 1 file changed, 435 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sm4450.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
>> new file mode 100644
>> index 000000000000..ab14aecbdcea
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
>> @@ -0,0 +1,435 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen { };
>> +
>> + clocks{
>> + xo_board: xo_board {
>
> Please start your work from scratch from mainline SoC, so we won't have
> to point you all these obvious issues which we fixed long time ago. Just
> pick the most recent SoC, like SM8550.
sure will pick like SM8550 and reference it.
>
>> + compatible = "fixed-clock";
>> + clock-frequency = <76800000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + sleep_clk: sleep_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <32000>;
>> + #clock-cells = <0>;
>> + };
>> + };
>
> ...
>
>> + };
>> + };
>> +
>> + firmware {
>> + scm: scm {
>> + compatible = "qcom,scm-sm4450", "qcom,scm";
>
> Undocumented compatible. If you plan to document it further, then please
> check if your patches are correctly ordered. Bindings are always before
> their users.
will remove this SCM node due to haven't use currently, and will check
other undocumented compatible and document it.
>
>> + #reset-cells = <1>;
>> + };
>> + };
>> +
>> + memory@a0000000 {
>> + device_type = "memory";
>> + /* We expect the bootloader to fill in the size */
>> + reg = <0x0 0xa0000000 0x0 0x0>;
>> + };
>> +
>> + pmu {
>> + compatible = "arm,armv8-pmuv3";
>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-1.0";
>> + method = "smc";
>> +
>> + CPU_PD0: power-domain-cpu0 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD1: power-domain-cpu1 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD2: power-domain-cpu2 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD3: power-domain-cpu3 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD4: power-domain-cpu4 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD5: power-domain-cpu5 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD6: power-domain-cpu6 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD7: power-domain-cpu7 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> + };
>> +
>> + CLUSTER_PD: power-domain-cpu-cluster0 {
>> + #power-domain-cells = <0>;
>> + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
>> + };
>> + };
>> +
>> + soc: soc@0 {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0 0 0 0 0x10 0>;
>> + dma-ranges = <0 0 0 0 0x10 0>;
>> + compatible = "simple-bus";
>> +
>> + tcsr_mutex: hwlock@1f40000 {
>> + compatible = "qcom,tcsr-mutex";
>> + reg = <0x0 0x01f40000 0x0 0x40000>;
>> + #hwlock-cells = <1>;
>> + };
>> +
>> + pdc: interrupt-controller@b220000 {
>> + compatible = "qcom,sm4450-pdc", "qcom,pdc";
>> + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
>> + qcom,pdc-ranges = <0 480 94>, <94 494 31>, <125 63 1>;
>> + #interrupt-cells = <2>;
>> + interrupt-parent = <&intc>;
>> + interrupt-controller;
>> + };
>> +
>> + intc: interrupt-controller@17200000 {
>> + compatible = "arm,gic-v3";
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + #redistributor-regions = <1>;
>> + redistributor-stride = <0x0 0x20000>;
>> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
>> + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
>
> reg is always after compatible. Then ranges follow.
will update sequence.
>
> Also, indentation looks not aligned here.
V2 patch will aligne.
>
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
>> + };
>> +
>> + timer@17420000 {
>> + compatible = "arm,armv7-timer-mem";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0 0 0x20000000>;
>> + reg = <0x0 0x17420000 0x0 0x1000>;
>
> Same problem... some weird ordering.
will update sequence.
>
>> + clock-frequency = <19200000>;
>
> Are you sure this property is allowed in new designs?
will remove this property.
>
>> +
>> + frame@17421000 {
>> + frame-number = <0>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x17421000 0x1000>,
>> + <0x17422000 0x1000>;
>> + };
>> +
>> + frame@17423000 {
>> + frame-number = <1>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x17423000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@17425000 {
>> + frame-number = <2>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x17425000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@17427000 {
>> + frame-number = <3>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x17427000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@17429000 {
>> + frame-number = <4>;
>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x17429000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@1742b000 {
>> + frame-number = <5>;
>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x1742b000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@1742d000 {
>> + frame-number = <6>;
>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x1742d000 0x1000>;
>> + status = "disabled";
>> + };
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>> + clock-frequency = <19200000>;
>
> Are you sure this property is allowed in new designs?
will remove this property.
>
>> + };
>> +};
>
> Best regards,
> Krzysztof
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI
2023-07-20 7:54 ` Konrad Dybcio
@ 2023-07-21 2:03 ` Tengfei Fan
0 siblings, 0 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-21 2:03 UTC (permalink / raw)
To: Konrad Dybcio, andersson, robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
在 7/20/2023 3:54 PM, Konrad Dybcio 写道:
> On 19.07.2023 12:01, Tengfei Fan wrote:
>> This add based DTSI for SM4450 SoC and includes base description of
>> CPUs and interrupt-controller which helps to boot to shell with
>> console on boards with this SoC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
> [...]
>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/gpio/gpio.h>
> Please sort them alphabetically
V2 patch will resort them.
>
>> +
>> +/ {
>> + interrupt-parent = <&intc>;
>> +
> [...]
>
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + CPU0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo";
> Please post dmesg | grep '\[', this is probably a standard ARM core.
sure, will do and update this compatible.
>
>> + reg = <0x0 0x0>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_0>;
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + #cooling-cells = <2>;
>> + L2_0: l2-cache {
> Missing a newline before subnodes
V2 patch will add newline.
>
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + L3_0: l3-cache {
> Ditto
V2 patch will add newline.
>
>> + compatible = "cache";
>> + cache-level = <3>;
>> + cache-unified;
>> + };
>> + };
>> + };
> [...]
>
>> +
>> + intc: interrupt-controller@17200000 {
>> + compatible = "arm,gic-v3";
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + #redistributor-regions = <1>;
>> + redistributor-stride = <0x0 0x20000>;
>> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
>> + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
> Misasligned
V2 patch will align.
>
> also, please move reg and interrupts after compatible
V2 patch will resort.
>
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
>> + };
>> +
>> + timer@17420000 {
>> + compatible = "arm,armv7-timer-mem";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0 0 0x20000000>;
>> + reg = <0x0 0x17420000 0x0 0x1000>;
>> + clock-frequency = <19200000>;
> Drop clock-frequency
V2 patch will Drop this clock-frequency node.
>
> [...]
>
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> Misaligned
V2 patch will align.
>
>> + clock-frequency = <19200000>;
> Drop
V2 patch will drop.
>
> Konrad
>> + };
>> +};
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/5] arm64: dts: qcom: Add base SM4450 QRD DTS
2023-07-19 10:17 ` Dmitry Baryshkov
@ 2023-07-21 2:07 ` Tengfei Fan
0 siblings, 0 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-21 2:07 UTC (permalink / raw)
To: Dmitry Baryshkov, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
在 7/19/2023 6:17 PM, Dmitry Baryshkov 写道:
> On 19/07/2023 13:01, Tengfei Fan wrote:
>> Add DTS for Qualcomm QRD platform which uses SM4450 SoC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 ++++++++++++++++++
>> 2 files changed, 19 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile
>> b/arch/arm64/boot/dts/qcom/Makefile
>> index 337abc4ceb17..a0cfd37e674b 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -215,3 +215,4 @@ dtb-$(CONFIG_ARCH_QCOM) +=
>> sm8450-sony-xperia-nagara-pdx223.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
>
> You guess, this should be sorted.
sure, will resorted.
>
>> diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>> b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>> new file mode 100644
>> index 000000000000..851a6761a6ea
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>> @@ -0,0 +1,18 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "sm4450.dtsi"
>> +/ {
>> + model = "Qualcomm Technologies, Inc. SM4450 QRD";
>> + compatible = "qcom,sm4450-qrd", "qcom,sm4450";
>> +
>> + aliases { };
>> +
>> + chosen {
>> + bootargs = " ";
>
> Do you need this?
V2 patch will remove bootargs = " ".
>
>> + };
>> +};
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/5] arm64: dts: qcom: Add base SM4450 QRD DTS
2023-07-19 10:23 ` Krzysztof Kozlowski
@ 2023-07-21 2:18 ` Tengfei Fan
0 siblings, 0 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-21 2:18 UTC (permalink / raw)
To: Krzysztof Kozlowski, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
在 7/19/2023 6:23 PM, Krzysztof Kozlowski 写道:
> On 19/07/2023 12:01, Tengfei Fan wrote:
>> Add DTS for Qualcomm QRD platform which uses SM4450 SoC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 ++++++++++++++++++
>> 2 files changed, 19 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 337abc4ceb17..a0cfd37e674b 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -215,3 +215,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
>
> Messed order.
V2 patch will order this.
>
>> diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>> new file mode 100644
>> index 000000000000..851a6761a6ea
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>> @@ -0,0 +1,18 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "sm4450.dtsi"
>> +/ {
>> + model = "Qualcomm Technologies, Inc. SM4450 QRD";
>> + compatible = "qcom,sm4450-qrd", "qcom,sm4450";
>
> Missing bindings.
[PATCH 4/5] updated bindings, will move [PATCH 4/5] in front of this
patch[PATCH 2/5].
>
>> +
>> + aliases { };
>> +
>> + chosen {
>> + bootargs = " ";
>
> Drop, useless.
Will Drop bootargs="", only chosen empty.
>
> OTOH, you miss here several properties. This is not even a basic board -
> nothing works here, right? Please submit when you have at least serial
> working.
We tested DCC console done(CONFIG_HVC_DCC), currnty DCC console can be
used after enable CONFIG_HVC_DCC and add some reasonable dcc properties,
so want to get review for this patch.
>
>> + };
>> +};
>
> Best regards,
> Krzysztof
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/5] dt-bindings: firmware: scm: Add SM4450
2023-07-19 10:16 ` Dmitry Baryshkov
@ 2023-07-21 2:19 ` Tengfei Fan
0 siblings, 0 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-21 2:19 UTC (permalink / raw)
To: Dmitry Baryshkov, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
在 7/19/2023 6:16 PM, Dmitry Baryshkov 写道:
> On 19/07/2023 13:01, Tengfei Fan wrote:
>> Add compatible for SM4450 SoCs.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
>> b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
>> index bdbee58a542b..f02f0815bece 100644
>> --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
>> +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
>> @@ -62,6 +62,7 @@ properties:
>> - qcom,scm-sm8450
>> - qcom,scm-sm8550
>> - qcom,scm-qcs404
>> + - qcom,scm-sm4450
>
> Please keep this list sorted.
V2 patch will resort.
>
>> - const: qcom,scm
>> clocks:
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/5] dt-bindings: firmware: scm: Add SM4450
2023-07-19 10:24 ` Krzysztof Kozlowski
@ 2023-07-21 2:19 ` Tengfei Fan
0 siblings, 0 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-21 2:19 UTC (permalink / raw)
To: Krzysztof Kozlowski, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
在 7/19/2023 6:24 PM, Krzysztof Kozlowski 写道:
> On 19/07/2023 12:01, Tengfei Fan wrote:
>> Add compatible for SM4450 SoCs.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
>> index bdbee58a542b..f02f0815bece 100644
>> --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
>> +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
>> @@ -62,6 +62,7 @@ properties:
>> - qcom,scm-sm8450
>> - qcom,scm-sm8550
>> - qcom,scm-qcs404
>> + - qcom,scm-sm4450
>
> Please keep things sorted...
V2 patch will resort.
>
> Best regards,
> Krzysztof
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 4/5] dt-bindings: arm: qcom: Document SM4450 SoC and boards
2023-07-19 10:15 ` Dmitry Baryshkov
@ 2023-07-21 2:20 ` Tengfei Fan
0 siblings, 0 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-21 2:20 UTC (permalink / raw)
To: Dmitry Baryshkov, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
在 7/19/2023 6:15 PM, Dmitry Baryshkov 写道:
> On 19/07/2023 13:01, Tengfei Fan wrote:
>> Document the SM8450 SoC binding and also the boards using it.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml
>> b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index 450f616774e0..691e66612872 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -83,6 +83,7 @@ description: |
>> sm8350
>> sm8450
>> sm8550
>> + sm4450
>
> Please sort properly
V2 patch will resort.
>
>> The 'board' element must be one of the following strings:
>> @@ -976,6 +977,11 @@ properties:
>> - qcom,sm8550-qrd
>> - const: qcom,sm8550
>> + - items:
>> + - enum:
>> + - qcom,sm4450-qrd
>> + - const: qcom,sm4450
>> +
>
> And here
V2 patch will resort.
>
>> # Board compatibles go above
>> qcom,msm-id:
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 4/5] dt-bindings: arm: qcom: Document SM4450 SoC and boards
2023-07-19 10:24 ` Krzysztof Kozlowski
@ 2023-07-21 2:24 ` Tengfei Fan
0 siblings, 0 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-21 2:24 UTC (permalink / raw)
To: Krzysztof Kozlowski, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
在 7/19/2023 6:24 PM, Krzysztof Kozlowski 写道:
> On 19/07/2023 12:01, Tengfei Fan wrote:
>> Document the SM8450 SoC binding and also the boards using it.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index 450f616774e0..691e66612872 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -83,6 +83,7 @@ description: |
>> sm8350
>> sm8450
>> sm8550
>> + sm4450
>>
>> The 'board' element must be one of the following strings:
>>
>> @@ -976,6 +977,11 @@ properties:
>> - qcom,sm8550-qrd
>> - const: qcom,sm8550
>>
>> + - items:
>> + - enum:
>> + - qcom,sm4450-qrd
>> + - const: qcom,sm4450
>
> No, really...
V2 patch will resort it.
>
> Best regards,
> Krzysztof
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 5/5] soc: qcom: socinfo: add SM4450 ID
2023-07-19 10:26 ` Krzysztof Kozlowski
@ 2023-07-21 2:26 ` Tengfei Fan
0 siblings, 0 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-21 2:26 UTC (permalink / raw)
To: Krzysztof Kozlowski, Dmitry Baryshkov, andersson, konrad.dybcio,
robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
在 7/19/2023 6:26 PM, Krzysztof Kozlowski 写道:
> On 19/07/2023 12:15, Dmitry Baryshkov wrote:
>> On 19/07/2023 13:01, Tengfei Fan wrote:
>>> Add the ID for the Qualcomm SM4450 SoC.
>>>
>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>> ---
>>> drivers/soc/qcom/socinfo.c | 1 +
>>> include/dt-bindings/arm/qcom,ids.h | 2 ++
>>> 2 files changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
>>> index 4d49945b3a35..fa5e4c54207a 100644
>>> --- a/drivers/soc/qcom/socinfo.c
>>> +++ b/drivers/soc/qcom/socinfo.c
>>> @@ -415,6 +415,7 @@ static const struct soc_id soc_id[] = {
>>> { qcom_board_id(IPQ5312) },
>>> { qcom_board_id(IPQ5302) },
>>> { qcom_board_id(IPQ5300) },
>>> + { qcom_board_id(SM4450) },
>>> };
>>>
>>> static const char *socinfo_machine(struct device *dev, unsigned int id)
>>> diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
>>> index bcbe9ee2cdaf..6201bfb1405e 100644
>>> --- a/include/dt-bindings/arm/qcom,ids.h
>>> +++ b/include/dt-bindings/arm/qcom,ids.h
>>> @@ -2,6 +2,7 @@
>>> /*
>>> * Copyright (c) 2015, The Linux Foundation. All rights reserved.
>>> * Copyright (c) 2022 Linaro Ltd
>>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>>
>> I wonder whether a single define is copyrightable.
>
> If you carefully choose a place, like out of order, then probably it is
> a creative work. :)
V2 patch will remove this copyrithtable.
>
> Best regards,
> Krzysztof
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 5/5] soc: qcom: socinfo: add SM4450 ID
2023-07-19 10:25 ` Krzysztof Kozlowski
@ 2023-07-21 2:27 ` Tengfei Fan
0 siblings, 0 replies; 29+ messages in thread
From: Tengfei Fan @ 2023-07-21 2:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: quic_tsoni, quic_shashim, quic_kaushalk, quic_tdas,
quic_tingweiz, quic_aiquny, linux-arm-msm, devicetree,
linux-kernel
在 7/19/2023 6:25 PM, Krzysztof Kozlowski 写道:
> On 19/07/2023 12:01, Tengfei Fan wrote:
>> Add the ID for the Qualcomm SM4450 SoC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> drivers/soc/qcom/socinfo.c | 1 +
>> include/dt-bindings/arm/qcom,ids.h | 2 ++
>
> Bindings are always separate patches.
V2 patch will separate.
>
>> 2 files changed, 3 insertions(+)
>>
>> diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
>> index 4d49945b3a35..fa5e4c54207a 100644
>> --- a/drivers/soc/qcom/socinfo.c
>> +++ b/drivers/soc/qcom/socinfo.c
>> @@ -415,6 +415,7 @@ static const struct soc_id soc_id[] = {
>> { qcom_board_id(IPQ5312) },
>> { qcom_board_id(IPQ5302) },
>> { qcom_board_id(IPQ5300) },
>> + { qcom_board_id(SM4450) },
>> };
>>
>> static const char *socinfo_machine(struct device *dev, unsigned int id)
>> diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
>> index bcbe9ee2cdaf..6201bfb1405e 100644
>> --- a/include/dt-bindings/arm/qcom,ids.h
>> +++ b/include/dt-bindings/arm/qcom,ids.h
>> @@ -2,6 +2,7 @@
>> /*
>> * Copyright (c) 2015, The Linux Foundation. All rights reserved.
>> * Copyright (c) 2022 Linaro Ltd
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>> * Author: Krzysztof Kozlowski <krzk@kernel.org> based on previous work of Kumar Gala.
>> */
>> #ifndef _DT_BINDINGS_ARM_QCOM_IDS_H
>> @@ -259,6 +260,7 @@
>> #define QCOM_ID_IPQ5312 594
>> #define QCOM_ID_IPQ5302 595
>> #define QCOM_ID_IPQ5300 624
>> +#define QCOM_ID_SM4450 568
>
> No, come on...
V2 patch will resort this.
>
> Best regards,
> Krzysztof
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2023-07-21 2:27 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-19 10:01 [PATCH 0/5] soc: qcom: Add support for SM4450 Tengfei Fan
2023-07-19 10:01 ` [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI Tengfei Fan
2023-07-19 10:14 ` Dmitry Baryshkov
2023-07-21 1:53 ` Tengfei Fan
2023-07-19 10:22 ` Krzysztof Kozlowski
2023-07-21 1:59 ` Tengfei Fan
2023-07-20 7:54 ` Konrad Dybcio
2023-07-21 2:03 ` Tengfei Fan
2023-07-19 10:01 ` [PATCH 2/5] arm64: dts: qcom: Add base SM4450 QRD DTS Tengfei Fan
2023-07-19 10:17 ` Dmitry Baryshkov
2023-07-21 2:07 ` Tengfei Fan
2023-07-19 10:23 ` Krzysztof Kozlowski
2023-07-21 2:18 ` Tengfei Fan
2023-07-19 10:01 ` [PATCH 3/5] dt-bindings: firmware: scm: Add SM4450 Tengfei Fan
2023-07-19 10:16 ` Dmitry Baryshkov
2023-07-21 2:19 ` Tengfei Fan
2023-07-19 10:24 ` Krzysztof Kozlowski
2023-07-21 2:19 ` Tengfei Fan
2023-07-19 10:01 ` [PATCH 4/5] dt-bindings: arm: qcom: Document SM4450 SoC and boards Tengfei Fan
2023-07-19 10:15 ` Dmitry Baryshkov
2023-07-21 2:20 ` Tengfei Fan
2023-07-19 10:24 ` Krzysztof Kozlowski
2023-07-21 2:24 ` Tengfei Fan
2023-07-19 10:01 ` [PATCH 5/5] soc: qcom: socinfo: add SM4450 ID Tengfei Fan
2023-07-19 10:15 ` Dmitry Baryshkov
2023-07-19 10:26 ` Krzysztof Kozlowski
2023-07-21 2:26 ` Tengfei Fan
2023-07-19 10:25 ` Krzysztof Kozlowski
2023-07-21 2:27 ` Tengfei Fan
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