From: Emil Renner Berthing <emil.renner.berthing@canonical.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Emil Renner Berthing <kernel@esmil.dk>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Cristian Ciocaltea <cristian.ciocaltea@collabora.com>, Geert Uytterhoeven <geert@linux-m68k.org> Subject: [PATCH v2 3/8] riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs Date: Thu, 30 Nov 2023 16:19:27 +0100 [thread overview] Message-ID: <20231130151932.729708-4-emil.renner.berthing@canonical.com> (raw) In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> From: Emil Renner Berthing <kernel@esmil.dk> The StarFive JH7100 SoC has non-coherent device DMAs, so mark the soc bus as such. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index a40a8544b860..7c1009428c1f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -144,6 +144,7 @@ soc { interrupt-parent = <&plic>; #address-cells = <2>; #size-cells = <2>; + dma-noncoherent; ranges; clint: clint@2000000 { -- 2.40.1
WARNING: multiple messages have this Message-ID (diff)
From: Emil Renner Berthing <emil.renner.berthing@canonical.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Emil Renner Berthing <kernel@esmil.dk>, Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Geert Uytterhoeven <geert@linux-m68k.org> Subject: [PATCH v2 3/8] riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs Date: Thu, 30 Nov 2023 16:19:27 +0100 [thread overview] Message-ID: <20231130151932.729708-4-emil.renner.berthing@canonical.com> (raw) In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> From: Emil Renner Berthing <kernel@esmil.dk> The StarFive JH7100 SoC has non-coherent device DMAs, so mark the soc bus as such. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index a40a8544b860..7c1009428c1f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -144,6 +144,7 @@ soc { interrupt-parent = <&plic>; #address-cells = <2>; #size-cells = <2>; + dma-noncoherent; ranges; clint: clint@2000000 { -- 2.40.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-11-30 15:20 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 1/8] riscv: errata: Add StarFive JH7100 errata Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-12-06 17:09 ` Palmer Dabbelt 2023-12-06 17:09 ` Palmer Dabbelt 2023-11-30 15:19 ` [PATCH v2 2/8] riscv: dts: starfive: Group tuples in interrupt properties Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing [this message] 2023-11-30 15:19 ` [PATCH v2 3/8] riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 4/8] riscv: dts: starfive: Add JH7100 cache controller Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 5/8] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 6/8] riscv: dts: starfive: Add JH7100 MMC nodes Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 7/8] riscv: dts: starfive: Enable SD-card on JH7100 boards Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 8/8] riscv: dts: starfive: Enable SDIO wifi " Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-12-13 15:42 ` (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree Conor Dooley 2023-12-13 15:42 ` Conor Dooley 2023-12-13 15:51 ` Geert Uytterhoeven 2023-12-13 15:51 ` Geert Uytterhoeven 2023-12-15 19:13 ` Emil Renner Berthing 2023-12-15 19:13 ` Emil Renner Berthing 2023-12-13 15:53 ` Conor Dooley 2023-12-13 15:53 ` Conor Dooley
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