From: Emil Renner Berthing <emil.renner.berthing@canonical.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Emil Renner Berthing <kernel@esmil.dk>, Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Cristian Ciocaltea <cristian.ciocaltea@collabora.com>, Geert Uytterhoeven <geert@linux-m68k.org> Subject: [PATCH v2 5/8] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards Date: Thu, 30 Nov 2023 16:19:29 +0100 [thread overview] Message-ID: <20231130151932.729708-6-emil.renner.berthing@canonical.com> (raw) In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> The StarFive JH7100 SoC has non-coherent device DMAs, but most drivers expect to be able to allocate coherent memory for DMA descriptors and such. However on the JH7100 DDR memory appears twice in the physical memory map, once cached and once uncached: 0x00_8000_0000 - 0x08_7fff_ffff : Off chip DDR memory, cached 0x10_0000_0000 - 0x17_ffff_ffff : Off chip DDR memory, uncached To use this uncached region we create a global DMA memory pool there and reserve the corresponding area in the cached region. However the uncached region is fully above the 32bit address limit, so add a dma-ranges map so the DMA address used for peripherals is still in the regular cached region below the limit. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..3af88e6970a3 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -39,6 +39,30 @@ led-ack { label = "ack"; }; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dma-reserved@fa000000 { + reg = <0x0 0xfa000000 0x0 0x1000000>; + no-map; + }; + + linux,dma@107a000000 { + compatible = "shared-dma-pool"; + reg = <0x10 0x7a000000 0x0 0x1000000>; + no-map; + linux,dma-default; + }; + }; + + soc { + dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>, + <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>, + <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>; + }; }; &gpio { -- 2.40.1
WARNING: multiple messages have this Message-ID (diff)
From: Emil Renner Berthing <emil.renner.berthing@canonical.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Emil Renner Berthing <kernel@esmil.dk>, Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Geert Uytterhoeven <geert@linux-m68k.org> Subject: [PATCH v2 5/8] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards Date: Thu, 30 Nov 2023 16:19:29 +0100 [thread overview] Message-ID: <20231130151932.729708-6-emil.renner.berthing@canonical.com> (raw) In-Reply-To: <20231130151932.729708-1-emil.renner.berthing@canonical.com> The StarFive JH7100 SoC has non-coherent device DMAs, but most drivers expect to be able to allocate coherent memory for DMA descriptors and such. However on the JH7100 DDR memory appears twice in the physical memory map, once cached and once uncached: 0x00_8000_0000 - 0x08_7fff_ffff : Off chip DDR memory, cached 0x10_0000_0000 - 0x17_ffff_ffff : Off chip DDR memory, uncached To use this uncached region we create a global DMA memory pool there and reserve the corresponding area in the cached region. However the uncached region is fully above the 32bit address limit, so add a dma-ranges map so the DMA address used for peripherals is still in the regular cached region below the limit. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..3af88e6970a3 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -39,6 +39,30 @@ led-ack { label = "ack"; }; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dma-reserved@fa000000 { + reg = <0x0 0xfa000000 0x0 0x1000000>; + no-map; + }; + + linux,dma@107a000000 { + compatible = "shared-dma-pool"; + reg = <0x10 0x7a000000 0x0 0x1000000>; + no-map; + linux,dma-default; + }; + }; + + soc { + dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>, + <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>, + <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>; + }; }; &gpio { -- 2.40.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-11-30 15:20 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-11-30 15:19 [PATCH v2 0/8] Add JH7100 errata and update device tree Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 1/8] riscv: errata: Add StarFive JH7100 errata Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-12-06 17:09 ` Palmer Dabbelt 2023-12-06 17:09 ` Palmer Dabbelt 2023-11-30 15:19 ` [PATCH v2 2/8] riscv: dts: starfive: Group tuples in interrupt properties Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 3/8] riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 4/8] riscv: dts: starfive: Add JH7100 cache controller Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing [this message] 2023-11-30 15:19 ` [PATCH v2 5/8] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 6/8] riscv: dts: starfive: Add JH7100 MMC nodes Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 7/8] riscv: dts: starfive: Enable SD-card on JH7100 boards Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-11-30 15:19 ` [PATCH v2 8/8] riscv: dts: starfive: Enable SDIO wifi " Emil Renner Berthing 2023-11-30 15:19 ` Emil Renner Berthing 2023-12-13 15:42 ` (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree Conor Dooley 2023-12-13 15:42 ` Conor Dooley 2023-12-13 15:51 ` Geert Uytterhoeven 2023-12-13 15:51 ` Geert Uytterhoeven 2023-12-15 19:13 ` Emil Renner Berthing 2023-12-15 19:13 ` Emil Renner Berthing 2023-12-13 15:53 ` Conor Dooley 2023-12-13 15:53 ` Conor Dooley
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