* [PATCH v2 0/5] arm64: PMU updates
@ 2021-12-14 14:16 ` Robin Murphy
0 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:16 UTC (permalink / raw)
To: will, robh+dt, mark.rutland
Cc: catalin.marinas, suzuki.poulose, thierry.reding,
linux-arm-kernel, devicetree
Hi all,
Here's v2, with the DSU binding actually finished (oh the shame...) and
the NVIDIA PMU patch pulled in to benefit from the cleanup and keep
things manageably together. The initial binding patch from v1 is no
longer included since Rob has picked it up separately.
Refactoring arm_pmu's probing to be more modular turns out to be a
substantial yak to shave, so in the end I decided it *is* worth
implementing Mark's macro suggestion now - after all, it can simply be
converted from a function template to a structure template as and when
the time comes.
Cheers,
Robin.
Robin Murphy (4):
arm64: perf: Simplify registration boilerplate
arm64: perf: Support new DT compatibles
dt-bindings: perf: Convert Arm DSU to schema
dt-bindings: perf: Add compatible for Arm DSU-110
Thierry Reding (1):
arm64: perf: Support Denver and Carmel PMUs
.../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 -----
.../devicetree/bindings/perf/arm,dsu-pmu.yaml | 45 +++++++
arch/arm64/kernel/perf_event.c | 111 +++++++-----------
3 files changed, 88 insertions(+), 95 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
--
2.28.0.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v2 1/5] arm64: perf: Support Denver and Carmel PMUs
2021-12-14 14:16 ` Robin Murphy
@ 2021-12-14 14:16 ` Robin Murphy
-1 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:16 UTC (permalink / raw)
To: will, robh+dt, mark.rutland
Cc: catalin.marinas, suzuki.poulose, thierry.reding,
linux-arm-kernel, devicetree, Thierry Reding
From: Thierry Reding <treding@nvidia.com>
Add support for the NVIDIA Denver and Carmel PMUs using the generic
PMUv3 event map for now.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
[ rm: reorder entries alphabetically ]
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
v2: Newly picked up
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index b4044469527e..035da52e04bf 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
armv8_vulcan_map_event);
}
+static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
+ armv8_pmuv3_map_event);
+}
+
+static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
+ armv8_pmuv3_map_event);
+}
+
static const struct of_device_id armv8_pmu_of_device_ids[] = {
{.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
{.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init},
@@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
{.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init},
{.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
{.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
+ {.compatible = "nvidia,carmel-pmu", .data = armv8_carmel_pmu_init},
+ {.compatible = "nvidia,denver-pmu", .data = armv8_denver_pmu_init},
{},
};
--
2.28.0.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v2 1/5] arm64: perf: Support Denver and Carmel PMUs
@ 2021-12-14 14:16 ` Robin Murphy
0 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:16 UTC (permalink / raw)
To: will, robh+dt, mark.rutland
Cc: catalin.marinas, suzuki.poulose, thierry.reding,
linux-arm-kernel, devicetree, Thierry Reding
From: Thierry Reding <treding@nvidia.com>
Add support for the NVIDIA Denver and Carmel PMUs using the generic
PMUv3 event map for now.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
[ rm: reorder entries alphabetically ]
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
v2: Newly picked up
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index b4044469527e..035da52e04bf 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
armv8_vulcan_map_event);
}
+static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
+ armv8_pmuv3_map_event);
+}
+
+static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
+ armv8_pmuv3_map_event);
+}
+
static const struct of_device_id armv8_pmu_of_device_ids[] = {
{.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
{.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init},
@@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
{.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init},
{.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
{.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
+ {.compatible = "nvidia,carmel-pmu", .data = armv8_carmel_pmu_init},
+ {.compatible = "nvidia,denver-pmu", .data = armv8_denver_pmu_init},
{},
};
--
2.28.0.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 2/5] arm64: perf: Simplify registration boilerplate
2021-12-14 14:16 ` Robin Murphy
@ 2021-12-14 14:16 ` Robin Murphy
-1 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:16 UTC (permalink / raw)
To: will, robh+dt, mark.rutland
Cc: catalin.marinas, suzuki.poulose, thierry.reding,
linux-arm-kernel, devicetree
With the trend for per-core events moving to userspace JSON, registering
names for PMUv3 implementations is increasingly a pure boilerplate
exercise. Let's wrap things a step further so we can generate the basic
PMUv3 init function with a macro invocation, and reduce further new
addition to just 2 lines each.
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
arch/arm64/kernel/perf_event.c | 113 +++++++++------------------------
1 file changed, 31 insertions(+), 82 deletions(-)
v2: Rewrite per Mark's suggestion, cover new NVIDIA PMUs too
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 035da52e04bf..ed6d8cd2f88f 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1145,17 +1145,26 @@ static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
}
-static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3",
- armv8_pmuv3_map_event);
+#define PMUV3_INIT_SIMPLE(name) \
+static int name##_pmu_init(struct arm_pmu *cpu_pmu) \
+{ \
+ return armv8_pmu_init_nogroups(cpu_pmu, #name, armv8_pmuv3_map_event);\
}
-static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34",
- armv8_pmuv3_map_event);
-}
+PMUV3_INIT_SIMPLE(armv8_pmuv3)
+
+PMUV3_INIT_SIMPLE(armv8_cortex_a34)
+PMUV3_INIT_SIMPLE(armv8_cortex_a55)
+PMUV3_INIT_SIMPLE(armv8_cortex_a65)
+PMUV3_INIT_SIMPLE(armv8_cortex_a75)
+PMUV3_INIT_SIMPLE(armv8_cortex_a76)
+PMUV3_INIT_SIMPLE(armv8_cortex_a77)
+PMUV3_INIT_SIMPLE(armv8_cortex_a78)
+PMUV3_INIT_SIMPLE(armv8_neoverse_e1)
+PMUV3_INIT_SIMPLE(armv8_neoverse_n1)
+
+PMUV3_INIT_SIMPLE(armv8_nvidia_carmel)
+PMUV3_INIT_SIMPLE(armv8_nvidia_denver)
static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
{
@@ -1169,24 +1178,12 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
armv8_a53_map_event);
}
-static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55",
- armv8_pmuv3_map_event);
-}
-
static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
armv8_a57_map_event);
}
-static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65",
- armv8_pmuv3_map_event);
-}
-
static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
@@ -1199,42 +1196,6 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
armv8_a73_map_event);
}
-static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1",
- armv8_pmuv3_map_event);
-}
-
static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
@@ -1247,38 +1208,26 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
armv8_vulcan_map_event);
}
-static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
- armv8_pmuv3_map_event);
-}
-
static const struct of_device_id armv8_pmu_of_device_ids[] = {
- {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
- {.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init},
+ {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init},
+ {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init},
{.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init},
{.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
- {.compatible = "arm,cortex-a55-pmu", .data = armv8_a55_pmu_init},
+ {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init},
{.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
- {.compatible = "arm,cortex-a65-pmu", .data = armv8_a65_pmu_init},
+ {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init},
{.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
{.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init},
- {.compatible = "arm,cortex-a75-pmu", .data = armv8_a75_pmu_init},
- {.compatible = "arm,cortex-a76-pmu", .data = armv8_a76_pmu_init},
- {.compatible = "arm,cortex-a77-pmu", .data = armv8_a77_pmu_init},
- {.compatible = "arm,cortex-a78-pmu", .data = armv8_a78_pmu_init},
- {.compatible = "arm,neoverse-e1-pmu", .data = armv8_e1_pmu_init},
- {.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init},
+ {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init},
+ {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init},
+ {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init},
+ {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init},
+ {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init},
+ {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init},
{.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
{.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
- {.compatible = "nvidia,carmel-pmu", .data = armv8_carmel_pmu_init},
- {.compatible = "nvidia,denver-pmu", .data = armv8_denver_pmu_init},
+ {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init},
+ {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init},
{},
};
@@ -1301,7 +1250,7 @@ static int __init armv8_pmu_driver_init(void)
if (acpi_disabled)
return platform_driver_register(&armv8_pmu_driver);
else
- return arm_pmu_acpi_probe(armv8_pmuv3_init);
+ return arm_pmu_acpi_probe(armv8_pmuv3_pmu_init);
}
device_initcall(armv8_pmu_driver_init)
--
2.28.0.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v2 2/5] arm64: perf: Simplify registration boilerplate
@ 2021-12-14 14:16 ` Robin Murphy
0 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:16 UTC (permalink / raw)
To: will, robh+dt, mark.rutland
Cc: catalin.marinas, suzuki.poulose, thierry.reding,
linux-arm-kernel, devicetree
With the trend for per-core events moving to userspace JSON, registering
names for PMUv3 implementations is increasingly a pure boilerplate
exercise. Let's wrap things a step further so we can generate the basic
PMUv3 init function with a macro invocation, and reduce further new
addition to just 2 lines each.
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
arch/arm64/kernel/perf_event.c | 113 +++++++++------------------------
1 file changed, 31 insertions(+), 82 deletions(-)
v2: Rewrite per Mark's suggestion, cover new NVIDIA PMUs too
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 035da52e04bf..ed6d8cd2f88f 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1145,17 +1145,26 @@ static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
}
-static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3",
- armv8_pmuv3_map_event);
+#define PMUV3_INIT_SIMPLE(name) \
+static int name##_pmu_init(struct arm_pmu *cpu_pmu) \
+{ \
+ return armv8_pmu_init_nogroups(cpu_pmu, #name, armv8_pmuv3_map_event);\
}
-static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34",
- armv8_pmuv3_map_event);
-}
+PMUV3_INIT_SIMPLE(armv8_pmuv3)
+
+PMUV3_INIT_SIMPLE(armv8_cortex_a34)
+PMUV3_INIT_SIMPLE(armv8_cortex_a55)
+PMUV3_INIT_SIMPLE(armv8_cortex_a65)
+PMUV3_INIT_SIMPLE(armv8_cortex_a75)
+PMUV3_INIT_SIMPLE(armv8_cortex_a76)
+PMUV3_INIT_SIMPLE(armv8_cortex_a77)
+PMUV3_INIT_SIMPLE(armv8_cortex_a78)
+PMUV3_INIT_SIMPLE(armv8_neoverse_e1)
+PMUV3_INIT_SIMPLE(armv8_neoverse_n1)
+
+PMUV3_INIT_SIMPLE(armv8_nvidia_carmel)
+PMUV3_INIT_SIMPLE(armv8_nvidia_denver)
static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
{
@@ -1169,24 +1178,12 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
armv8_a53_map_event);
}
-static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55",
- armv8_pmuv3_map_event);
-}
-
static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
armv8_a57_map_event);
}
-static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65",
- armv8_pmuv3_map_event);
-}
-
static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
@@ -1199,42 +1196,6 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
armv8_a73_map_event);
}
-static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1",
- armv8_pmuv3_map_event);
-}
-
static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
@@ -1247,38 +1208,26 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
armv8_vulcan_map_event);
}
-static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
- armv8_pmuv3_map_event);
-}
-
-static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
-{
- return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
- armv8_pmuv3_map_event);
-}
-
static const struct of_device_id armv8_pmu_of_device_ids[] = {
- {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
- {.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init},
+ {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init},
+ {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init},
{.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init},
{.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
- {.compatible = "arm,cortex-a55-pmu", .data = armv8_a55_pmu_init},
+ {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init},
{.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
- {.compatible = "arm,cortex-a65-pmu", .data = armv8_a65_pmu_init},
+ {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init},
{.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
{.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init},
- {.compatible = "arm,cortex-a75-pmu", .data = armv8_a75_pmu_init},
- {.compatible = "arm,cortex-a76-pmu", .data = armv8_a76_pmu_init},
- {.compatible = "arm,cortex-a77-pmu", .data = armv8_a77_pmu_init},
- {.compatible = "arm,cortex-a78-pmu", .data = armv8_a78_pmu_init},
- {.compatible = "arm,neoverse-e1-pmu", .data = armv8_e1_pmu_init},
- {.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init},
+ {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init},
+ {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init},
+ {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init},
+ {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init},
+ {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init},
+ {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init},
{.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
{.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
- {.compatible = "nvidia,carmel-pmu", .data = armv8_carmel_pmu_init},
- {.compatible = "nvidia,denver-pmu", .data = armv8_denver_pmu_init},
+ {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init},
+ {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init},
{},
};
@@ -1301,7 +1250,7 @@ static int __init armv8_pmu_driver_init(void)
if (acpi_disabled)
return platform_driver_register(&armv8_pmu_driver);
else
- return arm_pmu_acpi_probe(armv8_pmuv3_init);
+ return arm_pmu_acpi_probe(armv8_pmuv3_pmu_init);
}
device_initcall(armv8_pmu_driver_init)
--
2.28.0.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 3/5] arm64: perf: Support new DT compatibles
2021-12-14 14:16 ` Robin Murphy
@ 2021-12-14 14:16 ` Robin Murphy
-1 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:16 UTC (permalink / raw)
To: will, robh+dt, mark.rutland
Cc: catalin.marinas, suzuki.poulose, thierry.reding,
linux-arm-kernel, devicetree
Wire up the new DT compatibles so we can present appropriate
PMU names to userspace for the latest and greatest CPUs.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v2: Use new macro template
arch/arm64/kernel/perf_event.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index ed6d8cd2f88f..4c1698f63f34 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1160,8 +1160,14 @@ PMUV3_INIT_SIMPLE(armv8_cortex_a75)
PMUV3_INIT_SIMPLE(armv8_cortex_a76)
PMUV3_INIT_SIMPLE(armv8_cortex_a77)
PMUV3_INIT_SIMPLE(armv8_cortex_a78)
+PMUV3_INIT_SIMPLE(armv9_cortex_a510)
+PMUV3_INIT_SIMPLE(armv9_cortex_a710)
+PMUV3_INIT_SIMPLE(armv8_cortex_x1)
+PMUV3_INIT_SIMPLE(armv9_cortex_x2)
PMUV3_INIT_SIMPLE(armv8_neoverse_e1)
PMUV3_INIT_SIMPLE(armv8_neoverse_n1)
+PMUV3_INIT_SIMPLE(armv9_neoverse_n2)
+PMUV3_INIT_SIMPLE(armv8_neoverse_v1)
PMUV3_INIT_SIMPLE(armv8_nvidia_carmel)
PMUV3_INIT_SIMPLE(armv8_nvidia_denver)
@@ -1222,8 +1228,14 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
{.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init},
{.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init},
{.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init},
+ {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init},
+ {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init},
+ {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init},
+ {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init},
{.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init},
{.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init},
+ {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init},
+ {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init},
{.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
{.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
{.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init},
--
2.28.0.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v2 3/5] arm64: perf: Support new DT compatibles
@ 2021-12-14 14:16 ` Robin Murphy
0 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:16 UTC (permalink / raw)
To: will, robh+dt, mark.rutland
Cc: catalin.marinas, suzuki.poulose, thierry.reding,
linux-arm-kernel, devicetree
Wire up the new DT compatibles so we can present appropriate
PMU names to userspace for the latest and greatest CPUs.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v2: Use new macro template
arch/arm64/kernel/perf_event.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index ed6d8cd2f88f..4c1698f63f34 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1160,8 +1160,14 @@ PMUV3_INIT_SIMPLE(armv8_cortex_a75)
PMUV3_INIT_SIMPLE(armv8_cortex_a76)
PMUV3_INIT_SIMPLE(armv8_cortex_a77)
PMUV3_INIT_SIMPLE(armv8_cortex_a78)
+PMUV3_INIT_SIMPLE(armv9_cortex_a510)
+PMUV3_INIT_SIMPLE(armv9_cortex_a710)
+PMUV3_INIT_SIMPLE(armv8_cortex_x1)
+PMUV3_INIT_SIMPLE(armv9_cortex_x2)
PMUV3_INIT_SIMPLE(armv8_neoverse_e1)
PMUV3_INIT_SIMPLE(armv8_neoverse_n1)
+PMUV3_INIT_SIMPLE(armv9_neoverse_n2)
+PMUV3_INIT_SIMPLE(armv8_neoverse_v1)
PMUV3_INIT_SIMPLE(armv8_nvidia_carmel)
PMUV3_INIT_SIMPLE(armv8_nvidia_denver)
@@ -1222,8 +1228,14 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
{.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init},
{.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init},
{.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init},
+ {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init},
+ {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init},
+ {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init},
+ {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init},
{.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init},
{.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init},
+ {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init},
+ {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init},
{.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
{.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
{.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init},
--
2.28.0.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 4/5] dt-bindings: perf: Convert Arm DSU to schema
2021-12-14 14:16 ` Robin Murphy
@ 2021-12-14 14:16 ` Robin Murphy
-1 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:16 UTC (permalink / raw)
To: will, robh+dt, mark.rutland
Cc: catalin.marinas, suzuki.poulose, thierry.reding,
linux-arm-kernel, devicetree
Convert the DSU binding to schema, as one does.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v2: Actually finish converting the thing to valid schema...
.../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------
.../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
2 files changed, 41 insertions(+), 27 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
deleted file mode 100644
index 6efabba530f1..000000000000
--- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
-
-ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
-with a shared L3 memory system, control logic and external interfaces to
-form a multicore cluster. The PMU enables to gather various statistics on
-the operations of the DSU. The PMU provides independent 32bit counters that
-can count any of the supported events, along with a 64bit cycle counter.
-The PMU is accessed via CPU system registers and has no MMIO component.
-
-** DSU PMU required properties:
-
-- compatible : should be one of :
-
- "arm,dsu-pmu"
-
-- interrupts : Exactly 1 SPI must be listed.
-
-- cpus : List of phandles for the CPUs connected to this DSU instance.
-
-
-** Example:
-
-dsu-pmu-0 {
- compatible = "arm,dsu-pmu";
- interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
- cpus = <&cpu_0>, <&cpu_1>;
-};
diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
new file mode 100644
index 000000000000..09ddeb6a3ccc
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021 Arm Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
+
+maintainers:
+ - Suzuki K Poulose <suzuki.poulose@arm.com>
+ - Robin Murphy <robin.murphy@arm.com>
+
+description:
+ ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
+ L3 memory system, control logic and external interfaces to form a multicore
+ cluster. The PMU enables gathering various statistics on the operation of the
+ DSU. The PMU provides independent 32-bit counters that can count any of the
+ supported events, along with a 64-bit cycle counter. The PMU is accessed via
+ CPU system registers and has no MMIO component.
+
+properties:
+ compatible:
+ const: arm,dsu-pmu
+
+ interrupts:
+ items:
+ - description: nCLUSTERPMUIRQ interrupt
+
+ cpus:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 8
+ description: List of phandles for the CPUs connected to this DSU instance.
+
+required:
+ - compatible
+ - interrupts
+ - cpus
+
+additionalProperties: false
--
2.28.0.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v2 4/5] dt-bindings: perf: Convert Arm DSU to schema
@ 2021-12-14 14:16 ` Robin Murphy
0 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:16 UTC (permalink / raw)
To: will, robh+dt, mark.rutland
Cc: catalin.marinas, suzuki.poulose, thierry.reding,
linux-arm-kernel, devicetree
Convert the DSU binding to schema, as one does.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v2: Actually finish converting the thing to valid schema...
.../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------
.../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
2 files changed, 41 insertions(+), 27 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
deleted file mode 100644
index 6efabba530f1..000000000000
--- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
-
-ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
-with a shared L3 memory system, control logic and external interfaces to
-form a multicore cluster. The PMU enables to gather various statistics on
-the operations of the DSU. The PMU provides independent 32bit counters that
-can count any of the supported events, along with a 64bit cycle counter.
-The PMU is accessed via CPU system registers and has no MMIO component.
-
-** DSU PMU required properties:
-
-- compatible : should be one of :
-
- "arm,dsu-pmu"
-
-- interrupts : Exactly 1 SPI must be listed.
-
-- cpus : List of phandles for the CPUs connected to this DSU instance.
-
-
-** Example:
-
-dsu-pmu-0 {
- compatible = "arm,dsu-pmu";
- interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
- cpus = <&cpu_0>, <&cpu_1>;
-};
diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
new file mode 100644
index 000000000000..09ddeb6a3ccc
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021 Arm Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
+
+maintainers:
+ - Suzuki K Poulose <suzuki.poulose@arm.com>
+ - Robin Murphy <robin.murphy@arm.com>
+
+description:
+ ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
+ L3 memory system, control logic and external interfaces to form a multicore
+ cluster. The PMU enables gathering various statistics on the operation of the
+ DSU. The PMU provides independent 32-bit counters that can count any of the
+ supported events, along with a 64-bit cycle counter. The PMU is accessed via
+ CPU system registers and has no MMIO component.
+
+properties:
+ compatible:
+ const: arm,dsu-pmu
+
+ interrupts:
+ items:
+ - description: nCLUSTERPMUIRQ interrupt
+
+ cpus:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 8
+ description: List of phandles for the CPUs connected to this DSU instance.
+
+required:
+ - compatible
+ - interrupts
+ - cpus
+
+additionalProperties: false
--
2.28.0.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v2 4/5] dt-bindings: perf: Convert Arm DSU to schema
2021-12-14 14:16 ` Robin Murphy
@ 2021-12-14 14:36 ` Suzuki K Poulose
-1 siblings, 0 replies; 30+ messages in thread
From: Suzuki K Poulose @ 2021-12-14 14:36 UTC (permalink / raw)
To: Robin Murphy, will, robh+dt, mark.rutland
Cc: catalin.marinas, thierry.reding, linux-arm-kernel, devicetree
On 14/12/2021 14:16, Robin Murphy wrote:
> Convert the DSU binding to schema, as one does.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>
> v2: Actually finish converting the thing to valid schema...
>
> .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------
> .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
> 2 files changed, 41 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> deleted file mode 100644
> index 6efabba530f1..000000000000
> --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
> -
> -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
> -with a shared L3 memory system, control logic and external interfaces to
> -form a multicore cluster. The PMU enables to gather various statistics on
> -the operations of the DSU. The PMU provides independent 32bit counters that
> -can count any of the supported events, along with a 64bit cycle counter.
> -The PMU is accessed via CPU system registers and has no MMIO component.
> -
> -** DSU PMU required properties:
> -
> -- compatible : should be one of :
> -
> - "arm,dsu-pmu"
> -
> -- interrupts : Exactly 1 SPI must be listed.
> -
> -- cpus : List of phandles for the CPUs connected to this DSU instance.
> -
> -
> -** Example:
> -
> -dsu-pmu-0 {
> - compatible = "arm,dsu-pmu";
> - interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
> - cpus = <&cpu_0>, <&cpu_1>;
> -};
> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> new file mode 100644
> index 000000000000..09ddeb6a3ccc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright 2021 Arm Ltd.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
> +
> +maintainers:
> + - Suzuki K Poulose <suzuki.poulose@arm.com>
> + - Robin Murphy <robin.murphy@arm.com>
> +
> +description:
> + ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
nit: DynamIQ. I understand I am the one to blame for ;-)
Rest looks good to me.
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v2 4/5] dt-bindings: perf: Convert Arm DSU to schema
@ 2021-12-14 14:36 ` Suzuki K Poulose
0 siblings, 0 replies; 30+ messages in thread
From: Suzuki K Poulose @ 2021-12-14 14:36 UTC (permalink / raw)
To: Robin Murphy, will, robh+dt, mark.rutland
Cc: catalin.marinas, thierry.reding, linux-arm-kernel, devicetree
On 14/12/2021 14:16, Robin Murphy wrote:
> Convert the DSU binding to schema, as one does.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>
> v2: Actually finish converting the thing to valid schema...
>
> .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------
> .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
> 2 files changed, 41 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> deleted file mode 100644
> index 6efabba530f1..000000000000
> --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
> -
> -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
> -with a shared L3 memory system, control logic and external interfaces to
> -form a multicore cluster. The PMU enables to gather various statistics on
> -the operations of the DSU. The PMU provides independent 32bit counters that
> -can count any of the supported events, along with a 64bit cycle counter.
> -The PMU is accessed via CPU system registers and has no MMIO component.
> -
> -** DSU PMU required properties:
> -
> -- compatible : should be one of :
> -
> - "arm,dsu-pmu"
> -
> -- interrupts : Exactly 1 SPI must be listed.
> -
> -- cpus : List of phandles for the CPUs connected to this DSU instance.
> -
> -
> -** Example:
> -
> -dsu-pmu-0 {
> - compatible = "arm,dsu-pmu";
> - interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
> - cpus = <&cpu_0>, <&cpu_1>;
> -};
> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> new file mode 100644
> index 000000000000..09ddeb6a3ccc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright 2021 Arm Ltd.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
> +
> +maintainers:
> + - Suzuki K Poulose <suzuki.poulose@arm.com>
> + - Robin Murphy <robin.murphy@arm.com>
> +
> +description:
> + ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
nit: DynamIQ. I understand I am the one to blame for ;-)
Rest looks good to me.
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 4/5] dt-bindings: perf: Convert Arm DSU to schema
2021-12-14 14:16 ` Robin Murphy
@ 2021-12-14 20:38 ` Rob Herring
-1 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-12-14 20:38 UTC (permalink / raw)
To: Robin Murphy
Cc: catalin.marinas, thierry.reding, mark.rutland, will, devicetree,
suzuki.poulose, robh+dt, linux-arm-kernel
On Tue, 14 Dec 2021 14:16:16 +0000, Robin Murphy wrote:
> Convert the DSU binding to schema, as one does.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>
> v2: Actually finish converting the thing to valid schema...
>
> .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------
> .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
> 2 files changed, 41 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 4/5] dt-bindings: perf: Convert Arm DSU to schema
@ 2021-12-14 20:38 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-12-14 20:38 UTC (permalink / raw)
To: Robin Murphy
Cc: catalin.marinas, thierry.reding, mark.rutland, will, devicetree,
suzuki.poulose, robh+dt, linux-arm-kernel
On Tue, 14 Dec 2021 14:16:16 +0000, Robin Murphy wrote:
> Convert the DSU binding to schema, as one does.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>
> v2: Actually finish converting the thing to valid schema...
>
> .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------
> .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
> 2 files changed, 41 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v2 5/5] dt-bindings: perf: Add compatible for Arm DSU-110
2021-12-14 14:16 ` Robin Murphy
@ 2021-12-14 14:16 ` Robin Murphy
-1 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:16 UTC (permalink / raw)
To: will, robh+dt, mark.rutland
Cc: catalin.marinas, suzuki.poulose, thierry.reding,
linux-arm-kernel, devicetree
DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
largely identical to the previous generation of DSUs, so we can treat it
as compatible, but it does have a a handful of extra IMP-DEF PMU events
to call its own. Thanks to the new notion of core complexes, the maximum
number of supported CPUs goes up as well.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v2: Also make it complete and valid
Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
index 09ddeb6a3ccc..7f31bcecedb5 100644
--- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
+++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
@@ -21,7 +21,11 @@ description:
properties:
compatible:
- const: arm,dsu-pmu
+ oneOf:
+ - const: arm,dsu-pmu
+ - items:
+ - const: arm,dsu-110-pmu
+ - const: arm,dsu-pmu
interrupts:
items:
@@ -30,7 +34,7 @@ properties:
cpus:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
- maxItems: 8
+ maxItems: 12
description: List of phandles for the CPUs connected to this DSU instance.
required:
--
2.28.0.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v2 5/5] dt-bindings: perf: Add compatible for Arm DSU-110
@ 2021-12-14 14:16 ` Robin Murphy
0 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:16 UTC (permalink / raw)
To: will, robh+dt, mark.rutland
Cc: catalin.marinas, suzuki.poulose, thierry.reding,
linux-arm-kernel, devicetree
DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
largely identical to the previous generation of DSUs, so we can treat it
as compatible, but it does have a a handful of extra IMP-DEF PMU events
to call its own. Thanks to the new notion of core complexes, the maximum
number of supported CPUs goes up as well.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
v2: Also make it complete and valid
Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
index 09ddeb6a3ccc..7f31bcecedb5 100644
--- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
+++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
@@ -21,7 +21,11 @@ description:
properties:
compatible:
- const: arm,dsu-pmu
+ oneOf:
+ - const: arm,dsu-pmu
+ - items:
+ - const: arm,dsu-110-pmu
+ - const: arm,dsu-pmu
interrupts:
items:
@@ -30,7 +34,7 @@ properties:
cpus:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
- maxItems: 8
+ maxItems: 12
description: List of phandles for the CPUs connected to this DSU instance.
required:
--
2.28.0.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v2 5/5] dt-bindings: perf: Add compatible for Arm DSU-110
2021-12-14 14:16 ` Robin Murphy
@ 2021-12-14 14:42 ` Suzuki K Poulose
-1 siblings, 0 replies; 30+ messages in thread
From: Suzuki K Poulose @ 2021-12-14 14:42 UTC (permalink / raw)
To: Robin Murphy, will, robh+dt, mark.rutland
Cc: catalin.marinas, thierry.reding, linux-arm-kernel, devicetree
On 14/12/2021 14:16, Robin Murphy wrote:
> DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
> largely identical to the previous generation of DSUs, so we can treat it
> as compatible, but it does have a a handful of extra IMP-DEF PMU events
> to call its own. Thanks to the new notion of core complexes, the maximum
> number of supported CPUs goes up as well.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>
> v2: Also make it complete and valid
>
> Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> index 09ddeb6a3ccc..7f31bcecedb5 100644
> --- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> @@ -21,7 +21,11 @@ description:
>
> properties:
> compatible:
> - const: arm,dsu-pmu
> + oneOf:
> + - const: arm,dsu-pmu
> + - items:
> + - const: arm,dsu-110-pmu
> + - const: arm,dsu-pmu
Couldn't this be :
compatible:
oneOf:
- const: arm,dsu-110-pmu
- const: arm,dsu-pmu
Otherwise, looks good to me.
Suzuki
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: perf: Add compatible for Arm DSU-110
@ 2021-12-14 14:42 ` Suzuki K Poulose
0 siblings, 0 replies; 30+ messages in thread
From: Suzuki K Poulose @ 2021-12-14 14:42 UTC (permalink / raw)
To: Robin Murphy, will, robh+dt, mark.rutland
Cc: catalin.marinas, thierry.reding, linux-arm-kernel, devicetree
On 14/12/2021 14:16, Robin Murphy wrote:
> DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
> largely identical to the previous generation of DSUs, so we can treat it
> as compatible, but it does have a a handful of extra IMP-DEF PMU events
> to call its own. Thanks to the new notion of core complexes, the maximum
> number of supported CPUs goes up as well.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>
> v2: Also make it complete and valid
>
> Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> index 09ddeb6a3ccc..7f31bcecedb5 100644
> --- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
> @@ -21,7 +21,11 @@ description:
>
> properties:
> compatible:
> - const: arm,dsu-pmu
> + oneOf:
> + - const: arm,dsu-pmu
> + - items:
> + - const: arm,dsu-110-pmu
> + - const: arm,dsu-pmu
Couldn't this be :
compatible:
oneOf:
- const: arm,dsu-110-pmu
- const: arm,dsu-pmu
Otherwise, looks good to me.
Suzuki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: perf: Add compatible for Arm DSU-110
2021-12-14 14:42 ` Suzuki K Poulose
@ 2021-12-14 14:59 ` Robin Murphy
-1 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:59 UTC (permalink / raw)
To: Suzuki K Poulose, will, robh+dt, mark.rutland
Cc: catalin.marinas, thierry.reding, linux-arm-kernel, devicetree
On 2021-12-14 14:42, Suzuki K Poulose wrote:
> On 14/12/2021 14:16, Robin Murphy wrote:
>> DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
>> largely identical to the previous generation of DSUs, so we can treat it
>> as compatible, but it does have a a handful of extra IMP-DEF PMU events
>> to call its own. Thanks to the new notion of core complexes, the maximum
>> number of supported CPUs goes up as well.
>>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> ---
>>
>> v2: Also make it complete and valid
>>
>> Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>> b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>> index 09ddeb6a3ccc..7f31bcecedb5 100644
>> --- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>> @@ -21,7 +21,11 @@ description:
>> properties:
>> compatible:
>> - const: arm,dsu-pmu
>> + oneOf:
>> + - const: arm,dsu-pmu
>> + - items:
>> + - const: arm,dsu-110-pmu
>> + - const: arm,dsu-pmu
>
> Couldn't this be :
>
> compatible:
> oneOf:
> - const: arm,dsu-110-pmu
> - const: arm,dsu-pmu
>
> Otherwise, looks good to me.
My intent here was for the new case to use both strings and thus still
permit a less-specific match to the original one (hence why there's no
change to the actual driver included here). It's a true "compatible" in
the sense that you can run the thing with the existing driver as if it's
a 1st-gen DSU and get the expected results - at least that's the
conclusion I drew from a side-by-side comparison of the TRMs, and the
folks testing FPGAs haven't complained since I told them to try it
months ago :)
Thanks,
Robin.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: perf: Add compatible for Arm DSU-110
@ 2021-12-14 14:59 ` Robin Murphy
0 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 14:59 UTC (permalink / raw)
To: Suzuki K Poulose, will, robh+dt, mark.rutland
Cc: catalin.marinas, thierry.reding, linux-arm-kernel, devicetree
On 2021-12-14 14:42, Suzuki K Poulose wrote:
> On 14/12/2021 14:16, Robin Murphy wrote:
>> DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
>> largely identical to the previous generation of DSUs, so we can treat it
>> as compatible, but it does have a a handful of extra IMP-DEF PMU events
>> to call its own. Thanks to the new notion of core complexes, the maximum
>> number of supported CPUs goes up as well.
>>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> ---
>>
>> v2: Also make it complete and valid
>>
>> Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>> b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>> index 09ddeb6a3ccc..7f31bcecedb5 100644
>> --- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>> @@ -21,7 +21,11 @@ description:
>> properties:
>> compatible:
>> - const: arm,dsu-pmu
>> + oneOf:
>> + - const: arm,dsu-pmu
>> + - items:
>> + - const: arm,dsu-110-pmu
>> + - const: arm,dsu-pmu
>
> Couldn't this be :
>
> compatible:
> oneOf:
> - const: arm,dsu-110-pmu
> - const: arm,dsu-pmu
>
> Otherwise, looks good to me.
My intent here was for the new case to use both strings and thus still
permit a less-specific match to the original one (hence why there's no
change to the actual driver included here). It's a true "compatible" in
the sense that you can run the thing with the existing driver as if it's
a 1st-gen DSU and get the expected results - at least that's the
conclusion I drew from a side-by-side comparison of the TRMs, and the
folks testing FPGAs haven't complained since I told them to try it
months ago :)
Thanks,
Robin.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: perf: Add compatible for Arm DSU-110
2021-12-14 14:59 ` Robin Murphy
@ 2021-12-14 18:54 ` Suzuki K Poulose
-1 siblings, 0 replies; 30+ messages in thread
From: Suzuki K Poulose @ 2021-12-14 18:54 UTC (permalink / raw)
To: Robin Murphy, will, robh+dt, mark.rutland
Cc: catalin.marinas, thierry.reding, linux-arm-kernel, devicetree
On 14/12/2021 14:59, Robin Murphy wrote:
> On 2021-12-14 14:42, Suzuki K Poulose wrote:
>> On 14/12/2021 14:16, Robin Murphy wrote:
>>> DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
>>> largely identical to the previous generation of DSUs, so we can treat it
>>> as compatible, but it does have a a handful of extra IMP-DEF PMU events
>>> to call its own. Thanks to the new notion of core complexes, the maximum
>>> number of supported CPUs goes up as well.
>>>
>>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>>> ---
>>>
>>> v2: Also make it complete and valid
>>>
>>> Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
>>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>>> b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>>> index 09ddeb6a3ccc..7f31bcecedb5 100644
>>> --- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>>> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>>> @@ -21,7 +21,11 @@ description:
>>> properties:
>>> compatible:
>>> - const: arm,dsu-pmu
>>> + oneOf:
>>> + - const: arm,dsu-pmu
>>> + - items:
>>> + - const: arm,dsu-110-pmu
>>> + - const: arm,dsu-pmu
>>
>> Couldn't this be :
>>
>> compatible:
>> oneOf:
>> - const: arm,dsu-110-pmu
>> - const: arm,dsu-pmu
>>
>> Otherwise, looks good to me.
>
> My intent here was for the new case to use both strings and thus still
> permit a less-specific match to the original one (hence why there's no
> change to the actual driver included here). It's a true "compatible" in
> the sense that you can run the thing with the existing driver as if it's
> a 1st-gen DSU and get the expected results - at least that's the
> conclusion I drew from a side-by-side comparison of the TRMs, and the
> folks testing FPGAs haven't complained since I told them to try it
> months ago :)
Ah, right. I should have guessed it from the lack of update to the driver.
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: perf: Add compatible for Arm DSU-110
@ 2021-12-14 18:54 ` Suzuki K Poulose
0 siblings, 0 replies; 30+ messages in thread
From: Suzuki K Poulose @ 2021-12-14 18:54 UTC (permalink / raw)
To: Robin Murphy, will, robh+dt, mark.rutland
Cc: catalin.marinas, thierry.reding, linux-arm-kernel, devicetree
On 14/12/2021 14:59, Robin Murphy wrote:
> On 2021-12-14 14:42, Suzuki K Poulose wrote:
>> On 14/12/2021 14:16, Robin Murphy wrote:
>>> DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
>>> largely identical to the previous generation of DSUs, so we can treat it
>>> as compatible, but it does have a a handful of extra IMP-DEF PMU events
>>> to call its own. Thanks to the new notion of core complexes, the maximum
>>> number of supported CPUs goes up as well.
>>>
>>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>>> ---
>>>
>>> v2: Also make it complete and valid
>>>
>>> Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
>>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>>> b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>>> index 09ddeb6a3ccc..7f31bcecedb5 100644
>>> --- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>>> +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml
>>> @@ -21,7 +21,11 @@ description:
>>> properties:
>>> compatible:
>>> - const: arm,dsu-pmu
>>> + oneOf:
>>> + - const: arm,dsu-pmu
>>> + - items:
>>> + - const: arm,dsu-110-pmu
>>> + - const: arm,dsu-pmu
>>
>> Couldn't this be :
>>
>> compatible:
>> oneOf:
>> - const: arm,dsu-110-pmu
>> - const: arm,dsu-pmu
>>
>> Otherwise, looks good to me.
>
> My intent here was for the new case to use both strings and thus still
> permit a less-specific match to the original one (hence why there's no
> change to the actual driver included here). It's a true "compatible" in
> the sense that you can run the thing with the existing driver as if it's
> a 1st-gen DSU and get the expected results - at least that's the
> conclusion I drew from a side-by-side comparison of the TRMs, and the
> folks testing FPGAs haven't complained since I told them to try it
> months ago :)
Ah, right. I should have guessed it from the lack of update to the driver.
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: perf: Add compatible for Arm DSU-110
2021-12-14 14:16 ` Robin Murphy
@ 2021-12-14 20:41 ` Rob Herring
-1 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-12-14 20:41 UTC (permalink / raw)
To: Robin Murphy
Cc: linux-arm-kernel, suzuki.poulose, will, robh+dt, devicetree,
catalin.marinas, thierry.reding, mark.rutland
On Tue, 14 Dec 2021 14:16:17 +0000, Robin Murphy wrote:
> DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
> largely identical to the previous generation of DSUs, so we can treat it
> as compatible, but it does have a a handful of extra IMP-DEF PMU events
> to call its own. Thanks to the new notion of core complexes, the maximum
> number of supported CPUs goes up as well.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>
> v2: Also make it complete and valid
>
> Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Applied, thanks!
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: perf: Add compatible for Arm DSU-110
@ 2021-12-14 20:41 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-12-14 20:41 UTC (permalink / raw)
To: Robin Murphy
Cc: linux-arm-kernel, suzuki.poulose, will, robh+dt, devicetree,
catalin.marinas, thierry.reding, mark.rutland
On Tue, 14 Dec 2021 14:16:17 +0000, Robin Murphy wrote:
> DSU-110 is the newest and shiniest for Armv9. Its programmer's model is
> largely identical to the previous generation of DSUs, so we can treat it
> as compatible, but it does have a a handful of extra IMP-DEF PMU events
> to call its own. Thanks to the new notion of core complexes, the maximum
> number of supported CPUs goes up as well.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>
> v2: Also make it complete and valid
>
> Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 0/5] arm64: PMU updates
2021-12-14 14:16 ` Robin Murphy
@ 2021-12-14 18:33 ` Will Deacon
-1 siblings, 0 replies; 30+ messages in thread
From: Will Deacon @ 2021-12-14 18:33 UTC (permalink / raw)
To: Robin Murphy, robh+dt, mark.rutland
Cc: catalin.marinas, kernel-team, Will Deacon, suzuki.poulose,
devicetree, thierry.reding, linux-arm-kernel
On Tue, 14 Dec 2021 14:16:12 +0000, Robin Murphy wrote:
> Here's v2, with the DSU binding actually finished (oh the shame...) and
> the NVIDIA PMU patch pulled in to benefit from the cleanup and keep
> things manageably together. The initial binding patch from v1 is no
> longer included since Rob has picked it up separately.
>
> Refactoring arm_pmu's probing to be more modular turns out to be a
> substantial yak to shave, so in the end I decided it *is* worth
> implementing Mark's macro suggestion now - after all, it can simply be
> converted from a function template to a structure template as and when
> the time comes.
>
> [...]
Applied first three to will (for-next/perf-cpu), thanks!
[1/5] arm64: perf: Support Denver and Carmel PMUs
https://git.kernel.org/will/c/d4c4844a9b47
[2/5] arm64: perf: Simplify registration boilerplate
https://git.kernel.org/will/c/6ac9f30bd43b
[3/5] arm64: perf: Support new DT compatibles
https://git.kernel.org/will/c/893c34b60a59
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v2 0/5] arm64: PMU updates
@ 2021-12-14 18:33 ` Will Deacon
0 siblings, 0 replies; 30+ messages in thread
From: Will Deacon @ 2021-12-14 18:33 UTC (permalink / raw)
To: Robin Murphy, robh+dt, mark.rutland
Cc: catalin.marinas, kernel-team, Will Deacon, suzuki.poulose,
devicetree, thierry.reding, linux-arm-kernel
On Tue, 14 Dec 2021 14:16:12 +0000, Robin Murphy wrote:
> Here's v2, with the DSU binding actually finished (oh the shame...) and
> the NVIDIA PMU patch pulled in to benefit from the cleanup and keep
> things manageably together. The initial binding patch from v1 is no
> longer included since Rob has picked it up separately.
>
> Refactoring arm_pmu's probing to be more modular turns out to be a
> substantial yak to shave, so in the end I decided it *is* worth
> implementing Mark's macro suggestion now - after all, it can simply be
> converted from a function template to a structure template as and when
> the time comes.
>
> [...]
Applied first three to will (for-next/perf-cpu), thanks!
[1/5] arm64: perf: Support Denver and Carmel PMUs
https://git.kernel.org/will/c/d4c4844a9b47
[2/5] arm64: perf: Simplify registration boilerplate
https://git.kernel.org/will/c/6ac9f30bd43b
[3/5] arm64: perf: Support new DT compatibles
https://git.kernel.org/will/c/893c34b60a59
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v2 0/5] arm64: PMU updates
2021-12-14 18:33 ` Will Deacon
@ 2021-12-14 19:02 ` Robin Murphy
-1 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 19:02 UTC (permalink / raw)
To: Will Deacon, robh+dt, mark.rutland
Cc: catalin.marinas, kernel-team, suzuki.poulose, devicetree,
thierry.reding, linux-arm-kernel
On 2021-12-14 18:33, Will Deacon wrote:
> On Tue, 14 Dec 2021 14:16:12 +0000, Robin Murphy wrote:
>> Here's v2, with the DSU binding actually finished (oh the shame...) and
>> the NVIDIA PMU patch pulled in to benefit from the cleanup and keep
>> things manageably together. The initial binding patch from v1 is no
>> longer included since Rob has picked it up separately.
>>
>> Refactoring arm_pmu's probing to be more modular turns out to be a
>> substantial yak to shave, so in the end I decided it *is* worth
>> implementing Mark's macro suggestion now - after all, it can simply be
>> converted from a function template to a structure template as and when
>> the time comes.
>>
>> [...]
>
> Applied first three to will (for-next/perf-cpu), thanks!
>
> [1/5] arm64: perf: Support Denver and Carmel PMUs
> https://git.kernel.org/will/c/d4c4844a9b47
> [2/5] arm64: perf: Simplify registration boilerplate
> https://git.kernel.org/will/c/6ac9f30bd43b
> [3/5] arm64: perf: Support new DT compatibles
> https://git.kernel.org/will/c/893c34b60a59
Thanks Will! Just to clarify, are you leaving the DSU binding patches
for Rob to pick up, or waiting for the typo to get fixed? (and if the
former - Rob, would you like me to resend a v3 with the typo fixed?)
Cheers,
Robin.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 0/5] arm64: PMU updates
@ 2021-12-14 19:02 ` Robin Murphy
0 siblings, 0 replies; 30+ messages in thread
From: Robin Murphy @ 2021-12-14 19:02 UTC (permalink / raw)
To: Will Deacon, robh+dt, mark.rutland
Cc: catalin.marinas, kernel-team, suzuki.poulose, devicetree,
thierry.reding, linux-arm-kernel
On 2021-12-14 18:33, Will Deacon wrote:
> On Tue, 14 Dec 2021 14:16:12 +0000, Robin Murphy wrote:
>> Here's v2, with the DSU binding actually finished (oh the shame...) and
>> the NVIDIA PMU patch pulled in to benefit from the cleanup and keep
>> things manageably together. The initial binding patch from v1 is no
>> longer included since Rob has picked it up separately.
>>
>> Refactoring arm_pmu's probing to be more modular turns out to be a
>> substantial yak to shave, so in the end I decided it *is* worth
>> implementing Mark's macro suggestion now - after all, it can simply be
>> converted from a function template to a structure template as and when
>> the time comes.
>>
>> [...]
>
> Applied first three to will (for-next/perf-cpu), thanks!
>
> [1/5] arm64: perf: Support Denver and Carmel PMUs
> https://git.kernel.org/will/c/d4c4844a9b47
> [2/5] arm64: perf: Simplify registration boilerplate
> https://git.kernel.org/will/c/6ac9f30bd43b
> [3/5] arm64: perf: Support new DT compatibles
> https://git.kernel.org/will/c/893c34b60a59
Thanks Will! Just to clarify, are you leaving the DSU binding patches
for Rob to pick up, or waiting for the typo to get fixed? (and if the
former - Rob, would you like me to resend a v3 with the typo fixed?)
Cheers,
Robin.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 0/5] arm64: PMU updates
2021-12-14 19:02 ` Robin Murphy
@ 2021-12-14 19:32 ` Will Deacon
-1 siblings, 0 replies; 30+ messages in thread
From: Will Deacon @ 2021-12-14 19:32 UTC (permalink / raw)
To: Robin Murphy
Cc: robh+dt, mark.rutland, catalin.marinas, kernel-team,
suzuki.poulose, devicetree, thierry.reding, linux-arm-kernel
On Tue, Dec 14, 2021 at 07:02:57PM +0000, Robin Murphy wrote:
> On 2021-12-14 18:33, Will Deacon wrote:
> > On Tue, 14 Dec 2021 14:16:12 +0000, Robin Murphy wrote:
> > > Here's v2, with the DSU binding actually finished (oh the shame...) and
> > > the NVIDIA PMU patch pulled in to benefit from the cleanup and keep
> > > things manageably together. The initial binding patch from v1 is no
> > > longer included since Rob has picked it up separately.
> > >
> > > Refactoring arm_pmu's probing to be more modular turns out to be a
> > > substantial yak to shave, so in the end I decided it *is* worth
> > > implementing Mark's macro suggestion now - after all, it can simply be
> > > converted from a function template to a structure template as and when
> > > the time comes.
> > >
> > > [...]
> >
> > Applied first three to will (for-next/perf-cpu), thanks!
> >
> > [1/5] arm64: perf: Support Denver and Carmel PMUs
> > https://git.kernel.org/will/c/d4c4844a9b47
> > [2/5] arm64: perf: Simplify registration boilerplate
> > https://git.kernel.org/will/c/6ac9f30bd43b
> > [3/5] arm64: perf: Support new DT compatibles
> > https://git.kernel.org/will/c/893c34b60a59
>
> Thanks Will! Just to clarify, are you leaving the DSU binding patches for
> Rob to pick up, or waiting for the typo to get fixed? (and if the former -
> Rob, would you like me to resend a v3 with the typo fixed?)
I'm about to disappear on holiday, so I figured it was best to take the
first three patches and leave the other two (as they seem less urgent and
also had comment from Suzuki). If somebody else grabs 'em when they're
ready, so be it, otherwise I'll pick them next time around.
Cheers,
Will
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 0/5] arm64: PMU updates
@ 2021-12-14 19:32 ` Will Deacon
0 siblings, 0 replies; 30+ messages in thread
From: Will Deacon @ 2021-12-14 19:32 UTC (permalink / raw)
To: Robin Murphy
Cc: robh+dt, mark.rutland, catalin.marinas, kernel-team,
suzuki.poulose, devicetree, thierry.reding, linux-arm-kernel
On Tue, Dec 14, 2021 at 07:02:57PM +0000, Robin Murphy wrote:
> On 2021-12-14 18:33, Will Deacon wrote:
> > On Tue, 14 Dec 2021 14:16:12 +0000, Robin Murphy wrote:
> > > Here's v2, with the DSU binding actually finished (oh the shame...) and
> > > the NVIDIA PMU patch pulled in to benefit from the cleanup and keep
> > > things manageably together. The initial binding patch from v1 is no
> > > longer included since Rob has picked it up separately.
> > >
> > > Refactoring arm_pmu's probing to be more modular turns out to be a
> > > substantial yak to shave, so in the end I decided it *is* worth
> > > implementing Mark's macro suggestion now - after all, it can simply be
> > > converted from a function template to a structure template as and when
> > > the time comes.
> > >
> > > [...]
> >
> > Applied first three to will (for-next/perf-cpu), thanks!
> >
> > [1/5] arm64: perf: Support Denver and Carmel PMUs
> > https://git.kernel.org/will/c/d4c4844a9b47
> > [2/5] arm64: perf: Simplify registration boilerplate
> > https://git.kernel.org/will/c/6ac9f30bd43b
> > [3/5] arm64: perf: Support new DT compatibles
> > https://git.kernel.org/will/c/893c34b60a59
>
> Thanks Will! Just to clarify, are you leaving the DSU binding patches for
> Rob to pick up, or waiting for the typo to get fixed? (and if the former -
> Rob, would you like me to resend a v3 with the typo fixed?)
I'm about to disappear on holiday, so I figured it was best to take the
first three patches and leave the other two (as they seem less urgent and
also had comment from Suzuki). If somebody else grabs 'em when they're
ready, so be it, otherwise I'll pick them next time around.
Cheers,
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread