From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
will@kernel.org, mathieu.poirier@linaro.org
Cc: catalin.marinas@arm.com, mike.leach@linaro.org,
leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address
Date: Tue, 19 Oct 2021 11:30:32 +0530 [thread overview]
Message-ID: <378825b9-8cea-27b4-f5f5-bff187834f3d@arm.com> (raw)
In-Reply-To: <20211014223125.2605031-16-suzuki.poulose@arm.com>
On 10/15/21 4:01 AM, Suzuki K Poulose wrote:
> With the TRBE driver workaround available, enable the config symbols
> to be built without COMPILE_TEST
>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> arch/arm64/Kconfig | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index f72fa44d6182..d6383ef05871 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -743,7 +743,6 @@ config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
>
> config ARM64_ERRATUM_2253138
> bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
> - depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
> depends on CORESIGHT_TRBE
> default y
> select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
> @@ -762,7 +761,6 @@ config ARM64_ERRATUM_2253138
>
> config ARM64_ERRATUM_2224489
> bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
> - depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
> depends on CORESIGHT_TRBE
> default y
> select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
>
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
will@kernel.org, mathieu.poirier@linaro.org
Cc: catalin.marinas@arm.com, mike.leach@linaro.org,
leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address
Date: Tue, 19 Oct 2021 11:30:32 +0530 [thread overview]
Message-ID: <378825b9-8cea-27b4-f5f5-bff187834f3d@arm.com> (raw)
In-Reply-To: <20211014223125.2605031-16-suzuki.poulose@arm.com>
On 10/15/21 4:01 AM, Suzuki K Poulose wrote:
> With the TRBE driver workaround available, enable the config symbols
> to be built without COMPILE_TEST
>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> arch/arm64/Kconfig | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index f72fa44d6182..d6383ef05871 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -743,7 +743,6 @@ config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
>
> config ARM64_ERRATUM_2253138
> bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
> - depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
> depends on CORESIGHT_TRBE
> default y
> select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
> @@ -762,7 +761,6 @@ config ARM64_ERRATUM_2253138
>
> config ARM64_ERRATUM_2224489
> bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
> - depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
> depends on CORESIGHT_TRBE
> default y
> select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
>
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next prev parent reply other threads:[~2021-10-19 6:00 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-14 22:31 [PATCH v5 00/15] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 01/15] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-19 11:04 ` Will Deacon
2021-10-19 11:04 ` Will Deacon
2021-10-19 11:15 ` Suzuki K Poulose
2021-10-19 11:15 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-19 5:06 ` Anshuman Khandual
2021-10-19 5:06 ` Anshuman Khandual
2021-10-19 11:02 ` Will Deacon
2021-10-19 11:02 ` Will Deacon
2021-10-19 11:36 ` Suzuki K Poulose
2021-10-19 11:36 ` Suzuki K Poulose
2021-10-19 11:42 ` Will Deacon
2021-10-19 11:42 ` Will Deacon
2021-10-19 12:06 ` Suzuki K Poulose
2021-10-19 12:06 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 04/15] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-18 15:50 ` Mathieu Poirier
2021-10-18 15:50 ` Mathieu Poirier
2021-10-19 13:29 ` Suzuki K Poulose
2021-10-19 13:29 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 05/15] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 06/15] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 07/15] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 08/15] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 09/15] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-19 5:25 ` Anshuman Khandual
2021-10-19 5:25 ` Anshuman Khandual
2021-10-29 10:31 ` Arnd Bergmann
2021-10-29 10:31 ` Arnd Bergmann
2021-10-29 13:00 ` Suzuki K Poulose
2021-10-29 13:00 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-18 15:51 ` Mathieu Poirier
2021-10-18 15:51 ` Mathieu Poirier
2021-10-18 21:15 ` Suzuki K Poulose
2021-10-18 21:15 ` Suzuki K Poulose
2021-10-19 4:36 ` Anshuman Khandual
2021-10-19 4:36 ` Anshuman Khandual
2021-10-19 8:37 ` Suzuki K Poulose
2021-10-19 8:37 ` Suzuki K Poulose
2021-10-19 5:42 ` Anshuman Khandual
2021-10-19 5:42 ` Anshuman Khandual
2021-10-14 22:31 ` [PATCH v5 11/15] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 12/15] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-19 5:55 ` Anshuman Khandual
2021-10-19 5:55 ` Anshuman Khandual
2021-10-14 22:31 ` [PATCH v5 13/15] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-19 5:57 ` Anshuman Khandual
2021-10-19 5:57 ` Anshuman Khandual
2021-10-14 22:31 ` [PATCH v5 14/15] arm64: errata: Enable workaround for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-18 15:54 ` Mathieu Poirier
2021-10-18 15:54 ` Mathieu Poirier
2021-10-19 5:59 ` Anshuman Khandual
2021-10-19 5:59 ` Anshuman Khandual
2021-10-19 10:42 ` Will Deacon
2021-10-19 10:42 ` Will Deacon
2021-10-14 22:31 ` [PATCH v5 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-18 15:54 ` Mathieu Poirier
2021-10-18 15:54 ` Mathieu Poirier
2021-10-19 6:00 ` Anshuman Khandual [this message]
2021-10-19 6:00 ` Anshuman Khandual
2021-10-19 10:42 ` Will Deacon
2021-10-19 10:42 ` Will Deacon
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