From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Will Deacon <will@kernel.org>
Cc: mathieu.poirier@linaro.org, catalin.marinas@arm.com,
anshuman.khandual@arm.com, mike.leach@linaro.org,
leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH v5 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode
Date: Tue, 19 Oct 2021 12:15:49 +0100 [thread overview]
Message-ID: <fa6177aa-e84d-3928-f202-0dd70df3164a@arm.com> (raw)
In-Reply-To: <20211019110443.GE13251@willie-the-truck>
On 19/10/2021 12:04, Will Deacon wrote:
> On Thu, Oct 14, 2021 at 11:31:12PM +0100, Suzuki K Poulose wrote:
>> Arm Neoverse-N2 and the Cortex-A710 cores are affected
>> by a CPU erratum where the TRBE will overwrite the trace buffer
>> in FILL mode. The TRBE doesn't stop (as expected in FILL mode)
>> when it reaches the limit and wraps to the base to continue
>> writing upto 3 cache lines. This will overwrite any trace that
>> was written previously.
>>
>> Add the Neoverse-N2 erratumi(#2139208) and Cortex-A710 erratum
>> (#2119858) to the detection logic.
>
> Weird typo and double space in this sentence.
I have fixed this now.
Thanks
Suzuki
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Will Deacon <will@kernel.org>
Cc: mathieu.poirier@linaro.org, catalin.marinas@arm.com,
anshuman.khandual@arm.com, mike.leach@linaro.org,
leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH v5 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode
Date: Tue, 19 Oct 2021 12:15:49 +0100 [thread overview]
Message-ID: <fa6177aa-e84d-3928-f202-0dd70df3164a@arm.com> (raw)
In-Reply-To: <20211019110443.GE13251@willie-the-truck>
On 19/10/2021 12:04, Will Deacon wrote:
> On Thu, Oct 14, 2021 at 11:31:12PM +0100, Suzuki K Poulose wrote:
>> Arm Neoverse-N2 and the Cortex-A710 cores are affected
>> by a CPU erratum where the TRBE will overwrite the trace buffer
>> in FILL mode. The TRBE doesn't stop (as expected in FILL mode)
>> when it reaches the limit and wraps to the base to continue
>> writing upto 3 cache lines. This will overwrite any trace that
>> was written previously.
>>
>> Add the Neoverse-N2 erratumi(#2139208) and Cortex-A710 erratum
>> (#2119858) to the detection logic.
>
> Weird typo and double space in this sentence.
I have fixed this now.
Thanks
Suzuki
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next prev parent reply other threads:[~2021-10-19 11:15 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-14 22:31 [PATCH v5 00/15] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 01/15] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-19 11:04 ` Will Deacon
2021-10-19 11:04 ` Will Deacon
2021-10-19 11:15 ` Suzuki K Poulose [this message]
2021-10-19 11:15 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-19 5:06 ` Anshuman Khandual
2021-10-19 5:06 ` Anshuman Khandual
2021-10-19 11:02 ` Will Deacon
2021-10-19 11:02 ` Will Deacon
2021-10-19 11:36 ` Suzuki K Poulose
2021-10-19 11:36 ` Suzuki K Poulose
2021-10-19 11:42 ` Will Deacon
2021-10-19 11:42 ` Will Deacon
2021-10-19 12:06 ` Suzuki K Poulose
2021-10-19 12:06 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 04/15] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-18 15:50 ` Mathieu Poirier
2021-10-18 15:50 ` Mathieu Poirier
2021-10-19 13:29 ` Suzuki K Poulose
2021-10-19 13:29 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 05/15] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 06/15] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 07/15] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 08/15] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 09/15] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-19 5:25 ` Anshuman Khandual
2021-10-19 5:25 ` Anshuman Khandual
2021-10-29 10:31 ` Arnd Bergmann
2021-10-29 10:31 ` Arnd Bergmann
2021-10-29 13:00 ` Suzuki K Poulose
2021-10-29 13:00 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-18 15:51 ` Mathieu Poirier
2021-10-18 15:51 ` Mathieu Poirier
2021-10-18 21:15 ` Suzuki K Poulose
2021-10-18 21:15 ` Suzuki K Poulose
2021-10-19 4:36 ` Anshuman Khandual
2021-10-19 4:36 ` Anshuman Khandual
2021-10-19 8:37 ` Suzuki K Poulose
2021-10-19 8:37 ` Suzuki K Poulose
2021-10-19 5:42 ` Anshuman Khandual
2021-10-19 5:42 ` Anshuman Khandual
2021-10-14 22:31 ` [PATCH v5 11/15] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 12/15] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-19 5:55 ` Anshuman Khandual
2021-10-19 5:55 ` Anshuman Khandual
2021-10-14 22:31 ` [PATCH v5 13/15] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-19 5:57 ` Anshuman Khandual
2021-10-19 5:57 ` Anshuman Khandual
2021-10-14 22:31 ` [PATCH v5 14/15] arm64: errata: Enable workaround for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-18 15:54 ` Mathieu Poirier
2021-10-18 15:54 ` Mathieu Poirier
2021-10-19 5:59 ` Anshuman Khandual
2021-10-19 5:59 ` Anshuman Khandual
2021-10-19 10:42 ` Will Deacon
2021-10-19 10:42 ` Will Deacon
2021-10-14 22:31 ` [PATCH v5 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-18 15:54 ` Mathieu Poirier
2021-10-18 15:54 ` Mathieu Poirier
2021-10-19 6:00 ` Anshuman Khandual
2021-10-19 6:00 ` Anshuman Khandual
2021-10-19 10:42 ` Will Deacon
2021-10-19 10:42 ` Will Deacon
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