From: Suzuki K Poulose <suzuki.poulose@arm.com> To: Will Deacon <will@kernel.org> Cc: mathieu.poirier@linaro.org, catalin.marinas@arm.com, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Rutland <mark.rutland@arm.com> Subject: Re: [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures Date: Tue, 19 Oct 2021 12:36:48 +0100 [thread overview] Message-ID: <850c67de-a656-7515-e575-d47d2af78200@arm.com> (raw) In-Reply-To: <20211019110233.GD13251@willie-the-truck> On 19/10/2021 12:02, Will Deacon wrote: > On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote: >> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >> index ccd757373f36..bdbeac75ead6 100644 >> --- a/arch/arm64/kernel/cpu_errata.c >> +++ b/arch/arm64/kernel/cpu_errata.c >> @@ -352,6 +352,18 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { >> }; >> #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ >> >> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE >> +static const struct midr_range tsb_flush_fail_cpus[] = { >> +#ifdef CONFIG_ARM64_ERRATUM_2067961 >> + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), >> +#endif >> +#ifdef CONFIG_ARM64_ERRATUM_2054223 >> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), >> +#endif >> + {}, >> +}; >> +#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ >> + >> const struct arm64_cpu_capabilities arm64_errata[] = { >> #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE >> { >> @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >> .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, >> CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), >> }, >> +#endif >> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE > > You still haven't fixed this typo... > Sorry about that. I thought it was about selecting the Kconfig entries, which was fixed. I will fix this. > Seriously, I get compile warnings from this -- are you not seeing them? No, I don't get any warnings. Is there something that I am missing ? --8>-- suzuki@ewhatever:coresight$ grep "WERROR\|TSB" .config CONFIG_WERROR=y CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y suzuki@ewhatever:coresight$ grep TSB arch/arm64/kernel/cpu_errata.c #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, suzuki@ewhatever:coresight$ touch arch/arm64/kernel/cpu_errata.c suzuki@ewhatever:coresight$ make -j16 CALL scripts/atomic/check-atomics.sh CALL scripts/checksyscalls.sh CHK include/generated/compile.h CC arch/arm64/kernel/cpu_errata.o AR arch/arm64/kernel/built-in.a AR arch/arm64/built-in.a GEN .version CHK include/generated/compile.h UPD include/generated/compile.h CC init/version.o AR init/built-in.a LD vmlinux.o MODPOST vmlinux.symvers MODINFO modules.builtin.modinfo GEN modules.builtin LD .tmp_vmlinux.kallsyms1 KSYMS .tmp_vmlinux.kallsyms1.S AS .tmp_vmlinux.kallsyms1.S LD .tmp_vmlinux.kallsyms2 KSYMS .tmp_vmlinux.kallsyms2.S AS .tmp_vmlinux.kallsyms2.S LD vmlinux SORTTAB vmlinux SYSMAP System.map MODPOST modules-only.symvers OBJCOPY arch/arm64/boot/Image GEN Module.symvers GZIP arch/arm64/boot/Image.gz Suzuki > > Will >
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: Will Deacon <will@kernel.org> Cc: mathieu.poirier@linaro.org, catalin.marinas@arm.com, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Rutland <mark.rutland@arm.com> Subject: Re: [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures Date: Tue, 19 Oct 2021 12:36:48 +0100 [thread overview] Message-ID: <850c67de-a656-7515-e575-d47d2af78200@arm.com> (raw) In-Reply-To: <20211019110233.GD13251@willie-the-truck> On 19/10/2021 12:02, Will Deacon wrote: > On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote: >> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >> index ccd757373f36..bdbeac75ead6 100644 >> --- a/arch/arm64/kernel/cpu_errata.c >> +++ b/arch/arm64/kernel/cpu_errata.c >> @@ -352,6 +352,18 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { >> }; >> #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ >> >> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE >> +static const struct midr_range tsb_flush_fail_cpus[] = { >> +#ifdef CONFIG_ARM64_ERRATUM_2067961 >> + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), >> +#endif >> +#ifdef CONFIG_ARM64_ERRATUM_2054223 >> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), >> +#endif >> + {}, >> +}; >> +#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ >> + >> const struct arm64_cpu_capabilities arm64_errata[] = { >> #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE >> { >> @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >> .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, >> CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), >> }, >> +#endif >> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE > > You still haven't fixed this typo... > Sorry about that. I thought it was about selecting the Kconfig entries, which was fixed. I will fix this. > Seriously, I get compile warnings from this -- are you not seeing them? No, I don't get any warnings. Is there something that I am missing ? --8>-- suzuki@ewhatever:coresight$ grep "WERROR\|TSB" .config CONFIG_WERROR=y CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y suzuki@ewhatever:coresight$ grep TSB arch/arm64/kernel/cpu_errata.c #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, suzuki@ewhatever:coresight$ touch arch/arm64/kernel/cpu_errata.c suzuki@ewhatever:coresight$ make -j16 CALL scripts/atomic/check-atomics.sh CALL scripts/checksyscalls.sh CHK include/generated/compile.h CC arch/arm64/kernel/cpu_errata.o AR arch/arm64/kernel/built-in.a AR arch/arm64/built-in.a GEN .version CHK include/generated/compile.h UPD include/generated/compile.h CC init/version.o AR init/built-in.a LD vmlinux.o MODPOST vmlinux.symvers MODINFO modules.builtin.modinfo GEN modules.builtin LD .tmp_vmlinux.kallsyms1 KSYMS .tmp_vmlinux.kallsyms1.S AS .tmp_vmlinux.kallsyms1.S LD .tmp_vmlinux.kallsyms2 KSYMS .tmp_vmlinux.kallsyms2.S AS .tmp_vmlinux.kallsyms2.S LD vmlinux SORTTAB vmlinux SYSMAP System.map MODPOST modules-only.symvers OBJCOPY arch/arm64/boot/Image GEN Module.symvers GZIP arch/arm64/boot/Image.gz Suzuki > > Will > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-19 11:36 UTC|newest] Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-14 22:31 [PATCH v5 00/15] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-14 22:31 ` [PATCH v5 01/15] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-14 22:31 ` [PATCH v5 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-19 11:04 ` Will Deacon 2021-10-19 11:04 ` Will Deacon 2021-10-19 11:15 ` Suzuki K Poulose 2021-10-19 11:15 ` Suzuki K Poulose 2021-10-14 22:31 ` [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-19 5:06 ` Anshuman Khandual 2021-10-19 5:06 ` Anshuman Khandual 2021-10-19 11:02 ` Will Deacon 2021-10-19 11:02 ` Will Deacon 2021-10-19 11:36 ` Suzuki K Poulose [this message] 2021-10-19 11:36 ` Suzuki K Poulose 2021-10-19 11:42 ` Will Deacon 2021-10-19 11:42 ` Will Deacon 2021-10-19 12:06 ` Suzuki K Poulose 2021-10-19 12:06 ` Suzuki K Poulose 2021-10-14 22:31 ` [PATCH v5 04/15] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-18 15:50 ` Mathieu Poirier 2021-10-18 15:50 ` Mathieu Poirier 2021-10-19 13:29 ` Suzuki K Poulose 2021-10-19 13:29 ` Suzuki K Poulose 2021-10-14 22:31 ` [PATCH v5 05/15] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-14 22:31 ` [PATCH v5 06/15] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-14 22:31 ` [PATCH v5 07/15] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-14 22:31 ` [PATCH v5 08/15] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-14 22:31 ` [PATCH v5 09/15] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-19 5:25 ` Anshuman Khandual 2021-10-19 5:25 ` Anshuman Khandual 2021-10-29 10:31 ` Arnd Bergmann 2021-10-29 10:31 ` Arnd Bergmann 2021-10-29 13:00 ` Suzuki K Poulose 2021-10-29 13:00 ` Suzuki K Poulose 2021-10-14 22:31 ` [PATCH v5 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-18 15:51 ` Mathieu Poirier 2021-10-18 15:51 ` Mathieu Poirier 2021-10-18 21:15 ` Suzuki K Poulose 2021-10-18 21:15 ` Suzuki K Poulose 2021-10-19 4:36 ` Anshuman Khandual 2021-10-19 4:36 ` Anshuman Khandual 2021-10-19 8:37 ` Suzuki K Poulose 2021-10-19 8:37 ` Suzuki K Poulose 2021-10-19 5:42 ` Anshuman Khandual 2021-10-19 5:42 ` Anshuman Khandual 2021-10-14 22:31 ` [PATCH v5 11/15] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-14 22:31 ` [PATCH v5 12/15] coresight: trbe: Make sure we have enough space Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-19 5:55 ` Anshuman Khandual 2021-10-19 5:55 ` Anshuman Khandual 2021-10-14 22:31 ` [PATCH v5 13/15] coresight: trbe: Work around write to out of range Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-19 5:57 ` Anshuman Khandual 2021-10-19 5:57 ` Anshuman Khandual 2021-10-14 22:31 ` [PATCH v5 14/15] arm64: errata: Enable workaround for TRBE overwrite in FILL mode Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-18 15:54 ` Mathieu Poirier 2021-10-18 15:54 ` Mathieu Poirier 2021-10-19 5:59 ` Anshuman Khandual 2021-10-19 5:59 ` Anshuman Khandual 2021-10-19 10:42 ` Will Deacon 2021-10-19 10:42 ` Will Deacon 2021-10-14 22:31 ` [PATCH v5 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address Suzuki K Poulose 2021-10-14 22:31 ` Suzuki K Poulose 2021-10-18 15:54 ` Mathieu Poirier 2021-10-18 15:54 ` Mathieu Poirier 2021-10-19 6:00 ` Anshuman Khandual 2021-10-19 6:00 ` Anshuman Khandual 2021-10-19 10:42 ` Will Deacon 2021-10-19 10:42 ` Will Deacon
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=850c67de-a656-7515-e575-d47d2af78200@arm.com \ --to=suzuki.poulose@arm.com \ --cc=anshuman.khandual@arm.com \ --cc=catalin.marinas@arm.com \ --cc=coresight@lists.linaro.org \ --cc=leo.yan@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=mathieu.poirier@linaro.org \ --cc=maz@kernel.org \ --cc=mike.leach@linaro.org \ --cc=will@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.