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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: will@kernel.org, catalin.marinas@arm.com,
	anshuman.khandual@arm.com, mike.leach@linaro.org,
	leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH v5 04/15] arm64: errata: Add detection for TRBE write to out-of-range
Date: Tue, 19 Oct 2021 14:29:58 +0100	[thread overview]
Message-ID: <928f02ab-8226-1679-a120-06778d03c93c@arm.com> (raw)
In-Reply-To: <20211018155041.GA3163131@p14s>

On 18/10/2021 16:50, Mathieu Poirier wrote:
> Good morning,
> 
> On Thu, Oct 14, 2021 at 11:31:14PM +0100, Suzuki K Poulose wrote:
>> Arm Neoverse-N2 and Cortex-A710 cores are affected by an erratum where the
>> trbe, under some circumstances, might write upto 64bytes to an address after
> 
> Checkpatch gives me a warning about this line...
> 
>> the Limit as programmed by the TRBLIMITR_EL1.LIMIT. This might -
>>
>>    - Corrupt a page in the ring buffer, which may corrupt trace from a
>>      previous session, consumed by userspace.
>>    - Hit the guard page at the end of the vmalloc area and raise a fault.
>>
>> To keep the handling simpler, we always leave the last page from the
>> range, which TRBE is allowed to write. This can be achieved by ensuring
>> that we always have more than a PAGE worth space in the range, while
>> calculating the LIMIT for TRBE. And then the LIMIT pointer can be adjusted
>> to leave the PAGE (TRBLIMITR.LIMIT -= PAGE_SIZE), out of the TRBE range
>> while enabling it. This makes sure that the TRBE will only write to an area
>> within its allowed limit (i.e, [head-head+size]) and we do not have to handle
> 
> I'm pretty sure this line will also be flagged.
> 

Thanks for pointing them out. I have fixed it now.

Suzuki

WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: will@kernel.org, catalin.marinas@arm.com,
	anshuman.khandual@arm.com, mike.leach@linaro.org,
	leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH v5 04/15] arm64: errata: Add detection for TRBE write to out-of-range
Date: Tue, 19 Oct 2021 14:29:58 +0100	[thread overview]
Message-ID: <928f02ab-8226-1679-a120-06778d03c93c@arm.com> (raw)
In-Reply-To: <20211018155041.GA3163131@p14s>

On 18/10/2021 16:50, Mathieu Poirier wrote:
> Good morning,
> 
> On Thu, Oct 14, 2021 at 11:31:14PM +0100, Suzuki K Poulose wrote:
>> Arm Neoverse-N2 and Cortex-A710 cores are affected by an erratum where the
>> trbe, under some circumstances, might write upto 64bytes to an address after
> 
> Checkpatch gives me a warning about this line...
> 
>> the Limit as programmed by the TRBLIMITR_EL1.LIMIT. This might -
>>
>>    - Corrupt a page in the ring buffer, which may corrupt trace from a
>>      previous session, consumed by userspace.
>>    - Hit the guard page at the end of the vmalloc area and raise a fault.
>>
>> To keep the handling simpler, we always leave the last page from the
>> range, which TRBE is allowed to write. This can be achieved by ensuring
>> that we always have more than a PAGE worth space in the range, while
>> calculating the LIMIT for TRBE. And then the LIMIT pointer can be adjusted
>> to leave the PAGE (TRBLIMITR.LIMIT -= PAGE_SIZE), out of the TRBE range
>> while enabling it. This makes sure that the TRBE will only write to an area
>> within its allowed limit (i.e, [head-head+size]) and we do not have to handle
> 
> I'm pretty sure this line will also be flagged.
> 

Thanks for pointing them out. I have fixed it now.

Suzuki

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  reply	other threads:[~2021-10-19 13:30 UTC|newest]

Thread overview: 82+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-14 22:31 [PATCH v5 00/15] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-10-14 22:31 ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 01/15] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-19 11:04   ` Will Deacon
2021-10-19 11:04     ` Will Deacon
2021-10-19 11:15     ` Suzuki K Poulose
2021-10-19 11:15       ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-19  5:06   ` Anshuman Khandual
2021-10-19  5:06     ` Anshuman Khandual
2021-10-19 11:02   ` Will Deacon
2021-10-19 11:02     ` Will Deacon
2021-10-19 11:36     ` Suzuki K Poulose
2021-10-19 11:36       ` Suzuki K Poulose
2021-10-19 11:42       ` Will Deacon
2021-10-19 11:42         ` Will Deacon
2021-10-19 12:06         ` Suzuki K Poulose
2021-10-19 12:06           ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 04/15] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-18 15:50   ` Mathieu Poirier
2021-10-18 15:50     ` Mathieu Poirier
2021-10-19 13:29     ` Suzuki K Poulose [this message]
2021-10-19 13:29       ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 05/15] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 06/15] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 07/15] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 08/15] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 09/15] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-19  5:25   ` Anshuman Khandual
2021-10-19  5:25     ` Anshuman Khandual
2021-10-29 10:31   ` Arnd Bergmann
2021-10-29 10:31     ` Arnd Bergmann
2021-10-29 13:00     ` Suzuki K Poulose
2021-10-29 13:00       ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-18 15:51   ` Mathieu Poirier
2021-10-18 15:51     ` Mathieu Poirier
2021-10-18 21:15     ` Suzuki K Poulose
2021-10-18 21:15       ` Suzuki K Poulose
2021-10-19  4:36       ` Anshuman Khandual
2021-10-19  4:36         ` Anshuman Khandual
2021-10-19  8:37         ` Suzuki K Poulose
2021-10-19  8:37           ` Suzuki K Poulose
2021-10-19  5:42   ` Anshuman Khandual
2021-10-19  5:42     ` Anshuman Khandual
2021-10-14 22:31 ` [PATCH v5 11/15] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-14 22:31 ` [PATCH v5 12/15] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-19  5:55   ` Anshuman Khandual
2021-10-19  5:55     ` Anshuman Khandual
2021-10-14 22:31 ` [PATCH v5 13/15] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-19  5:57   ` Anshuman Khandual
2021-10-19  5:57     ` Anshuman Khandual
2021-10-14 22:31 ` [PATCH v5 14/15] arm64: errata: Enable workaround for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-18 15:54   ` Mathieu Poirier
2021-10-18 15:54     ` Mathieu Poirier
2021-10-19  5:59   ` Anshuman Khandual
2021-10-19  5:59     ` Anshuman Khandual
2021-10-19 10:42   ` Will Deacon
2021-10-19 10:42     ` Will Deacon
2021-10-14 22:31 ` [PATCH v5 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address Suzuki K Poulose
2021-10-14 22:31   ` Suzuki K Poulose
2021-10-18 15:54   ` Mathieu Poirier
2021-10-18 15:54     ` Mathieu Poirier
2021-10-19  6:00   ` Anshuman Khandual
2021-10-19  6:00     ` Anshuman Khandual
2021-10-19 10:42   ` Will Deacon
2021-10-19 10:42     ` Will Deacon

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