From: Marc Zyngier <marc.zyngier@arm.com> To: Rasmus Villemoes <rasmus.villemoes@prevas.dk>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com> Cc: Alexander Stein <alexander.stein@systec-electronic.com>, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [RFC] irqchip: add support for LS1021A external interrupt lines Date: Mon, 11 Dec 2017 18:29:59 +0000 [thread overview] Message-ID: <3b22d1ed-fe8f-b733-1543-86e89b493114@arm.com> (raw) In-Reply-To: <563e0aaa-faf9-ae6a-ccd4-2aa89d7e457b@prevas.dk> On 11/12/17 09:30, Rasmus Villemoes wrote: > On 2017-12-08 17:02, Marc Zyngier wrote: [...] >> Overall, it is a bit annoying that you just copied the driver altogether >> instead of trying to allow the common stuff to be shared between >> drivers. Most of this is just boilerplate code... > > Yes, it did annoy me as well. However, the real meat of this is which > bits of which register to poke to support a negative polarity irq, and > there doesn't seem to be a good way to express that in DT. The register > offset and the mapping from external irq# to the GIC one is reasonably > easy (and would thus get rid of my NIRQ and INTPCR macros), but > describing the mapping from IRQ# to the bit that needs to be set (or > cleared) seems much harder. I cannot generalize from one example, so > lacking documentation for any other Layerscape SOC, whatever I might > come up with might not actually be useful for other hardware, making it > rather pointless. But if you have any suggestions for how the DT > bindings might look, I'm all ears. You could have a list of <bit irq> pairs defining the mapping, for example. But I'd encourage you to get in touch with the Freescale/NXP folks and find out how this HW works. get_maintainers.pl gives me this: Shawn Guo <shawnguo@kernel.org> Tang Yuantian <Yuantian.Tang@nxp.com> Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Madalin Bucur <madalin.bucur@nxp.com> Minghuan Lian <Minghuan.Lian@nxp.com> Yuantian Tang <andy.tang@nxp.com> Yangbo Lu <yangbo.lu@nxp.com> "Horia Geantă" <horia.geanta@nxp.com> I suggest you spam them and find out. Thanks, M. -- Jazz is not dead. It just smells funny...
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> To: Rasmus Villemoes <rasmus.villemoes-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org>, Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>, Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> Cc: Alexander Stein <alexander.stein-93q1YBGzJSMe9JSWTWOYM3xStJ4P+DSV@public.gmane.org>, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: Re: [RFC] irqchip: add support for LS1021A external interrupt lines Date: Mon, 11 Dec 2017 18:29:59 +0000 [thread overview] Message-ID: <3b22d1ed-fe8f-b733-1543-86e89b493114@arm.com> (raw) In-Reply-To: <563e0aaa-faf9-ae6a-ccd4-2aa89d7e457b-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org> On 11/12/17 09:30, Rasmus Villemoes wrote: > On 2017-12-08 17:02, Marc Zyngier wrote: [...] >> Overall, it is a bit annoying that you just copied the driver altogether >> instead of trying to allow the common stuff to be shared between >> drivers. Most of this is just boilerplate code... > > Yes, it did annoy me as well. However, the real meat of this is which > bits of which register to poke to support a negative polarity irq, and > there doesn't seem to be a good way to express that in DT. The register > offset and the mapping from external irq# to the GIC one is reasonably > easy (and would thus get rid of my NIRQ and INTPCR macros), but > describing the mapping from IRQ# to the bit that needs to be set (or > cleared) seems much harder. I cannot generalize from one example, so > lacking documentation for any other Layerscape SOC, whatever I might > come up with might not actually be useful for other hardware, making it > rather pointless. But if you have any suggestions for how the DT > bindings might look, I'm all ears. You could have a list of <bit irq> pairs defining the mapping, for example. But I'd encourage you to get in touch with the Freescale/NXP folks and find out how this HW works. get_maintainers.pl gives me this: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> Tang Yuantian <Yuantian.Tang-3arQi8VN3Tc@public.gmane.org> Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org> Madalin Bucur <madalin.bucur-3arQi8VN3Tc@public.gmane.org> Minghuan Lian <Minghuan.Lian-3arQi8VN3Tc@public.gmane.org> Yuantian Tang <andy.tang-3arQi8VN3Tc@public.gmane.org> Yangbo Lu <yangbo.lu-3arQi8VN3Tc@public.gmane.org> "Horia Geantă" <horia.geanta-3arQi8VN3Tc@public.gmane.org> I suggest you spam them and find out. Thanks, M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2017-12-11 18:30 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-12-04 15:11 polarity inversion on LS1021a Rasmus Villemoes 2017-12-04 15:23 ` Marc Zyngier 2017-12-08 14:33 ` [RFC] irqchip: add support for LS1021A external interrupt lines Rasmus Villemoes 2017-12-08 14:33 ` Rasmus Villemoes 2017-12-08 15:11 ` Alexander Stein 2017-12-08 15:11 ` Alexander Stein 2017-12-08 16:09 ` Marc Zyngier 2017-12-08 16:09 ` Marc Zyngier 2017-12-11 9:08 ` Rasmus Villemoes 2017-12-11 9:08 ` Rasmus Villemoes 2017-12-11 9:45 ` Alexander Stein 2017-12-11 9:45 ` Alexander Stein 2017-12-11 10:02 ` Alexander Stein 2017-12-11 10:02 ` Alexander Stein 2017-12-11 13:45 ` Rasmus Villemoes 2017-12-11 13:45 ` Rasmus Villemoes 2017-12-11 14:06 ` Rasmus Villemoes 2017-12-11 14:06 ` Rasmus Villemoes 2017-12-11 14:38 ` Alexander Stein 2017-12-11 14:38 ` Alexander Stein 2017-12-08 16:02 ` Marc Zyngier 2017-12-08 16:02 ` Marc Zyngier 2017-12-11 9:30 ` Rasmus Villemoes 2017-12-11 9:30 ` Rasmus Villemoes 2017-12-11 18:29 ` Marc Zyngier [this message] 2017-12-11 18:29 ` Marc Zyngier 2017-12-12 23:28 ` Rob Herring 2017-12-12 23:28 ` Rob Herring 2017-12-15 22:55 ` Rasmus Villemoes 2017-12-15 22:55 ` Rasmus Villemoes 2017-12-21 22:45 ` Rob Herring 2017-12-21 22:45 ` Rob Herring 2017-12-20 8:30 ` [PATCH v2 1/2] irqchip: add support for Layerscape " Rasmus Villemoes 2017-12-20 8:30 ` [PATCH v2 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes 2017-12-20 8:30 ` Rasmus Villemoes 2017-12-21 22:44 ` Rob Herring 2017-12-21 22:44 ` Rob Herring 2018-01-22 9:21 ` [PATCH v3 1/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes 2018-01-22 9:21 ` [PATCH v3 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes 2018-01-22 9:21 ` Rasmus Villemoes 2018-01-24 15:28 ` Marc Zyngier 2018-01-25 15:02 ` [PATCH v4 1/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes 2018-01-25 15:02 ` [PATCH v4 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes 2018-01-25 15:02 ` Rasmus Villemoes 2018-02-05 6:07 ` Rob Herring 2018-02-05 6:07 ` Rob Herring 2018-02-08 15:08 ` Rasmus Villemoes 2018-02-09 9:47 ` Marc Zyngier 2018-02-09 9:47 ` Marc Zyngier 2018-02-23 21:08 ` [PATCH v5 0/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes 2018-02-23 21:08 ` [PATCH v5 1/2] " Rasmus Villemoes 2018-03-01 12:16 ` Thomas Gleixner 2018-05-04 7:44 ` Rasmus Villemoes 2019-09-17 9:39 ` Kurt Kanzenbach 2018-02-23 21:09 ` [PATCH v5 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes 2018-03-02 19:49 ` Rob Herring 2018-05-04 8:07 ` Rasmus Villemoes 2017-12-04 15:31 ` polarity inversion on LS1021a Alexander Stein 2017-12-04 15:37 ` Marc Zyngier 2017-12-04 16:04 ` Alexander Stein
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