From: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
To: Alexander Stein <alexander.stein@systec-electronic.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [RFC] irqchip: add support for LS1021A external interrupt lines
Date: Mon, 11 Dec 2017 14:45:39 +0100 [thread overview]
Message-ID: <42019fb5-393a-08b0-924d-bf1a97e078fe@prevas.dk> (raw)
In-Reply-To: <2475814.YIHTfursNv@ws-stein>
On 2017-12-11 11:02, Alexander Stein wrote:
> Oh, and what is the content of register SCFG_SCFGREVCR?
Good point. On my board it's 0xffffffff, set even before U-boot starts,
and lots board support code in U-boot expects this. I can't immediately
find examples in the linux source code that actually writes to the scfg,
so I don't know if we already have that as an implicit assumption as
well. But it would be kind of nasty to have to make the code read
SCFG_SCFGREVCR and decide the bit pattern to use based on that -
especially since I wouldn't be able to test it.
Who thought such a magic switch could ever be a good idea?
--
Rasmus Villemoes
Software Developer
Prevas A/S
Hedeager 3
DK-8200 Aarhus N
+45 51210274
rasmus.villemoes@prevas.dk
www.prevas.dk
WARNING: multiple messages have this Message-ID (diff)
From: Rasmus Villemoes <rasmus.villemoes-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org>
To: Alexander Stein
<alexander.stein-93q1YBGzJSMe9JSWTWOYM3xStJ4P+DSV@public.gmane.org>
Cc: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>,
Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>,
Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [RFC] irqchip: add support for LS1021A external interrupt lines
Date: Mon, 11 Dec 2017 14:45:39 +0100 [thread overview]
Message-ID: <42019fb5-393a-08b0-924d-bf1a97e078fe@prevas.dk> (raw)
In-Reply-To: <2475814.YIHTfursNv@ws-stein>
On 2017-12-11 11:02, Alexander Stein wrote:
> Oh, and what is the content of register SCFG_SCFGREVCR?
Good point. On my board it's 0xffffffff, set even before U-boot starts,
and lots board support code in U-boot expects this. I can't immediately
find examples in the linux source code that actually writes to the scfg,
so I don't know if we already have that as an implicit assumption as
well. But it would be kind of nasty to have to make the code read
SCFG_SCFGREVCR and decide the bit pattern to use based on that -
especially since I wouldn't be able to test it.
Who thought such a magic switch could ever be a good idea?
--
Rasmus Villemoes
Software Developer
Prevas A/S
Hedeager 3
DK-8200 Aarhus N
+45 51210274
rasmus.villemoes-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org
www.prevas.dk
--
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next prev parent reply other threads:[~2017-12-11 13:45 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-04 15:11 polarity inversion on LS1021a Rasmus Villemoes
2017-12-04 15:23 ` Marc Zyngier
2017-12-08 14:33 ` [RFC] irqchip: add support for LS1021A external interrupt lines Rasmus Villemoes
2017-12-08 14:33 ` Rasmus Villemoes
2017-12-08 15:11 ` Alexander Stein
2017-12-08 15:11 ` Alexander Stein
2017-12-08 16:09 ` Marc Zyngier
2017-12-08 16:09 ` Marc Zyngier
2017-12-11 9:08 ` Rasmus Villemoes
2017-12-11 9:08 ` Rasmus Villemoes
2017-12-11 9:45 ` Alexander Stein
2017-12-11 9:45 ` Alexander Stein
2017-12-11 10:02 ` Alexander Stein
2017-12-11 10:02 ` Alexander Stein
2017-12-11 13:45 ` Rasmus Villemoes [this message]
2017-12-11 13:45 ` Rasmus Villemoes
2017-12-11 14:06 ` Rasmus Villemoes
2017-12-11 14:06 ` Rasmus Villemoes
2017-12-11 14:38 ` Alexander Stein
2017-12-11 14:38 ` Alexander Stein
2017-12-08 16:02 ` Marc Zyngier
2017-12-08 16:02 ` Marc Zyngier
2017-12-11 9:30 ` Rasmus Villemoes
2017-12-11 9:30 ` Rasmus Villemoes
2017-12-11 18:29 ` Marc Zyngier
2017-12-11 18:29 ` Marc Zyngier
2017-12-12 23:28 ` Rob Herring
2017-12-12 23:28 ` Rob Herring
2017-12-15 22:55 ` Rasmus Villemoes
2017-12-15 22:55 ` Rasmus Villemoes
2017-12-21 22:45 ` Rob Herring
2017-12-21 22:45 ` Rob Herring
2017-12-20 8:30 ` [PATCH v2 1/2] irqchip: add support for Layerscape " Rasmus Villemoes
2017-12-20 8:30 ` [PATCH v2 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
2017-12-20 8:30 ` Rasmus Villemoes
2017-12-21 22:44 ` Rob Herring
2017-12-21 22:44 ` Rob Herring
2018-01-22 9:21 ` [PATCH v3 1/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes
2018-01-22 9:21 ` [PATCH v3 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
2018-01-22 9:21 ` Rasmus Villemoes
2018-01-24 15:28 ` Marc Zyngier
2018-01-25 15:02 ` [PATCH v4 1/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes
2018-01-25 15:02 ` [PATCH v4 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
2018-01-25 15:02 ` Rasmus Villemoes
2018-02-05 6:07 ` Rob Herring
2018-02-05 6:07 ` Rob Herring
2018-02-08 15:08 ` Rasmus Villemoes
2018-02-09 9:47 ` Marc Zyngier
2018-02-09 9:47 ` Marc Zyngier
2018-02-23 21:08 ` [PATCH v5 0/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes
2018-02-23 21:08 ` [PATCH v5 1/2] " Rasmus Villemoes
2018-03-01 12:16 ` Thomas Gleixner
2018-05-04 7:44 ` Rasmus Villemoes
2019-09-17 9:39 ` Kurt Kanzenbach
2018-02-23 21:09 ` [PATCH v5 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
2018-03-02 19:49 ` Rob Herring
2018-05-04 8:07 ` Rasmus Villemoes
2017-12-04 15:31 ` polarity inversion on LS1021a Alexander Stein
2017-12-04 15:37 ` Marc Zyngier
2017-12-04 16:04 ` Alexander Stein
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