* [REGRESSION] e1000e failure triggered by "PCI: Remove MRRS modification from MPS setting code" @ 2011-09-27 17:01 Avi Kivity 2011-09-27 17:59 ` Jon Mason 0 siblings, 1 reply; 26+ messages in thread From: Avi Kivity @ 2011-09-27 17:01 UTC (permalink / raw) To: Jon Mason Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci Commit ed2888e906b567 (merged 3.1-rc6) causes a reproducible failure with my e1000e card here. Starting a kvm guest (which mostly consists of shoving display updates over X over ssh, as far as the network is concerned) locks up the card hard. The failure is easily reproducible, will gladly test patches. -- error compiling committee.c: too many arguments to function ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [REGRESSION] e1000e failure triggered by "PCI: Remove MRRS modification from MPS setting code" 2011-09-27 17:01 [REGRESSION] e1000e failure triggered by "PCI: Remove MRRS modification from MPS setting code" Avi Kivity @ 2011-09-27 17:59 ` Jon Mason 2011-09-27 18:28 ` Avi Kivity 0 siblings, 1 reply; 26+ messages in thread From: Jon Mason @ 2011-09-27 17:59 UTC (permalink / raw) To: Avi Kivity Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci On Tue, Sep 27, 2011 at 12:01 PM, Avi Kivity <avi@redhat.com> wrote: > Commit ed2888e906b567 (merged 3.1-rc6) causes a reproducible failure with my > e1000e card here. Starting a kvm guest (which mostly consists of shoving > display updates over X over ssh, as far as the network is concerned) locks > up the card hard. > > The failure is easily reproducible, will gladly test patches. Does the problem occur with the adapter assigned to the kvm guest or the host? I assume that you are running with the default behavior and not with the boot arg "pci=pcie_bus_perf". Can you get the dmesg output (specifically the lines that have "Dev MPS") and lspci -vvv on the host? Is this an e1000e 4port adapter? Thanks, Jon > > -- > error compiling committee.c: too many arguments to function > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [REGRESSION] e1000e failure triggered by "PCI: Remove MRRS modification from MPS setting code" 2011-09-27 17:59 ` Jon Mason @ 2011-09-27 18:28 ` Avi Kivity 2011-09-27 20:11 ` Jon Mason 2011-09-30 0:16 ` Workaround for Intel MPS errata Jon Mason 0 siblings, 2 replies; 26+ messages in thread From: Avi Kivity @ 2011-09-27 18:28 UTC (permalink / raw) To: Jon Mason Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci On 09/27/2011 08:59 PM, Jon Mason wrote: > On Tue, Sep 27, 2011 at 12:01 PM, Avi Kivity<avi@redhat.com> wrote: > > Commit ed2888e906b567 (merged 3.1-rc6) causes a reproducible failure with my > > e1000e card here. Starting a kvm guest (which mostly consists of shoving > > display updates over X over ssh, as far as the network is concerned) locks > > up the card hard. > > > > The failure is easily reproducible, will gladly test patches. > > Does the problem occur with the adapter assigned to the kvm guest or > the host? The host. It's not even using vhost-net or tap or bridge. In fact the failure happens before the guest has set up neworking itself (in grub, while clearing the screen); all of the networking load is due to tunnelling X over ssh. > I assume that you are running with the default behavior and > not with the boot arg "pci=pcie_bus_perf". Correct. > Can you get the dmesg > output (specifically the lines that have "Dev MPS") (this is with the patch reverted) Sep 27 20:42:48 violet-regb kernel: pci 0000:02:02.0: PCI bridge to [bus 04-04] Sep 27 20:42:48 violet-regb kernel: pci 0000:01:00.3: PCI bridge to [bus 05-05] Sep 27 20:42:48 violet-regb kernel: pci 0000:00:03.0: PCI bridge to [bus 06-06] Sep 27 20:42:48 violet-regb kernel: pci 0000:00:1c.0: PCI bridge to [bus 07-07] Sep 27 20:42:48 violet-regb kernel: pci 0000:00:1e.0: PCI bridge to [bus 08-08] (subtractive decode) Sep 27 20:42:48 violet-regb kernel: pci 0000:00:02.0: Dev MPS 128 MPSS 256 MRRS 128 Sep 27 20:42:48 violet-regb kernel: pci 0000:00:02.0: Dev MPS 256 MPSS 256 MRRS 128 Sep 27 20:42:48 violet-regb kernel: pci 0000:01:00.0: Dev MPS 128 MPSS 256 MRRS 4096 Sep 27 20:42:48 violet-regb kernel: pci 0000:01:00.0: Dev MPS 256 MPSS 256 MRRS 128 Sep 27 20:42:48 violet-regb kernel: pci 0000:02:00.0: Dev MPS 128 MPSS 256 MRRS 2048 Sep 27 20:42:48 violet-regb kernel: pci 0000:02:00.0: Dev MPS 256 MPSS 256 MRRS 128 Sep 27 20:42:48 violet-regb kernel: pci 0000:02:02.0: Dev MPS 128 MPSS 256 MRRS 2048 Sep 27 20:42:48 violet-regb kernel: pci 0000:02:02.0: Dev MPS 256 MPSS 256 MRRS 128 Sep 27 20:42:48 violet-regb kernel: pci 0000:04:00.0: Dev MPS 128 MPSS 256 MRRS 512 Sep 27 20:42:48 violet-regb kernel: pci 0000:04:00.0: Dev MPS 256 MPSS 256 MRRS 128 Sep 27 20:42:48 violet-regb kernel: pci 0000:04:00.1: Dev MPS 128 MPSS 256 MRRS 512 Sep 27 20:42:48 violet-regb kernel: pci 0000:04:00.1: Dev MPS 256 MPSS 256 MRRS 128 Sep 27 20:42:48 violet-regb kernel: pci 0000:01:00.3: Dev MPS 256 MPSS 256 MRRS 256 Sep 27 20:42:48 violet-regb kernel: pci 0000:01:00.3: Dev MPS 256 MPSS 256 MRRS 256 Sep 27 20:42:48 violet-regb kernel: pci 0000:00:03.0: Dev MPS 128 MPSS 256 MRRS 128 Sep 27 20:42:48 violet-regb kernel: pci 0000:00:03.0: Dev MPS 256 MPSS 256 MRRS 128 Sep 27 20:42:48 violet-regb kernel: pci 0000:00:1c.0: Dev MPS 128 MPSS 128 MRRS 128 Sep 27 20:42:48 violet-regb kernel: pci 0000:00:1c.0: Dev MPS 128 MPSS 128 MRRS 128 Sep 27 20:42:48 violet-regb kernel: pci0000:00: Requesting ACPI _OSC control (0x1d) Sep 27 20:42:48 violet-regb kernel: pci0000:00: ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d Sep 27 20:42:48 violet-regb kernel: ACPI _OSC control for PCIe not granted, disabling ASPM Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 *7 10 11 14 15) Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 *5 6 7 10 11 14 15) Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 *10 11 14 15) Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 10 *11 14 15) Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 11 14 15) *0, disabled. Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKF] (IRQs 4 5 6 7 10 11 14 15) *0, disabled. Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 11 14 15) *0, disabled. > and lspci -vvv on > the host? # lspci -vvv 00:00.0 Host bridge: Intel Corporation 5000V Chipset Memory Controller Hub (rev 92) Subsystem: Tyan Computer Device 5372 Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 0 Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit- Address: fee00000 Data: 0000 Capabilities: [6c] Express (v1) Root Port (Slot-), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Surprise+ LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 15, GenCap- CGenEn- ChkCap- ChkEn- 00:02.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x8 Port 2-3 (rev 92) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=01, subordinate=05, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: df100000-df2fffff Prefetchable memory behind bridge: 00000000d0000000-00000000d00fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit- Address: fee00000 Data: 0000 Capabilities: [6c] Express (v1) Root Port (Slot-), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 256 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Surprise+ LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- RootCtl: ErrCorrectable+ ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Kernel driver in use: pcieport 00:03.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x4 Port 3 (rev 92) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit- Address: fee00000 Data: 0000 Capabilities: [6c] Express (v1) Root Port (Slot-), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 256 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #3, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Surprise+ LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- RootCtl: ErrCorrectable+ ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Kernel driver in use: pcieport 00:08.0 System peripheral: Intel Corporation 5000 Series Chipset DMA Engine (rev 92) Subsystem: Intel Corporation Device 8086 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 0 Region 0: Memory at fe700000 (64-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] MSI: Enable- Count=1/1 Maskable- 64bit- Address: fee00000 Data: 0000 Capabilities: [6c] Express (v1) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal+ Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM unknown, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- 00:10.0 Host bridge: Intel Corporation 5000 Series Chipset FSB Registers (rev 92) Subsystem: Intel Corporation Device 8086 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:10.1 Host bridge: Intel Corporation 5000 Series Chipset FSB Registers (rev 92) Subsystem: Intel Corporation Device 8086 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:10.2 Host bridge: Intel Corporation 5000 Series Chipset FSB Registers (rev 92) Subsystem: Intel Corporation Device 8086 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:11.0 Host bridge: Intel Corporation 5000 Series Chipset Reserved Registers (rev 92) Subsystem: Intel Corporation Device 8086 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:13.0 Host bridge: Intel Corporation 5000 Series Chipset Reserved Registers (rev 92) Subsystem: Intel Corporation Device 8086 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:15.0 Host bridge: Intel Corporation 5000 Series Chipset FBD Registers (rev 92) Subsystem: Intel Corporation Device 8086 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:16.0 Host bridge: Intel Corporation 5000 Series Chipset FBD Registers (rev 92) Subsystem: Intel Corporation Device 8086 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:1c.0 PCI bridge: Intel Corporation 631xESB/632xESB/3100 Chipset PCI Express Root Port 1 (rev 09) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=07, subordinate=07, sec-latency=0 I/O behind bridge: 00004000-00004fff Memory behind bridge: d0100000-d02fffff Prefetchable memory behind bridge: 00000000d0300000-00000000d04fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag+ RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #0, PowerLimit 0.000W; Interlock- NoCompl- SltCtl: Enable: AttnBtn+ PwrFlt- MRL- PresDet+ CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4151 Capabilities: [90] Subsystem: Tyan Computer Device 5372 Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed+ WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 Status: NegoPending- InProgress- Capabilities: [180 v1] Root Complex Link Desc: PortNumber=01 ComponentID=02 EltType=Config Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ Addr: 00000000fed1c001 Kernel driver in use: pcieport 00:1d.0 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #1 (rev 09) (prog-if 00 [UHCI]) Subsystem: Tyan Computer Device 5372 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 17 Region 4: I/O ports at 1800 [size=32] Kernel driver in use: uhci_hcd 00:1d.1 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #2 (rev 09) (prog-if 00 [UHCI]) Subsystem: Tyan Computer Device 5372 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 4: I/O ports at 1820 [size=32] Kernel driver in use: uhci_hcd 00:1d.2 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #3 (rev 09) (prog-if 00 [UHCI]) Subsystem: Tyan Computer Device 5372 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at 1840 [size=32] Kernel driver in use: uhci_hcd 00:1d.3 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #4 (rev 09) (prog-if 00 [UHCI]) Subsystem: Tyan Computer Device 5372 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin D routed to IRQ 16 Region 4: I/O ports at 1860 [size=32] Kernel driver in use: uhci_hcd 00:1d.7 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset EHCI USB2 Controller (rev 09) (prog-if 20 [EHCI]) Subsystem: Intel Corporation 631xESB/632xESB/3100 Chipset EHCI USB2 Controller Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 17 Region 0: Memory at df500000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Kernel driver in use: ehci_hcd 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev d9) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=08, subordinate=08, sec-latency=32 I/O behind bridge: 00003000-00003fff Memory behind bridge: df000000-df0fffff Prefetchable memory behind bridge: 00000000de000000-00000000deffffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Subsystem: Tyan Computer Device 5372 00:1f.0 ISA bridge: Intel Corporation 631xESB/632xESB/3100 Chipset LPC Interface Controller (rev 09) Subsystem: Tyan Computer Device 5372 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00:1f.2 IDE interface: Intel Corporation 631xESB/632xESB/3100 Chipset SATA IDE Controller (rev 09) (prog-if 80 [Master]) Subsystem: Tyan Computer Device 5372 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 0: I/O ports at 01f0 [size=8] Region 1: I/O ports at 03f4 [size=1] Region 2: I/O ports at 0170 [size=8] Region 3: I/O ports at 0374 [size=1] Region 4: I/O ports at 18b0 [size=16] Capabilities: [70] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ata_piix Kernel modules: ata_generic, pata_acpi 00:1f.3 SMBus: Intel Corporation 631xESB/632xESB/3100 Chipset SMBus Controller (rev 09) Subsystem: Tyan Computer Device 5372 Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at 1100 [size=32] Kernel driver in use: i801_smbus Kernel modules: i2c-i801 01:00.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Upstream Port (rev 01) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=01, secondary=02, subordinate=04, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: df200000-df2fffff Prefetchable memory behind bridge: 00000000d0000000-00000000d00fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [44] Express (v1) Upstream Port, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-SlotPowerLimit 0.000W DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 256 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [70] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] Subsystem: Tyan Computer Device 5372 Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn- Kernel driver in use: pcieport 01:00.3 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express to PCI-X Bridge (rev 01) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=01, secondary=05, subordinate=05, sec-latency=64 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz+ FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [44] Express (v1) PCI/PCI-X Bridge, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal+ Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- MaxPayload 256 bytes, MaxReadReq 256 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [6c] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] Subsystem: Tyan Computer Device 5372 Capabilities: [d8] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=133MHz Status: Dev=00:00.3 64bit- 133MHz- SCD- USC- SCO- SRD- Upstream: Capacity=65535 CommitmentLimit=65535 Downstream: Capacity=65535 CommitmentLimit=65535 Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn- 02:00.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Downstream Port E1 (rev 01) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=02, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [44] Express (v1) Downstream Port (Slot-), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 256 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 <512ns, L1 unlimited ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [60] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] Subsystem: Tyan Computer Device 5372 Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Kernel driver in use: pcieport 02:02.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Downstream Port E3 (rev 01) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=02, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: df200000-df2fffff Prefetchable memory behind bridge: 00000000d0000000-00000000d00fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [44] Express (v1) Downstream Port (Slot-), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 256 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [60] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] Subsystem: Tyan Computer Device 5372 Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Kernel driver in use: pcieport 04:00.0 Ethernet controller: Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper) (rev 01) Subsystem: Tyan Computer Device 5300 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 65 Region 0: Memory at df220000 (32-bit, non-prefetchable) [size=128K] Region 1: Memory at df200000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at 2000 [size=32] [virtual] Expansion ROM at d0000000 [disabled] [size=64K] Capabilities: [c8] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0100c Data: 4179 Capabilities: [e0] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 256 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <128ns, L1 <64us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO+ CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [140 v1] Device Serial Number 00-e0-81-ff-ff-44-3f-4e Kernel driver in use: e1000e Kernel modules: e1000e 04:00.1 Ethernet controller: Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper) (rev 01) Subsystem: Tyan Computer Device 5300 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin B routed to IRQ 66 Region 0: Memory at df260000 (32-bit, non-prefetchable) [size=128K] Region 1: Memory at df240000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at 2020 [size=32] [virtual] Expansion ROM at d0010000 [disabled] [size=64K] Capabilities: [c8] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0200c Data: 4189 Capabilities: [e0] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 256 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <128ns, L1 <64us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [140 v1] Device Serial Number 00-e0-81-ff-ff-44-3f-4e Kernel driver in use: e1000e Kernel modules: e1000e 08:01.0 VGA compatible controller: XGI Technology Inc. (eXtreme Graphics Innovation) Z7/Z9 (XG20 core) (prog-if 00 [VGA controller]) Subsystem: XGI Technology Inc. (eXtreme Graphics Innovation) Z7/Z9 (XG20 core) Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- BIST result: 00 Region 0: Memory at de000000 (32-bit, prefetchable) [size=16M] Region 1: Memory at df000000 (32-bit, non-prefetchable) [size=256K] Region 2: I/O ports at 3000 [size=128] Expansion ROM at <unassigned> [disabled] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 08:02.0 Ethernet controller: Intel Corporation 82557/8/9/0/1 Ethernet Pro 100 (rev 10) Subsystem: Intel Corporation EtherExpress PRO/100 S Server Adapter Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 66 (2000ns min, 14000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 10 Region 0: Memory at df060000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at 3080 [size=64] Region 2: Memory at df040000 (32-bit, non-prefetchable) [size=128K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME- > Is this an e1000e 4port adapter? Dual port. -- I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [REGRESSION] e1000e failure triggered by "PCI: Remove MRRS modification from MPS setting code" 2011-09-27 18:28 ` Avi Kivity @ 2011-09-27 20:11 ` Jon Mason 2011-09-29 4:33 ` Benjamin Herrenschmidt 2011-09-30 0:16 ` Workaround for Intel MPS errata Jon Mason 1 sibling, 1 reply; 26+ messages in thread From: Jon Mason @ 2011-09-27 20:11 UTC (permalink / raw) To: Avi Kivity Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci On Tue, Sep 27, 2011 at 1:28 PM, Avi Kivity <avi@redhat.com> wrote: > On 09/27/2011 08:59 PM, Jon Mason wrote: >> >> On Tue, Sep 27, 2011 at 12:01 PM, Avi Kivity<avi@redhat.com> wrote: >> > Commit ed2888e906b567 (merged 3.1-rc6) causes a reproducible failure >> > with my >> > e1000e card here. Starting a kvm guest (which mostly consists of >> > shoving >> > display updates over X over ssh, as far as the network is concerned) >> > locks >> > up the card hard. >> > >> > The failure is easily reproducible, will gladly test patches. >> >> Does the problem occur with the adapter assigned to the kvm guest or >> the host? > > The host. It's not even using vhost-net or tap or bridge. In fact the > failure happens before the guest has set up neworking itself (in grub, while > clearing the screen); all of the networking load is due to tunnelling X over > ssh. > >> I assume that you are running with the default behavior and >> not with the boot arg "pci=pcie_bus_perf". > > Correct. > >> Can you get the dmesg >> output (specifically the lines that have "Dev MPS") > > (this is with the patch reverted) Booting with "pci=pcie_bus_perf" should provide you with the same behavior as before (e.g., with the patch reverted). This should enable you work around this issue until I can get it resolved. On the positive side, your system should be 10% faster than it was in 3.0 (due to the PCI bus payloads being 2x larger). If you can provide the same output with the patch not reverted, it would be very beneficial. Based on your description, the lockup only occurs with traffic. You can gather this before any traffic goes out (perhaps booting without networking enabled). > > Sep 27 20:42:48 violet-regb kernel: pci 0000:02:02.0: PCI bridge to [bus > 04-04] > Sep 27 20:42:48 violet-regb kernel: pci 0000:01:00.3: PCI bridge to [bus > 05-05] > Sep 27 20:42:48 violet-regb kernel: pci 0000:00:03.0: PCI bridge to [bus > 06-06] > Sep 27 20:42:48 violet-regb kernel: pci 0000:00:1c.0: PCI bridge to [bus > 07-07] > Sep 27 20:42:48 violet-regb kernel: pci 0000:00:1e.0: PCI bridge to [bus > 08-08] (subtractive decode) > Sep 27 20:42:48 violet-regb kernel: pci 0000:00:02.0: Dev MPS 128 MPSS 256 > MRRS 128 > Sep 27 20:42:48 violet-regb kernel: pci 0000:00:02.0: Dev MPS 256 MPSS 256 > MRRS 128 > Sep 27 20:42:48 violet-regb kernel: pci 0000:01:00.0: Dev MPS 128 MPSS 256 > MRRS 4096 > Sep 27 20:42:48 violet-regb kernel: pci 0000:01:00.0: Dev MPS 256 MPSS 256 > MRRS 128 > Sep 27 20:42:48 violet-regb kernel: pci 0000:02:00.0: Dev MPS 128 MPSS 256 > MRRS 2048 > Sep 27 20:42:48 violet-regb kernel: pci 0000:02:00.0: Dev MPS 256 MPSS 256 > MRRS 128 > Sep 27 20:42:48 violet-regb kernel: pci 0000:02:02.0: Dev MPS 128 MPSS 256 > MRRS 2048 > Sep 27 20:42:48 violet-regb kernel: pci 0000:02:02.0: Dev MPS 256 MPSS 256 > MRRS 128 > Sep 27 20:42:48 violet-regb kernel: pci 0000:04:00.0: Dev MPS 128 MPSS 256 > MRRS 512 > Sep 27 20:42:48 violet-regb kernel: pci 0000:04:00.0: Dev MPS 256 MPSS 256 > MRRS 128 > Sep 27 20:42:48 violet-regb kernel: pci 0000:04:00.1: Dev MPS 128 MPSS 256 > MRRS 512 > Sep 27 20:42:48 violet-regb kernel: pci 0000:04:00.1: Dev MPS 256 MPSS 256 > MRRS 128 > Sep 27 20:42:48 violet-regb kernel: pci 0000:01:00.3: Dev MPS 256 MPSS 256 > MRRS 256 > Sep 27 20:42:48 violet-regb kernel: pci 0000:01:00.3: Dev MPS 256 MPSS 256 > MRRS 256 > Sep 27 20:42:48 violet-regb kernel: pci 0000:00:03.0: Dev MPS 128 MPSS 256 > MRRS 128 > Sep 27 20:42:48 violet-regb kernel: pci 0000:00:03.0: Dev MPS 256 MPSS 256 > MRRS 128 > Sep 27 20:42:48 violet-regb kernel: pci 0000:00:1c.0: Dev MPS 128 MPSS 128 > MRRS 128 > Sep 27 20:42:48 violet-regb kernel: pci 0000:00:1c.0: Dev MPS 128 MPSS 128 > MRRS 128 > Sep 27 20:42:48 violet-regb kernel: pci0000:00: Requesting ACPI _OSC control > (0x1d) > Sep 27 20:42:48 violet-regb kernel: pci0000:00: ACPI _OSC request failed > (AE_NOT_FOUND), returned control mask: 0x1d > Sep 27 20:42:48 violet-regb kernel: ACPI _OSC control for PCIe not granted, > disabling ASPM > Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKA] (IRQs 3 > 4 5 6 *7 10 11 14 15) > Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKB] (IRQs 3 > 4 *5 6 7 10 11 14 15) > Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKC] (IRQs 3 > 4 5 6 7 *10 11 14 15) > Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKD] (IRQs 3 > 4 5 6 7 10 *11 14 15) > Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKE] (IRQs 3 > 4 5 6 7 10 11 14 15) *0, disabled. > Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKF] (IRQs 4 > 5 6 7 10 11 14 15) *0, disabled. > Sep 27 20:42:48 violet-regb kernel: ACPI: PCI Interrupt Link [LNKG] (IRQs 3 > 4 5 6 7 10 11 14 15) *0, disabled. > > >> and lspci -vvv on >> the host? `lspci -vt` might also help by making the bus hierarchy known. > > # lspci -vvv > 00:00.0 Host bridge: Intel Corporation 5000V Chipset Memory Controller Hub > (rev 92) > Subsystem: Tyan Computer Device 5372 > Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Interrupt: pin A routed to IRQ 0 > Capabilities: [50] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit- > Address: fee00000 Data: 0000 > Capabilities: [6c] Express (v1) Root Port (Slot-), MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, > L1 unlimited > ExtTag- RBE- FLReset- > DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ > MaxPayload 128 bytes, MaxReadReq 128 bytes > DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- > TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 > unlimited, L1 unlimited > ClockPM- Surprise+ LLActRep+ BwNot- > LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ > BWMgmt- ABWMgmt- > RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- > CRSVisible- > RootCap: CRSVisible- > RootSta: PME ReqID 0000, PMEStatus- PMEPending- > Capabilities: [100 v1] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol+ > UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ > MalfTLP+ ECRC- UnsupReq- ACSViol+ > CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > AERCap: First Error Pointer: 15, GenCap- CGenEn- ChkCap- ChkEn- > > 00:02.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x8 > Port 2-3 (rev 92) (prog-if 00 [Normal decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Bus: primary=00, secondary=01, subordinate=05, sec-latency=0 > I/O behind bridge: 00002000-00002fff > Memory behind bridge: df100000-df2fffff > Prefetchable memory behind bridge: 00000000d0000000-00000000d00fffff > Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- <SERR- <PERR- > BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- > PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- > Capabilities: [50] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit- > Address: fee00000 Data: 0000 > Capabilities: [6c] Express (v1) Root Port (Slot-), MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, > L1 unlimited > ExtTag- RBE- FLReset- > DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ > MaxPayload 256 bytes, MaxReadReq 128 bytes > DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- > TransPend- > LnkCap: Port #2, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 > unlimited, L1 unlimited > ClockPM- Surprise+ LLActRep+ BwNot- > LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ > BWMgmt- ABWMgmt- > RootCtl: ErrCorrectable+ ErrNon-Fatal- ErrFatal- PMEIntEna- > CRSVisible- > RootCap: CRSVisible- > RootSta: PME ReqID 0000, PMEStatus- PMEPending- > Capabilities: [100 v1] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ > MalfTLP+ ECRC- UnsupReq- ACSViol- > CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- > Kernel driver in use: pcieport > > 00:03.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x4 > Port 3 (rev 92) (prog-if 00 [Normal decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 > I/O behind bridge: 0000f000-00000fff > Memory behind bridge: fff00000-000fffff > Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff > Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- <SERR- <PERR- > BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- > PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- > Capabilities: [50] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [58] MSI: Enable- Count=1/2 Maskable- 64bit- > Address: fee00000 Data: 0000 > Capabilities: [6c] Express (v1) Root Port (Slot-), MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, > L1 unlimited > ExtTag- RBE- FLReset- > DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ > MaxPayload 256 bytes, MaxReadReq 128 bytes > DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- > TransPend- > LnkCap: Port #3, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 > unlimited, L1 unlimited > ClockPM- Surprise+ LLActRep+ BwNot- > LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- > BWMgmt- ABWMgmt- > RootCtl: ErrCorrectable+ ErrNon-Fatal- ErrFatal- PMEIntEna- > CRSVisible- > RootCap: CRSVisible- > RootSta: PME ReqID 0000, PMEStatus- PMEPending- > Capabilities: [100 v1] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ > MalfTLP+ ECRC- UnsupReq- ACSViol- > CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- > Kernel driver in use: pcieport > > 00:08.0 System peripheral: Intel Corporation 5000 Series Chipset DMA Engine > (rev 92) > Subsystem: Intel Corporation Device 8086 > Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0 > Interrupt: pin A routed to IRQ 0 > Region 0: Memory at fe700000 (64-bit, non-prefetchable) [size=1K] > Capabilities: [50] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [58] MSI: Enable- Count=1/1 Maskable- 64bit- > Address: fee00000 Data: 0000 > Capabilities: [6c] Express (v1) Root Complex Integrated Endpoint, MSI 00 > DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 > <1us > ExtTag- RBE- FLReset- > DevCtl: Report errors: Correctable- Non-Fatal- Fatal+ Unsupported- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- > MaxPayload 128 bytes, MaxReadReq 128 bytes > DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- > TransPend- > LnkCap: Port #0, Speed unknown, Width x0, ASPM unknown, Latency L0 > <64ns, L1 <1us > ClockPM- Surprise- LLActRep- BwNot- > LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- > BWMgmt- ABWMgmt- > > 00:10.0 Host bridge: Intel Corporation 5000 Series Chipset FSB Registers > (rev 92) > Subsystem: Intel Corporation Device 8086 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > > 00:10.1 Host bridge: Intel Corporation 5000 Series Chipset FSB Registers > (rev 92) > Subsystem: Intel Corporation Device 8086 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > > 00:10.2 Host bridge: Intel Corporation 5000 Series Chipset FSB Registers > (rev 92) > Subsystem: Intel Corporation Device 8086 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > > 00:11.0 Host bridge: Intel Corporation 5000 Series Chipset Reserved > Registers (rev 92) > Subsystem: Intel Corporation Device 8086 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > > 00:13.0 Host bridge: Intel Corporation 5000 Series Chipset Reserved > Registers (rev 92) > Subsystem: Intel Corporation Device 8086 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > > 00:15.0 Host bridge: Intel Corporation 5000 Series Chipset FBD Registers > (rev 92) > Subsystem: Intel Corporation Device 8086 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > > 00:16.0 Host bridge: Intel Corporation 5000 Series Chipset FBD Registers > (rev 92) > Subsystem: Intel Corporation Device 8086 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > > 00:1c.0 PCI bridge: Intel Corporation 631xESB/632xESB/3100 Chipset PCI > Express Root Port 1 (rev 09) (prog-if 00 [Normal decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx+ > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Bus: primary=00, secondary=07, subordinate=07, sec-latency=0 > I/O behind bridge: 00004000-00004fff > Memory behind bridge: d0100000-d02fffff > Prefetchable memory behind bridge: 00000000d0300000-00000000d04fffff > Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- <SERR- <PERR- > BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- > PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- > Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 > DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, > L1 unlimited > ExtTag+ RBE- FLReset- > DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- > MaxPayload 128 bytes, MaxReadReq 128 bytes > DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ > TransPend- > LnkCap: Port #1, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 > <256ns, L1 <4us > ClockPM- Surprise- LLActRep- BwNot- > LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- > BWMgmt- ABWMgmt- > SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ > Slot #0, PowerLimit 0.000W; Interlock- NoCompl- > SltCtl: Enable: AttnBtn+ PwrFlt- MRL- PresDet+ CmdCplt- HPIrq- > LinkChg- > Control: AttnInd Off, PwrInd Off, Power- Interlock- > SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- > Interlock- > Changed: MRL- PresDet- LinkState- > RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- > CRSVisible- > RootCap: CRSVisible- > RootSta: PME ReqID 0000, PMEStatus- PMEPending- > Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- > Address: fee0300c Data: 4151 > Capabilities: [90] Subsystem: Tyan Computer Device 5372 > Capabilities: [a0] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [100 v1] Virtual Channel > Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 > Arb: Fixed+ WRR32- WRR64- WRR128- > Ctrl: ArbSelect=Fixed > Status: InProgress- > VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- > Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- > Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff > Status: NegoPending- InProgress- > VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- > Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- > Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 > Status: NegoPending- InProgress- > Capabilities: [180 v1] Root Complex Link > Desc: PortNumber=01 ComponentID=02 EltType=Config > Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- > LinkType=MemMapped LinkValid+ > Addr: 00000000fed1c001 > Kernel driver in use: pcieport > > 00:1d.0 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI > USB Controller #1 (rev 09) (prog-if 00 [UHCI]) > Subsystem: Tyan Computer Device 5372 > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0 > Interrupt: pin A routed to IRQ 17 > Region 4: I/O ports at 1800 [size=32] > Kernel driver in use: uhci_hcd > > 00:1d.1 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI > USB Controller #2 (rev 09) (prog-if 00 [UHCI]) > Subsystem: Tyan Computer Device 5372 > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0 > Interrupt: pin B routed to IRQ 19 > Region 4: I/O ports at 1820 [size=32] > Kernel driver in use: uhci_hcd > > 00:1d.2 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI > USB Controller #3 (rev 09) (prog-if 00 [UHCI]) > Subsystem: Tyan Computer Device 5372 > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0 > Interrupt: pin C routed to IRQ 18 > Region 4: I/O ports at 1840 [size=32] > Kernel driver in use: uhci_hcd > > 00:1d.3 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset UHCI > USB Controller #4 (rev 09) (prog-if 00 [UHCI]) > Subsystem: Tyan Computer Device 5372 > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0 > Interrupt: pin D routed to IRQ 16 > Region 4: I/O ports at 1860 [size=32] > Kernel driver in use: uhci_hcd > > 00:1d.7 USB Controller: Intel Corporation 631xESB/632xESB/3100 Chipset EHCI > USB2 Controller (rev 09) (prog-if 20 [EHCI]) > Subsystem: Intel Corporation 631xESB/632xESB/3100 Chipset EHCI USB2 > Controller > Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0 > Interrupt: pin A routed to IRQ 17 > Region 0: Memory at df500000 (32-bit, non-prefetchable) [size=1K] > Capabilities: [50] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [58] Debug port: BAR=1 offset=00a0 > Kernel driver in use: ehci_hcd > > 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev d9) (prog-if 01 > [Subtractive decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0 > Bus: primary=00, secondary=08, subordinate=08, sec-latency=32 > I/O behind bridge: 00003000-00003fff > Memory behind bridge: df000000-df0fffff > Prefetchable memory behind bridge: 00000000de000000-00000000deffffff > Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort+ <SERR- <PERR- > BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- > PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- > Capabilities: [50] Subsystem: Tyan Computer Device 5372 > > 00:1f.0 ISA bridge: Intel Corporation 631xESB/632xESB/3100 Chipset LPC > Interface Controller (rev 09) > Subsystem: Tyan Computer Device 5372 > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0 > > 00:1f.2 IDE interface: Intel Corporation 631xESB/632xESB/3100 Chipset SATA > IDE Controller (rev 09) (prog-if 80 [Master]) > Subsystem: Tyan Computer Device 5372 > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0 > Interrupt: pin B routed to IRQ 19 > Region 0: I/O ports at 01f0 [size=8] > Region 1: I/O ports at 03f4 [size=1] > Region 2: I/O ports at 0170 [size=8] > Region 3: I/O ports at 0374 [size=1] > Region 4: I/O ports at 18b0 [size=16] > Capabilities: [70] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA > PME(D0-,D1-,D2-,D3hot+,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Kernel driver in use: ata_piix > Kernel modules: ata_generic, pata_acpi > > 00:1f.3 SMBus: Intel Corporation 631xESB/632xESB/3100 Chipset SMBus > Controller (rev 09) > Subsystem: Tyan Computer Device 5372 > Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Interrupt: pin C routed to IRQ 18 > Region 4: I/O ports at 1100 [size=32] > Kernel driver in use: i801_smbus > Kernel modules: i2c-i801 > > 01:00.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Upstream > Port (rev 01) (prog-if 00 [Normal decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Bus: primary=01, secondary=02, subordinate=04, sec-latency=0 > I/O behind bridge: 00002000-00002fff > Memory behind bridge: df200000-df2fffff > Prefetchable memory behind bridge: 00000000d0000000-00000000d00fffff > Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- <SERR- <PERR- > BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- > PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- > Capabilities: [44] Express (v1) Upstream Port, MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 > <1us > ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-SlotPowerLimit > 0.000W > DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- > MaxPayload 256 bytes, MaxReadReq 128 bytes > DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- > TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 > unlimited, L1 unlimited > ClockPM- Surprise- LLActRep- BwNot- > LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- > BWMgmt- ABWMgmt- > Capabilities: [70] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [80] Subsystem: Tyan Computer Device 5372 > Capabilities: [100 v1] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq+ ACSViol- > UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ > MalfTLP+ ECRC- UnsupReq- ACSViol- > CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn- > Kernel driver in use: pcieport > > 01:00.3 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express to PCI-X > Bridge (rev 01) (prog-if 00 [Normal decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 64 bytes > Bus: primary=01, secondary=05, subordinate=05, sec-latency=64 > I/O behind bridge: 0000f000-00000fff > Memory behind bridge: fff00000-000fffff > Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff > Secondary status: 66MHz+ FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort+ <SERR- <PERR- > BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- > PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- > Capabilities: [44] Express (v1) PCI/PCI-X Bridge, MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 > <1us > ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- > DevCtl: Report errors: Correctable- Non-Fatal- Fatal+ Unsupported- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- > MaxPayload 256 bytes, MaxReadReq 256 bytes > DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- > TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 > unlimited, L1 unlimited > ClockPM- Surprise- LLActRep- BwNot- > LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk- DLActive- > BWMgmt- ABWMgmt- > Capabilities: [6c] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [80] Subsystem: Tyan Computer Device 5372 > Capabilities: [d8] PCI-X bridge device > Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=133MHz > Status: Dev=00:00.3 64bit- 133MHz- SCD- USC- SCO- SRD- > Upstream: Capacity=65535 CommitmentLimit=65535 > Downstream: Capacity=65535 CommitmentLimit=65535 > Capabilities: [100 v1] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq+ ACSViol- > UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ > MalfTLP+ ECRC- UnsupReq- ACSViol- > CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn- > > 02:00.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Downstream > Port E1 (rev 01) (prog-if 00 [Normal decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Bus: primary=02, secondary=03, subordinate=03, sec-latency=0 > I/O behind bridge: 0000f000-00000fff > Memory behind bridge: fff00000-000fffff > Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff > Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- <SERR- <PERR- > BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- > PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- > Capabilities: [44] Express (v1) Downstream Port (Slot-), MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 > <1us > ExtTag- RBE- FLReset- > DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- > MaxPayload 256 bytes, MaxReadReq 128 bytes > DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- > TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 > <512ns, L1 unlimited > ClockPM- Surprise- LLActRep- BwNot- > LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk+ > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- > BWMgmt- ABWMgmt- > Capabilities: [60] MSI: Enable- Count=1/1 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 > Capabilities: [70] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [80] Subsystem: Tyan Computer Device 5372 > Capabilities: [100 v1] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ > MalfTLP+ ECRC- UnsupReq- ACSViol- > CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- > Kernel driver in use: pcieport > > 02:02.0 PCI bridge: Intel Corporation 6311ESB/6321ESB PCI Express Downstream > Port E3 (rev 01) (prog-if 00 [Normal decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Bus: primary=02, secondary=04, subordinate=04, sec-latency=0 > I/O behind bridge: 00002000-00002fff > Memory behind bridge: df200000-df2fffff > Prefetchable memory behind bridge: 00000000d0000000-00000000d00fffff > Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- <SERR- <PERR- > BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- > PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- > Capabilities: [44] Express (v1) Downstream Port (Slot-), MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 > <1us > ExtTag- RBE- FLReset- > DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- > MaxPayload 256 bytes, MaxReadReq 128 bytes > DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- > TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 > unlimited, L1 unlimited > ClockPM- Surprise- LLActRep- BwNot- > LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- > BWMgmt- ABWMgmt- > Capabilities: [60] MSI: Enable- Count=1/1 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 > Capabilities: [70] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [80] Subsystem: Tyan Computer Device 5372 > Capabilities: [100 v1] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ > MalfTLP+ ECRC- UnsupReq- ACSViol- > CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- > Kernel driver in use: pcieport > > 04:00.0 Ethernet controller: Intel Corporation 80003ES2LAN Gigabit Ethernet > Controller (Copper) (rev 01) > Subsystem: Tyan Computer Device 5300 > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx+ > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Interrupt: pin A routed to IRQ 65 > Region 0: Memory at df220000 (32-bit, non-prefetchable) [size=128K] > Region 1: Memory at df200000 (32-bit, non-prefetchable) [size=128K] > Region 2: I/O ports at 2000 [size=32] > [virtual] Expansion ROM at d0000000 [disabled] [size=64K] > Capabilities: [c8] Power Management version 2 > Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- > Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit+ > Address: 00000000fee0100c Data: 4179 > Capabilities: [e0] Express (v1) Endpoint, MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 > <64us > ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- > DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ > RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ > MaxPayload 256 bytes, MaxReadReq 128 bytes > DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ > TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 > <128ns, L1 <64us > ClockPM- Surprise- LLActRep- BwNot- > LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- > BWMgmt- ABWMgmt- > Capabilities: [100 v1] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO+ CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq+ ACSViol- > UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ > MalfTLP+ ECRC- UnsupReq- ACSViol- > CESta: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn- > Capabilities: [140 v1] Device Serial Number 00-e0-81-ff-ff-44-3f-4e > Kernel driver in use: e1000e > Kernel modules: e1000e > > 04:00.1 Ethernet controller: Intel Corporation 80003ES2LAN Gigabit Ethernet > Controller (Copper) (rev 01) > Subsystem: Tyan Computer Device 5300 > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx+ > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Interrupt: pin B routed to IRQ 66 > Region 0: Memory at df260000 (32-bit, non-prefetchable) [size=128K] > Region 1: Memory at df240000 (32-bit, non-prefetchable) [size=128K] > Region 2: I/O ports at 2020 [size=32] > [virtual] Expansion ROM at d0010000 [disabled] [size=64K] > Capabilities: [c8] Power Management version 2 > Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA > PME(D0+,D1-,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- > Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit+ > Address: 00000000fee0200c Data: 4189 > Capabilities: [e0] Express (v1) Endpoint, MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 > <64us > ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- > DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ > RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ > MaxPayload 256 bytes, MaxReadReq 128 bytes > DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ > TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 > <128ns, L1 <64us > ClockPM- Surprise- LLActRep- BwNot- > LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- > BWMgmt- ABWMgmt- > Capabilities: [100 v1] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq+ ACSViol- > UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- > MalfTLP- ECRC- UnsupReq- ACSViol- > UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ > MalfTLP+ ECRC- UnsupReq- ACSViol- > CESta: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn- > Capabilities: [140 v1] Device Serial Number 00-e0-81-ff-ff-44-3f-4e > Kernel driver in use: e1000e > Kernel modules: e1000e > > 08:01.0 VGA compatible controller: XGI Technology Inc. (eXtreme Graphics > Innovation) Z7/Z9 (XG20 core) (prog-if 00 [VGA controller]) > Subsystem: XGI Technology Inc. (eXtreme Graphics Innovation) Z7/Z9 (XG20 > core) > Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > BIST result: 00 > Region 0: Memory at de000000 (32-bit, prefetchable) [size=16M] > Region 1: Memory at df000000 (32-bit, non-prefetchable) [size=256K] > Region 2: I/O ports at 3000 [size=128] > Expansion ROM at <unassigned> [disabled] > Capabilities: [40] Power Management version 2 > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA > PME(D0-,D1-,D2-,D3hot-,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > > 08:02.0 Ethernet controller: Intel Corporation 82557/8/9/0/1 Ethernet Pro > 100 (rev 10) > Subsystem: Intel Corporation EtherExpress PRO/100 S Server Adapter > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 66 (2000ns min, 14000ns max), Cache Line Size: 32 bytes > Interrupt: pin A routed to IRQ 10 > Region 0: Memory at df060000 (32-bit, non-prefetchable) [size=4K] > Region 1: I/O ports at 3080 [size=64] > Region 2: Memory at df040000 (32-bit, non-prefetchable) [size=128K] > Capabilities: [dc] Power Management version 2 > Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA > PME(D0+,D1+,D2+,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME- > > >> Is this an e1000e 4port adapter? > > Dual port. Thanks for your help, Jon > > -- > I have a truly marvellous patch that fixes the bug which this > signature is too narrow to contain. > > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [REGRESSION] e1000e failure triggered by "PCI: Remove MRRS modification from MPS setting code" 2011-09-27 20:11 ` Jon Mason @ 2011-09-29 4:33 ` Benjamin Herrenschmidt 2011-09-29 13:53 ` Jon Mason 0 siblings, 1 reply; 26+ messages in thread From: Benjamin Herrenschmidt @ 2011-09-29 4:33 UTC (permalink / raw) To: Jon Mason Cc: Avi Kivity, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci > Booting with "pci=pcie_bus_perf" should provide you with the same > behavior as before (e.g., with the patch reverted). This should > enable you work around this issue until I can get it resolved. On the > positive side, your system should be 10% faster than it was in 3.0 > (due to the PCI bus payloads being 2x larger). Ugh, that's assuming your fixes for the "perf" mode are in, which I thought wasn't the case yet ... without them, "perf" does very wrong things.. > If you can provide the same output with the patch not reverted, it > would be very beneficial. Based on your description, the lockup only > occurs with traffic. You can gather this before any traffic goes out > (perhaps booting without networking enabled). Right, the output he provided has the MRRS clearly changing in addition to the MPS. Ideally, we'd need the output with current upstream vs. with before your very first patch went in and compare that. Also, Avi, can you send these outputs like patches ? IE without wrapping them ? That would be handy :-) Cheers, Ben. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [REGRESSION] e1000e failure triggered by "PCI: Remove MRRS modification from MPS setting code" 2011-09-29 4:33 ` Benjamin Herrenschmidt @ 2011-09-29 13:53 ` Jon Mason 0 siblings, 0 replies; 26+ messages in thread From: Jon Mason @ 2011-09-29 13:53 UTC (permalink / raw) To: Benjamin Herrenschmidt Cc: Avi Kivity, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci On Wed, Sep 28, 2011 at 11:33 PM, Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote: > >> Booting with "pci=pcie_bus_perf" should provide you with the same >> behavior as before (e.g., with the patch reverted). This should >> enable you work around this issue until I can get it resolved. On the >> positive side, your system should be 10% faster than it was in 3.0 >> (due to the PCI bus payloads being 2x larger). > > Ugh, that's assuming your fixes for the "perf" mode are in, which I > thought wasn't the case yet ... without them, "perf" does very wrong > things.. Yes, but this was "working" before. The patch he wants reverted was the one that makes MPS "Safe" the default. So, changing it to "perf" would give it the same behavior as before. >> If you can provide the same output with the patch not reverted, it >> would be very beneficial. Based on your description, the lockup only >> occurs with traffic. You can gather this before any traffic goes out >> (perhaps booting without networking enabled). > > Right, the output he provided has the MRRS clearly changing in addition > to the MPS. > > Ideally, we'd need the output with current upstream vs. with before your > very first patch went in and compare that. > > Also, Avi, can you send these outputs like patches ? IE without wrapping > them ? That would be handy :-) > > Cheers, > Ben. > > > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Workaround for Intel MPS errata 2011-09-27 18:28 ` Avi Kivity 2011-09-27 20:11 ` Jon Mason @ 2011-09-30 0:16 ` Jon Mason 2011-09-30 2:21 ` Jesse Brandeburg ` (3 more replies) 1 sibling, 4 replies; 26+ messages in thread From: Jon Mason @ 2011-09-30 0:16 UTC (permalink / raw) To: Avi Kivity Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings Hey Avi, Can you try this patch? It should resolve the issue you are seeing. Thanks, Jon PCI: Workaround for Intel MPS errata Intel 5000 and 5100 series memory controllers have a known issue if read completion coalescing is enabled (the default setting) and the PCI-E Maximum Payload Size is set to 256B. To work around this issue, disable read completion coalescing if the MPS is 256B. http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf Reported-by: Avi Kivity <avi@redhat.com> Signed-off-by: Jon Mason <mason@myri.com> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index a919db2..13c733a 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1361,6 +1361,80 @@ static int pcie_find_smpss(struct pci_dev *dev, void *data) return 0; } +static void pcie_errata_check(int mps) +{ + struct pci_dev *dev = NULL; + static bool done = false; + + if (done) + return; + + /* Intel 5000 and 5100 Memory controllers have an errata with read + * completion coalescing (which is enabled by default) and MPS of 256B. + */ + /* 5000X Chipset Memory Controller Hub */ + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25C0, NULL); + if (dev) + goto fixup; + + /* 5000Z Chipset Memory Controller Hub */ + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25D0, NULL); + if (dev) + goto fixup; + + /* 5000V Chipset Memory Controller Hub */ + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25D4, NULL); + if (dev) + goto fixup; + + /* 5000P Chipset Memory Controller Hub */ + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25D8, NULL); + if (dev) + goto fixup; + + /* 5100 Chipset Memory Controller Hub */ + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x65C0, NULL); + if (dev) + goto fixup; + + /* No Intel 5000 or 5100 Memory controller in the system, no need to + * check again + */ + if (!dev) { + done = true; + return; + } + +fixup: + /* Disable read completion coalescing to allow an MPS of 256 */ + if (mps == 256) { + int err; + u16 rcc; + + /* Intel errata specifies bits to change but does not say what + * they are. Keeping them magical until such time as the + * registers and values can be explained. + */ + err = pci_read_config_word(dev, 0x48, &rcc); + if (err) { + dev_err(&dev->dev, "Error attempting to read the read " + "completion coalescing register.\n"); + return; + } + + rcc &= ~(1 << 10); + + err = pci_write_config_word(dev, 0x48, rcc); + if (err) { + dev_err(&dev->dev, "Error attempting to read the read " + "completion coalescing register.\n"); + return; + } + + done = true; + } +} + static void pcie_write_mps(struct pci_dev *dev, int mps) { int rc; @@ -1384,6 +1458,8 @@ static void pcie_write_mps(struct pci_dev *dev, int mps) mps = min(mps, pcie_get_mps(dev->bus->self)); } + pcie_errata_check(mps); + rc = pcie_set_mps(dev, mps); if (rc) dev_err(&dev->dev, "Failed attempting to set the MPS\n"); @@ -1445,7 +1521,7 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data) return 0; } -/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down, +/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, * parents then children fashion. If this changes, then this code will not * work as designed. */ ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-09-30 0:16 ` Workaround for Intel MPS errata Jon Mason @ 2011-09-30 2:21 ` Jesse Brandeburg 2011-09-30 2:51 ` Jon Mason 2011-09-30 5:01 ` Bjorn Helgaas ` (2 subsequent siblings) 3 siblings, 1 reply; 26+ messages in thread From: Jesse Brandeburg @ 2011-09-30 2:21 UTC (permalink / raw) To: Jon Mason Cc: Avi Kivity, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings, Jesse Brandeburg On Thu, Sep 29, 2011 at 5:16 PM, Jon Mason <mason@myri.com> wrote: > Hey Avi, > Can you try this patch? It should resolve the issue you are seeing. > > Thanks, > Jon > > PCI: Workaround for Intel MPS errata > > Intel 5000 and 5100 series memory controllers have a known issue if read > completion coalescing is enabled (the default setting) and the PCI-E > Maximum Payload Size is set to 256B. To work around this issue, disable > read completion coalescing if the MPS is 256B. Hey Jon, glad I could help out by pointing this erratum out on IRC today. The patch looks mostly fine, with one nit, see below. > + /* Disable read completion coalescing to allow an MPS of 256 */ > + if (mps == 256) { > + int err; > + u16 rcc; > + > + /* Intel errata specifies bits to change but does not say what > + * they are. Keeping them magical until such time as the > + * registers and values can be explained. > + */ > + err = pci_read_config_word(dev, 0x48, &rcc); > + if (err) { > + dev_err(&dev->dev, "Error attempting to read the read " > + "completion coalescing register.\n"); > + return; > + } > + > + rcc &= ~(1 << 10); > + > + err = pci_write_config_word(dev, 0x48, rcc); > + if (err) { > + dev_err(&dev->dev, "Error attempting to read the read " this should be "to write the read " > + "completion coalescing register.\n"); > + return; > + } do you have to do anything to change the bit back to 1 if something sets the mps back to 128? ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-09-30 2:21 ` Jesse Brandeburg @ 2011-09-30 2:51 ` Jon Mason 0 siblings, 0 replies; 26+ messages in thread From: Jon Mason @ 2011-09-30 2:51 UTC (permalink / raw) To: Jesse Brandeburg Cc: Avi Kivity, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings, Jesse Brandeburg On Thu, Sep 29, 2011 at 9:21 PM, Jesse Brandeburg <jesse.brandeburg@gmail.com> wrote: > On Thu, Sep 29, 2011 at 5:16 PM, Jon Mason <mason@myri.com> wrote: >> Hey Avi, >> Can you try this patch? It should resolve the issue you are seeing. >> >> Thanks, >> Jon >> >> PCI: Workaround for Intel MPS errata >> >> Intel 5000 and 5100 series memory controllers have a known issue if read >> completion coalescing is enabled (the default setting) and the PCI-E >> Maximum Payload Size is set to 256B. To work around this issue, disable >> read completion coalescing if the MPS is 256B. > > Hey Jon, glad I could help out by pointing this erratum out on IRC > today. The patch looks mostly fine, with one nit, see below. Sorry, I thought I gave you and Ben props in the commit log. That will be corrected in the version I push (assuming it fixes the issue). You really saved my rear :) >> + /* Disable read completion coalescing to allow an MPS of 256 */ >> + if (mps == 256) { >> + int err; >> + u16 rcc; >> + >> + /* Intel errata specifies bits to change but does not say what >> + * they are. Keeping them magical until such time as the >> + * registers and values can be explained. >> + */ >> + err = pci_read_config_word(dev, 0x48, &rcc); >> + if (err) { >> + dev_err(&dev->dev, "Error attempting to read the read " >> + "completion coalescing register.\n"); >> + return; >> + } >> + >> + rcc &= ~(1 << 10); >> + >> + err = pci_write_config_word(dev, 0x48, rcc); >> + if (err) { >> + dev_err(&dev->dev, "Error attempting to read the read " > > this should be "to write the read " Good catch. > >> + "completion coalescing register.\n"); >> + return; >> + } > > do you have to do anything to change the bit back to 1 if something > sets the mps back to 128? The only time this would really be called is at boot time. Its possible that someone could hotplug an adapter with 256, then remove it (and thereby reduce the performance). The problem is that nothing is called to reset the MPS when a device is hotplug removed, and it seems like overkill to add a callback only for this. However, it should be documented in the code that the hole exists. Thanks, Jon > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-09-30 0:16 ` Workaround for Intel MPS errata Jon Mason 2011-09-30 2:21 ` Jesse Brandeburg @ 2011-09-30 5:01 ` Bjorn Helgaas 2011-09-30 15:35 ` Jon Mason 2011-09-30 7:03 ` Rolf Eike Beer 2011-10-02 9:26 ` Avi Kivity 3 siblings, 1 reply; 26+ messages in thread From: Bjorn Helgaas @ 2011-09-30 5:01 UTC (permalink / raw) To: Jon Mason Cc: Avi Kivity, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On Thu, Sep 29, 2011 at 6:16 PM, Jon Mason <mason@myri.com> wrote: > Hey Avi, > Can you try this patch? It should resolve the issue you are seeing. > > Thanks, > Jon > > PCI: Workaround for Intel MPS errata > > Intel 5000 and 5100 series memory controllers have a known issue if read > completion coalescing is enabled (the default setting) and the PCI-E > Maximum Payload Size is set to 256B. To work around this issue, disable > read completion coalescing if the MPS is 256B. I'd much rather see this done as an early quirk so it doesn't clutter probe.c. I don't know how you decide whether - no coalescing with MPS=256, or - coalescing with MPS=128 is better. I suspect that having a quirk that doesn't change the setting, but merely limits MPS to 128 if the BIOS enabled coalescing, would be simplest and would stay in the best-tested chipset configuration. If you do end up changing the coalescing setting, I think you should check the current setting, then log something in dmesg if you change it. If the quirk limits the max MPS, I think dmesg should reflect that, too. I think you're missing a pci_dev_put(). Even if we work out these issues and Avi reports that it fixes his hang, I'm still concerned about MPS configuration being enabled by default in 3.1. It feels like we happened to trip over a few issues and fix them, but I'm worried that with wider testing, we'll find more. I'd feel more comfortable if everything were disabled in 3.1 (it'd be OK to have a command-line flag to enable it), then turned on by default early in the 3.2 merge window. Bjorn > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index a919db2..13c733a 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -1361,6 +1361,80 @@ static int pcie_find_smpss(struct pci_dev *dev, void *data) > return 0; > } > > +static void pcie_errata_check(int mps) > +{ > + struct pci_dev *dev = NULL; > + static bool done = false; > + > + if (done) > + return; > + > + /* Intel 5000 and 5100 Memory controllers have an errata with read > + * completion coalescing (which is enabled by default) and MPS of 256B. > + */ > + /* 5000X Chipset Memory Controller Hub */ > + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25C0, NULL); > + if (dev) > + goto fixup; > + > + /* 5000Z Chipset Memory Controller Hub */ > + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25D0, NULL); > + if (dev) > + goto fixup; > + > + /* 5000V Chipset Memory Controller Hub */ > + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25D4, NULL); > + if (dev) > + goto fixup; > + > + /* 5000P Chipset Memory Controller Hub */ > + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25D8, NULL); > + if (dev) > + goto fixup; > + > + /* 5100 Chipset Memory Controller Hub */ > + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x65C0, NULL); > + if (dev) > + goto fixup; > + > + /* No Intel 5000 or 5100 Memory controller in the system, no need to > + * check again > + */ > + if (!dev) { > + done = true; > + return; > + } > + > +fixup: > + /* Disable read completion coalescing to allow an MPS of 256 */ > + if (mps == 256) { > + int err; > + u16 rcc; > + > + /* Intel errata specifies bits to change but does not say what > + * they are. Keeping them magical until such time as the > + * registers and values can be explained. > + */ > + err = pci_read_config_word(dev, 0x48, &rcc); > + if (err) { > + dev_err(&dev->dev, "Error attempting to read the read " > + "completion coalescing register.\n"); > + return; > + } > + > + rcc &= ~(1 << 10); > + > + err = pci_write_config_word(dev, 0x48, rcc); > + if (err) { > + dev_err(&dev->dev, "Error attempting to read the read " > + "completion coalescing register.\n"); > + return; > + } > + > + done = true; > + } > +} > + > static void pcie_write_mps(struct pci_dev *dev, int mps) > { > int rc; > @@ -1384,6 +1458,8 @@ static void pcie_write_mps(struct pci_dev *dev, int mps) > mps = min(mps, pcie_get_mps(dev->bus->self)); > } > > + pcie_errata_check(mps); > + > rc = pcie_set_mps(dev, mps); > if (rc) > dev_err(&dev->dev, "Failed attempting to set the MPS\n"); > @@ -1445,7 +1521,7 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data) > return 0; > } > > -/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down, > +/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, > * parents then children fashion. If this changes, then this code will not > * work as designed. > */ > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-09-30 5:01 ` Bjorn Helgaas @ 2011-09-30 15:35 ` Jon Mason 2011-09-30 17:17 ` Bjorn Helgaas 0 siblings, 1 reply; 26+ messages in thread From: Jon Mason @ 2011-09-30 15:35 UTC (permalink / raw) To: Bjorn Helgaas Cc: Avi Kivity, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On Fri, Sep 30, 2011 at 12:01 AM, Bjorn Helgaas <bhelgaas@google.com> wrote: > On Thu, Sep 29, 2011 at 6:16 PM, Jon Mason <mason@myri.com> wrote: >> Hey Avi, >> Can you try this patch? It should resolve the issue you are seeing. >> >> Thanks, >> Jon >> >> PCI: Workaround for Intel MPS errata >> >> Intel 5000 and 5100 series memory controllers have a known issue if read >> completion coalescing is enabled (the default setting) and the PCI-E >> Maximum Payload Size is set to 256B. To work around this issue, disable >> read completion coalescing if the MPS is 256B. > > I'd much rather see this done as an early quirk so it doesn't clutter probe.c. > > I don't know how you decide whether > - no coalescing with MPS=256, or > - coalescing with MPS=128 > is better. I suspect that having a quirk that doesn't change the > setting, but merely limits MPS to 128 if the BIOS enabled coalescing, > would be simplest and would stay in the best-tested chipset > configuration. This is what I was debating yesterday. Is it better to disable coalescing and get better throughput (which could be a net negative if the MPS isn't 256) or never allow it to be greater than 128? There is no way of knowing at quirk time if the disable is necessary or not, only when setting the MPS is it known (which is why I did it this way). I could, as you suggest, simply read the bit and see if it is enabled by the BIOS (which I'd bet it is every single time), and then limit the MPS to 128 as a quirk. This would be fairly simple to do. However, the errata from Intel says Windows 2008 always disables the coalescing and sets the MPS to 256B. With this known, Linux's I/O performance would be less than Windows on these systems. While it might not matter to some of us, I imagine the distros will care. I'll defer to your judgement in this matter. > If you do end up changing the coalescing setting, I think you should > check the current setting, then log something in dmesg if you change > it. If the quirk limits the max MPS, I think dmesg should reflect > that, too. Good point, this should be made more obvious to the user. > I think you're missing a pci_dev_put(). Good catch. > Even if we work out these issues and Avi reports that it fixes his > hang, I'm still concerned about MPS configuration being enabled by > default in 3.1. It feels like we happened to trip over a few issues > and fix them, but I'm worried that with wider testing, we'll find > more. > > I'd feel more comfortable if everything were disabled in 3.1 (it'd be > OK to have a command-line flag to enable it), then turned on by > default early in the 3.2 merge window. Okay, I'll create a patch to do this as well. > > Bjorn > >> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c >> index a919db2..13c733a 100644 >> --- a/drivers/pci/probe.c >> +++ b/drivers/pci/probe.c >> @@ -1361,6 +1361,80 @@ static int pcie_find_smpss(struct pci_dev *dev, void *data) >> return 0; >> } >> >> +static void pcie_errata_check(int mps) >> +{ >> + struct pci_dev *dev = NULL; >> + static bool done = false; >> + >> + if (done) >> + return; >> + >> + /* Intel 5000 and 5100 Memory controllers have an errata with read >> + * completion coalescing (which is enabled by default) and MPS of 256B. >> + */ >> + /* 5000X Chipset Memory Controller Hub */ >> + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25C0, NULL); >> + if (dev) >> + goto fixup; >> + >> + /* 5000Z Chipset Memory Controller Hub */ >> + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25D0, NULL); >> + if (dev) >> + goto fixup; >> + >> + /* 5000V Chipset Memory Controller Hub */ >> + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25D4, NULL); >> + if (dev) >> + goto fixup; >> + >> + /* 5000P Chipset Memory Controller Hub */ >> + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x25D8, NULL); >> + if (dev) >> + goto fixup; >> + >> + /* 5100 Chipset Memory Controller Hub */ >> + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x65C0, NULL); >> + if (dev) >> + goto fixup; >> + >> + /* No Intel 5000 or 5100 Memory controller in the system, no need to >> + * check again >> + */ >> + if (!dev) { >> + done = true; >> + return; >> + } >> + >> +fixup: >> + /* Disable read completion coalescing to allow an MPS of 256 */ >> + if (mps == 256) { >> + int err; >> + u16 rcc; >> + >> + /* Intel errata specifies bits to change but does not say what >> + * they are. Keeping them magical until such time as the >> + * registers and values can be explained. >> + */ >> + err = pci_read_config_word(dev, 0x48, &rcc); >> + if (err) { >> + dev_err(&dev->dev, "Error attempting to read the read " >> + "completion coalescing register.\n"); >> + return; >> + } >> + >> + rcc &= ~(1 << 10); >> + >> + err = pci_write_config_word(dev, 0x48, rcc); >> + if (err) { >> + dev_err(&dev->dev, "Error attempting to read the read " >> + "completion coalescing register.\n"); >> + return; >> + } >> + >> + done = true; >> + } >> +} >> + >> static void pcie_write_mps(struct pci_dev *dev, int mps) >> { >> int rc; >> @@ -1384,6 +1458,8 @@ static void pcie_write_mps(struct pci_dev *dev, int mps) >> mps = min(mps, pcie_get_mps(dev->bus->self)); >> } >> >> + pcie_errata_check(mps); >> + >> rc = pcie_set_mps(dev, mps); >> if (rc) >> dev_err(&dev->dev, "Failed attempting to set the MPS\n"); >> @@ -1445,7 +1521,7 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data) >> return 0; >> } >> >> -/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down, >> +/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, >> * parents then children fashion. If this changes, then this code will not >> * work as designed. >> */ >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-pci" in >> the body of a message to majordomo@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html >> > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-09-30 15:35 ` Jon Mason @ 2011-09-30 17:17 ` Bjorn Helgaas 2011-09-30 17:38 ` Jon Mason 0 siblings, 1 reply; 26+ messages in thread From: Bjorn Helgaas @ 2011-09-30 17:17 UTC (permalink / raw) To: Jon Mason Cc: Avi Kivity, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On Fri, Sep 30, 2011 at 9:35 AM, Jon Mason <mason@myri.com> wrote: > > On Fri, Sep 30, 2011 at 12:01 AM, Bjorn Helgaas <bhelgaas@google.com> wrote: > > On Thu, Sep 29, 2011 at 6:16 PM, Jon Mason <mason@myri.com> wrote: > >> Hey Avi, > >> Can you try this patch? It should resolve the issue you are seeing. > >> > >> Thanks, > >> Jon > >> > >> PCI: Workaround for Intel MPS errata > >> > >> Intel 5000 and 5100 series memory controllers have a known issue if read > >> completion coalescing is enabled (the default setting) and the PCI-E > >> Maximum Payload Size is set to 256B. To work around this issue, disable > >> read completion coalescing if the MPS is 256B. > > > > I'd much rather see this done as an early quirk so it doesn't clutter probe.c. > > > > I don't know how you decide whether > > - no coalescing with MPS=256, or > > - coalescing with MPS=128 > > is better. I suspect that having a quirk that doesn't change the > > setting, but merely limits MPS to 128 if the BIOS enabled coalescing, > > would be simplest and would stay in the best-tested chipset > > configuration. > > This is what I was debating yesterday. Is it better to disable > coalescing and get better throughput (which could be a net negative if > the MPS isn't 256) or never allow it to be greater than 128? There is > no way of knowing at quirk time if the disable is necessary or not, > only when setting the MPS is it known (which is why I did it this > way). I could, as you suggest, simply read the bit and see if it is > enabled by the BIOS (which I'd bet it is every single time), and then > limit the MPS to 128 as a quirk. This would be fairly simple to do. > However, the errata from Intel says Windows 2008 always disables the > coalescing and sets the MPS to 256B. With this known, Linux's I/O > performance would be less than Windows on these systems. ... Presumably coalescing improves performance, too, and I don't have the evidence that says "no coalescing with MPS=256" performs better than "coalescing with MPS=128." But the fact that Windows 2008 disables coalescing is worth a lot (if this is in a public erratum, a URL would be good). Given that, I'd probably go with "no coalescing and MPS=256" just as you did. Maybe the quirk could be moved out of the generic code by making pcie_set_mps() a weak function, so x86 could supply a version that disables coalescing if MPS=256? No news from Avi? Were you able to reproduce the problem and verify that the quirk fixes it? I wish the kernel.org bugzilla were back. Since it's not, maybe we should include the LKML URL (https://lkml.org/lkml/2011/9/27/274) in the changelog. Bjorn ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-09-30 17:17 ` Bjorn Helgaas @ 2011-09-30 17:38 ` Jon Mason 2011-09-30 17:57 ` Bjorn Helgaas 0 siblings, 1 reply; 26+ messages in thread From: Jon Mason @ 2011-09-30 17:38 UTC (permalink / raw) To: Bjorn Helgaas Cc: Avi Kivity, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On Fri, Sep 30, 2011 at 12:17 PM, Bjorn Helgaas <bhelgaas@google.com> wrote: > On Fri, Sep 30, 2011 at 9:35 AM, Jon Mason <mason@myri.com> wrote: >> >> On Fri, Sep 30, 2011 at 12:01 AM, Bjorn Helgaas <bhelgaas@google.com> wrote: >> > On Thu, Sep 29, 2011 at 6:16 PM, Jon Mason <mason@myri.com> wrote: >> >> Hey Avi, >> >> Can you try this patch? It should resolve the issue you are seeing. >> >> >> >> Thanks, >> >> Jon >> >> >> >> PCI: Workaround for Intel MPS errata >> >> >> >> Intel 5000 and 5100 series memory controllers have a known issue if read >> >> completion coalescing is enabled (the default setting) and the PCI-E >> >> Maximum Payload Size is set to 256B. To work around this issue, disable >> >> read completion coalescing if the MPS is 256B. >> > >> > I'd much rather see this done as an early quirk so it doesn't clutter probe.c. >> > >> > I don't know how you decide whether >> > - no coalescing with MPS=256, or >> > - coalescing with MPS=128 >> > is better. I suspect that having a quirk that doesn't change the >> > setting, but merely limits MPS to 128 if the BIOS enabled coalescing, >> > would be simplest and would stay in the best-tested chipset >> > configuration. >> >> This is what I was debating yesterday. Is it better to disable >> coalescing and get better throughput (which could be a net negative if >> the MPS isn't 256) or never allow it to be greater than 128? There is >> no way of knowing at quirk time if the disable is necessary or not, >> only when setting the MPS is it known (which is why I did it this >> way). I could, as you suggest, simply read the bit and see if it is >> enabled by the BIOS (which I'd bet it is every single time), and then >> limit the MPS to 128 as a quirk. This would be fairly simple to do. >> However, the errata from Intel says Windows 2008 always disables the >> coalescing and sets the MPS to 256B. With this known, Linux's I/O >> performance would be less than Windows on these systems. ... > > Presumably coalescing improves performance, too, and I don't have the > evidence that says "no coalescing with MPS=256" performs better than > "coalescing with MPS=128." > > But the fact that Windows 2008 disables coalescing is worth a lot (if > this is in a public erratum, a URL would be good). Given that, I'd The URLs were in the top of the patch, but perhaps they weren't obvious. http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf Search for "MPS", as they are several pages into the errata chapter. > probably go with "no coalescing and MPS=256" just as you did. > > Maybe the quirk could be moved out of the generic code by making > pcie_set_mps() a weak function, so x86 could supply a version that > disables coalescing if MPS=256? Not sure what you mean here. Are you saying to make the function defined differently on each arch? > No news from Avi? Were you able to reproduce the problem and verify None so far. I believe he is in .il, so we might not hear back until Sunday. > that the quirk fixes it? I wish the kernel.org bugzilla were back. I just found a system to try it on! It has an Intel Corporation 5000X Chipset Memory Controller Hub, which should have the erratum. > Since it's not, maybe we should include the LKML URL > (https://lkml.org/lkml/2011/9/27/274) in the changelog. Will do. > > Bjorn > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-09-30 17:38 ` Jon Mason @ 2011-09-30 17:57 ` Bjorn Helgaas 0 siblings, 0 replies; 26+ messages in thread From: Bjorn Helgaas @ 2011-09-30 17:57 UTC (permalink / raw) To: Jon Mason Cc: Avi Kivity, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On Fri, Sep 30, 2011 at 11:38 AM, Jon Mason <mason@myri.com> wrote: > > On Fri, Sep 30, 2011 at 12:17 PM, Bjorn Helgaas <bhelgaas@google.com> wrote: > > On Fri, Sep 30, 2011 at 9:35 AM, Jon Mason <mason@myri.com> wrote: > >> > >> On Fri, Sep 30, 2011 at 12:01 AM, Bjorn Helgaas <bhelgaas@google.com> wrote: > >> > On Thu, Sep 29, 2011 at 6:16 PM, Jon Mason <mason@myri.com> wrote: > >> >> Hey Avi, > >> >> Can you try this patch? It should resolve the issue you are seeing. > >> >> > >> >> Thanks, > >> >> Jon > >> >> > >> >> PCI: Workaround for Intel MPS errata > >> >> > >> >> Intel 5000 and 5100 series memory controllers have a known issue if read > >> >> completion coalescing is enabled (the default setting) and the PCI-E > >> >> Maximum Payload Size is set to 256B. To work around this issue, disable > >> >> read completion coalescing if the MPS is 256B. > >> > > >> > I'd much rather see this done as an early quirk so it doesn't clutter probe.c. > >> > > >> > I don't know how you decide whether > >> > - no coalescing with MPS=256, or > >> > - coalescing with MPS=128 > >> > is better. I suspect that having a quirk that doesn't change the > >> > setting, but merely limits MPS to 128 if the BIOS enabled coalescing, > >> > would be simplest and would stay in the best-tested chipset > >> > configuration. > >> > >> This is what I was debating yesterday. Is it better to disable > >> coalescing and get better throughput (which could be a net negative if > >> the MPS isn't 256) or never allow it to be greater than 128? There is > >> no way of knowing at quirk time if the disable is necessary or not, > >> only when setting the MPS is it known (which is why I did it this > >> way). I could, as you suggest, simply read the bit and see if it is > >> enabled by the BIOS (which I'd bet it is every single time), and then > >> limit the MPS to 128 as a quirk. This would be fairly simple to do. > >> However, the errata from Intel says Windows 2008 always disables the > >> coalescing and sets the MPS to 256B. With this known, Linux's I/O > >> performance would be less than Windows on these systems. ... > > > > Presumably coalescing improves performance, too, and I don't have the > > evidence that says "no coalescing with MPS=256" performs better than > > "coalescing with MPS=128." > > > > But the fact that Windows 2008 disables coalescing is worth a lot (if > > this is in a public erratum, a URL would be good). Given that, I'd > > The URLs were in the top of the patch, but perhaps they weren't obvious. ... > Search for "MPS", as they are several pages into the errata chapter. I saw the errata, but searching for "Windows" failed. But now I see the "Microsoft Server 2008" reference in the 5100 errata. The wording is interesting, though... it says: Microsoft Server 2008* forces the maximum payload size to 256 B in the PEXDEVCTRL register; therefore, the workaround with coalescing disabled must be used for Microsoft Server 2008*. I would read that as saying "Windows Server 2008 always sets MPS to 256 but doesn't do anything with the coalescing setting. Therefore, if you want to run Server 2008 on your system, make sure the BIOS leaves coalescing disabled." > > Maybe the quirk could be moved out of the generic code by making > > pcie_set_mps() a weak function, so x86 could supply a version that > > disables coalescing if MPS=256? > > Not sure what you mean here. Are you saying to make the function > defined differently on each arch? You can define the generic pcie_set_mps() with the __weak attribute in drivers/pci/probe.c. Then if you put a normal (non-weak) pcie_set_mps() definition in the arch code, it will be used instead of the weak definition. If the arch doesn't supply a definition, the generic weak version will be used. Bjorn ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-09-30 0:16 ` Workaround for Intel MPS errata Jon Mason 2011-09-30 2:21 ` Jesse Brandeburg 2011-09-30 5:01 ` Bjorn Helgaas @ 2011-09-30 7:03 ` Rolf Eike Beer 2011-09-30 15:39 ` Jon Mason 2011-10-02 9:26 ` Avi Kivity 3 siblings, 1 reply; 26+ messages in thread From: Rolf Eike Beer @ 2011-09-30 7:03 UTC (permalink / raw) To: Jon Mason Cc: Avi Kivity, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings > Hey Avi, > Can you try this patch? It should resolve the issue you are seeing. > > Thanks, > Jon > > PCI: Workaround for Intel MPS errata > > Intel 5000 and 5100 series memory controllers have a known issue if > read > completion coalescing is enabled (the default setting) and the PCI-E > Maximum Payload Size is set to 256B. To work around this issue, > disable > read completion coalescing if the MPS is 256B. > > http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf > http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf > > Reported-by: Avi Kivity <avi@redhat.com> > Signed-off-by: Jon Mason <mason@myri.com> > > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index a919db2..13c733a 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -1361,6 +1361,80 @@ static int pcie_find_smpss(struct pci_dev *dev, > void *data) > return 0; > } > > +static void pcie_errata_check(int mps) > +{ While this whole function is about Intel 5x00 devices the name of it is very generic (and in a very generic file). Maybe this can be changed, e.g. "fixup:" renamed to "fixup_intel_5x00:". Also I wonder if that shouldn't be a nop when CONFIG_PCI_QUIRKS is not set. Eike ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-09-30 7:03 ` Rolf Eike Beer @ 2011-09-30 15:39 ` Jon Mason 0 siblings, 0 replies; 26+ messages in thread From: Jon Mason @ 2011-09-30 15:39 UTC (permalink / raw) To: Rolf Eike Beer Cc: Avi Kivity, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On Fri, Sep 30, 2011 at 2:03 AM, Rolf Eike Beer <eike-kernel@sf-tec.de> wrote: >> Hey Avi, >> Can you try this patch? It should resolve the issue you are seeing. >> >> Thanks, >> Jon >> >> PCI: Workaround for Intel MPS errata >> >> Intel 5000 and 5100 series memory controllers have a known issue if >> read >> completion coalescing is enabled (the default setting) and the PCI-E >> Maximum Payload Size is set to 256B. To work around this issue, >> disable >> read completion coalescing if the MPS is 256B. >> >> http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf >> http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf >> >> Reported-by: Avi Kivity <avi@redhat.com> >> Signed-off-by: Jon Mason <mason@myri.com> >> >> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c >> index a919db2..13c733a 100644 >> --- a/drivers/pci/probe.c >> +++ b/drivers/pci/probe.c >> @@ -1361,6 +1361,80 @@ static int pcie_find_smpss(struct pci_dev *dev, >> void *data) >> return 0; >> } >> >> +static void pcie_errata_check(int mps) >> +{ > > While this whole function is about Intel 5x00 devices the name of it is > very generic (and in a very generic file). Maybe this can be changed, e.g. I made it generic in naming because I'm betting there are other chips out there that don't play nice with others. > "fixup:" renamed to "fixup_intel_5x00:". Also I wonder if that shouldn't > be a nop when CONFIG_PCI_QUIRKS is not set. It probably should be a no-op for non-x86 too, as I doubt many other arches use Intel memory controllers (maybe IA64). Thanks, Jon > > Eike > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-09-30 0:16 ` Workaround for Intel MPS errata Jon Mason ` (2 preceding siblings ...) 2011-09-30 7:03 ` Rolf Eike Beer @ 2011-10-02 9:26 ` Avi Kivity 2011-10-03 4:58 ` Jon Mason 3 siblings, 1 reply; 26+ messages in thread From: Avi Kivity @ 2011-10-02 9:26 UTC (permalink / raw) To: Jon Mason Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On 09/30/2011 03:16 AM, Jon Mason wrote: > Hey Avi, > Can you try this patch? It should resolve the issue you are seeing. It doesn't; the fixup: label is not reached (though I do have an 0x25d4 device). -- error compiling committee.c: too many arguments to function ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-10-02 9:26 ` Avi Kivity @ 2011-10-03 4:58 ` Jon Mason 2011-10-03 10:11 ` Avi Kivity 0 siblings, 1 reply; 26+ messages in thread From: Jon Mason @ 2011-10-03 4:58 UTC (permalink / raw) To: Avi Kivity Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On Sun, Oct 02, 2011 at 11:26:12AM +0200, Avi Kivity wrote: > On 09/30/2011 03:16 AM, Jon Mason wrote: > >Hey Avi, > >Can you try this patch? It should resolve the issue you are seeing. > > It doesn't; the fixup: label is not reached (though I do have an > 0x25d4 device). > > -- > error compiling committee.c: too many arguments to function > I found a system with a 5000X Memory controller (which should have the same errata). It doesn't have the faulty bit (perhaps better BIOS). I was able to findout why the code in the previous patch wasn't working, but wasn't able to cause the crash by setting the bit from the errata. The reworked version of the previous patch found below should resolve the issue. Please test it if you can. Thanks, Jon --- PCI: Workaround for Intel MPS errata Intel 5000 and 5100 series memory controllers have a known issue if read completion coalescing is enabled (the default setting) and the PCI-E Maximum Payload Size is set to 256B. To work around this issue, disable read completion coalescing if the MPS is 256B. It is worth noting that there is no function to undo the disable of read completion coalescing, and the performance benefit of read completion coalescing will be lost if the MPS is set from 256B to 128B. It is only possible to have this issue via hotplug removing the only 256B MPS device in the system (thus making all of the other devices in the system have a performance degradation without the benefit of any 256B transfers). Therefore, this trade off is acceptable. http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf Thanks to Jesse Brandeburg and Ben Hutchings for providing insight into the problem. Reported-by: Avi Kivity <avi@redhat.com> Signed-off-by: Jon Mason <mason@myri.com> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index a919db2..8f6725f 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1361,6 +1361,90 @@ static int pcie_find_smpss(struct pci_dev *dev, void *data) return 0; } +static void pcie_errata_check(int mps) +{ + static bool done = false; + struct pci_bus *bus; + u16 val; + + if (done) + return; + + /* pci_get_device cannot be used for these, as there are no pci_dev's + * created for the memory controllers. We'll have to get nasty here and + * check PCI config space ourselves. + */ + bus = pci_find_bus(0, 0); + if (!bus) + return; + + /* Intel 5000 and 5100 Memory controllers have an errata with read + * completion coalescing (which is enabled by default) and MPS of 256B. + */ + pci_bus_read_config_word(bus, 0, PCI_VENDOR_ID, &val); + if (val != PCI_VENDOR_ID_INTEL) { + done = true; + return; + } + + pci_bus_read_config_word(bus, 0, PCI_DEVICE_ID, &val); + switch (val) { + case 0x25C0: /* 5000X Chipset Memory Controller Hub */ + case 0x25D0: /* 5000Z Chipset Memory Controller Hub */ + case 0x25D4: /* 5000V Chipset Memory Controller Hub */ + case 0x25D8: /* 5000P Chipset Memory Controller Hub */ + case 0x65C0: /* 5100 Chipset Memory Controller Hub */ + break; + default: + done = true; + return; + } + + /* Disable read completion coalescing to allow an MPS of 256. + * + * It is worth noting that there is no function to undo the disable of + * read completion coalescing, and the performance benefit of read + * completion coalescing will be lost if the MPS is set from 256B to + * 128B. It is only possible to have this issue via hotplug removing + * the only 256B MPS device in the system (thus making all of the other + * devices in the system have a performance degradation without the + * benefit of any 256B transfers). Therefore, this trade off is + * acceptable. + */ + if (mps == 256) { + int err; + + /* Intel errata specifies bits to change but does not say what + * they are. Keeping them magical until such time as the + * registers and values can be explained. + */ + err = pci_bus_read_config_word(bus, 0, 0x48, &val); + if (err) { + dev_err(&bus->dev, "Error attempting to read the read " + "completion coalescing register.\n"); + return; + } + + if (!(val & (1 << 10))) { + done = true; + return; + } + + val |= (1 << 10); + err = pci_bus_write_config_word(bus, 0, 0x48, val); + if (err) { + dev_err(&bus->dev, "Error attempting to write the read " + "completion coalescing register.\n"); + return; + } + + dev_info(&bus->dev, "Read completion coalescing disabled due " + "to hardware errata relating to 256B MPS.\n"); + + done = true; + } +} + static void pcie_write_mps(struct pci_dev *dev, int mps) { int rc; @@ -1384,6 +1468,8 @@ static void pcie_write_mps(struct pci_dev *dev, int mps) mps = min(mps, pcie_get_mps(dev->bus->self)); } + pcie_errata_check(mps); + rc = pcie_set_mps(dev, mps); if (rc) dev_err(&dev->dev, "Failed attempting to set the MPS\n"); @@ -1433,19 +1519,19 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data) if (!pci_is_pcie(dev)) return 0; - dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", + dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); pcie_write_mps(dev, mps); pcie_write_mrrs(dev); - dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", + dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); return 0; } -/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down, +/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, * parents then children fashion. If this changes, then this code will not * work as designed. */ ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-10-03 4:58 ` Jon Mason @ 2011-10-03 10:11 ` Avi Kivity 2011-10-03 15:12 ` Jon Mason 0 siblings, 1 reply; 26+ messages in thread From: Avi Kivity @ 2011-10-03 10:11 UTC (permalink / raw) To: Jon Mason Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On 10/03/2011 06:58 AM, Jon Mason wrote: > On Sun, Oct 02, 2011 at 11:26:12AM +0200, Avi Kivity wrote: > > On 09/30/2011 03:16 AM, Jon Mason wrote: > > >Hey Avi, > > >Can you try this patch? It should resolve the issue you are seeing. > > > > It doesn't; the fixup: label is not reached (though I do have an > > 0x25d4 device). > > > > -- > > error compiling committee.c: too many arguments to function > > > > I found a system with a 5000X Memory controller (which should have the > same errata). It doesn't have the faulty bit (perhaps better BIOS). I > was able to findout why the code in the previous patch wasn't working, > but wasn't able to cause the crash by setting the bit from the errata. > The reworked version of the previous patch found below should resolve > the issue. Please test it if you can. Will be happy to test, but patch appears to be against a different tree? $ git apply -C2 .git/rebase-apply/patch .git/rebase-apply/patch:75: trailing whitespace, shock horror. * Context reduced to (2/2) to apply fragment at 1362 Context reduced to (2/2) to apply fragment at 1475 error: patch failed: drivers/pci/probe.c:1433 error: drivers/pci/probe.c: patch does not apply -- error compiling committee.c: too many arguments to function ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-10-03 10:11 ` Avi Kivity @ 2011-10-03 15:12 ` Jon Mason 2011-10-04 9:46 ` Avi Kivity 0 siblings, 1 reply; 26+ messages in thread From: Jon Mason @ 2011-10-03 15:12 UTC (permalink / raw) To: Avi Kivity Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On Mon, Oct 03, 2011 at 12:11:53PM +0200, Avi Kivity wrote: > On 10/03/2011 06:58 AM, Jon Mason wrote: > >On Sun, Oct 02, 2011 at 11:26:12AM +0200, Avi Kivity wrote: > >> On 09/30/2011 03:16 AM, Jon Mason wrote: > >> >Hey Avi, > >> >Can you try this patch? It should resolve the issue you are seeing. > >> > >> It doesn't; the fixup: label is not reached (though I do have an > >> 0x25d4 device). > >> > >> -- > error compiling committee.c: too many arguments to > >function > >> > > > >I found a system with a 5000X Memory controller (which should have the > >same errata). It doesn't have the faulty bit (perhaps better BIOS). I > >was able to findout why the code in the previous patch wasn't working, > >but wasn't able to cause the crash by setting the bit from the errata. > >The reworked version of the previous patch found below should resolve > >the issue. Please test it if you can. > > Will be happy to test, but patch appears to be against a different tree? > > $ git apply -C2 .git/rebase-apply/patch > .git/rebase-apply/patch:75: trailing whitespace, shock horror. > * > Context reduced to (2/2) to apply fragment at 1362 > Context reduced to (2/2) to apply fragment at 1475 > error: patch failed: drivers/pci/probe.c:1433 > error: drivers/pci/probe.c: patch does not apply Sorry, I had the patch on top of the 3 patches I just sent to Linus. I've rebased it and inserted it below. Thanks, Jon PCI: Workaround for Intel MPS errata Intel 5000 and 5100 series memory controllers have a known issue if read completion coalescing is enabled (the default setting) and the PCI-E Maximum Payload Size is set to 256B. To work around this issue, disable read completion coalescing if the MPS is 256B. It is worth noting that there is no function to undo the disable of read completion coalescing, and the performance benefit of read completion coalescing will be lost if the MPS is set from 256B to 128B. It is only possible to have this issue via hotplug removing the only 256B MPS device in the system (thus making all of the other devices in the system have a performance degradation without the benefit of any 256B transfers). Therefore, this trade off is acceptable. http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf Thanks to Jesse Brandeburg and Ben Hutchings for providing insight into the problem. Reported-by: Avi Kivity <avi@redhat.com> Signed-off-by: Jon Mason <mason@myri.com> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index f3f94a5..1dd11a5 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1361,6 +1361,90 @@ static int pcie_find_smpss(struct pci_dev *dev, void *data) return 0; } +static void pcie_errata_check(int mps) +{ + static bool done = false; + struct pci_bus *bus; + u16 val; + + if (done) + return; + + /* pci_get_device cannot be used for these, as there are no pci_dev's + * created for the memory controllers. We'll have to get nasty here and + * check PCI config space ourselves. + */ + bus = pci_find_bus(0, 0); + if (!bus) + return; + + /* Intel 5000 and 5100 Memory controllers have an errata with read + * completion coalescing (which is enabled by default) and MPS of 256B. + */ + pci_bus_read_config_word(bus, 0, PCI_VENDOR_ID, &val); + if (val != PCI_VENDOR_ID_INTEL) { + done = true; + return; + } + + pci_bus_read_config_word(bus, 0, PCI_DEVICE_ID, &val); + switch (val) { + case 0x25C0: /* 5000X Chipset Memory Controller Hub */ + case 0x25D0: /* 5000Z Chipset Memory Controller Hub */ + case 0x25D4: /* 5000V Chipset Memory Controller Hub */ + case 0x25D8: /* 5000P Chipset Memory Controller Hub */ + case 0x65C0: /* 5100 Chipset Memory Controller Hub */ + break; + default: + done = true; + return; + } + + /* Disable read completion coalescing to allow an MPS of 256. + * + * It is worth noting that there is no function to undo the disable of + * read completion coalescing, and the performance benefit of read + * completion coalescing will be lost if the MPS is set from 256B to + * 128B. It is only possible to have this issue via hotplug removing + * the only 256B MPS device in the system (thus making all of the other + * devices in the system have a performance degradation without the + * benefit of any 256B transfers). Therefore, this trade off is + * acceptable. + */ + if (mps == 256) { + int err; + + /* Intel errata specifies bits to change but does not say what + * they are. Keeping them magical until such time as the + * registers and values can be explained. + */ + err = pci_bus_read_config_word(bus, 0, 0x48, &val); + if (err) { + dev_err(&bus->dev, "Error attempting to read the read " + "completion coalescing register.\n"); + return; + } + + if (!(val & (1 << 10))) { + done = true; + return; + } + + val |= (1 << 10); + err = pci_bus_write_config_word(bus, 0, 0x48, val); + if (err) { + dev_err(&bus->dev, "Error attempting to write the read " + "completion coalescing register.\n"); + return; + } + + dev_info(&bus->dev, "Read completion coalescing disabled due " + "to hardware errata relating to 256B MPS.\n"); + + done = true; + } +} + static void pcie_write_mps(struct pci_dev *dev, int mps) { int rc, dev_mpss; @@ -1390,6 +1474,8 @@ static void pcie_write_mps(struct pci_dev *dev, int mps) dev->pcie_mpss = ffs(mps) - 8; } + pcie_errata_check(mps); + rc = pcie_set_mps(dev, mps); if (rc) dev_err(&dev->dev, "Failed attempting to set the MPS\n"); @@ -1452,7 +1538,7 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data) return 0; } -/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down, +/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, * parents then children fashion. If this changes, then this code will not * work as designed. */ ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-10-03 15:12 ` Jon Mason @ 2011-10-04 9:46 ` Avi Kivity 2011-10-04 13:06 ` Avi Kivity 0 siblings, 1 reply; 26+ messages in thread From: Avi Kivity @ 2011-10-04 9:46 UTC (permalink / raw) To: Jon Mason Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On 10/03/2011 05:12 PM, Jon Mason wrote: > PCI: Workaround for Intel MPS errata > > Intel 5000 and 5100 series memory controllers have a known issue if read > completion coalescing is enabled (the default setting) and the PCI-E > Maximum Payload Size is set to 256B. To work around this issue, disable > read completion coalescing if the MPS is 256B. > > It is worth noting that there is no function to undo the disable of read > completion coalescing, and the performance benefit of read completion > coalescing will be lost if the MPS is set from 256B to 128B. It is only > possible to have this issue via hotplug removing the only 256B MPS > device in the system (thus making all of the other devices in the system > have a performance degradation without the benefit of any 256B > transfers). Therefore, this trade off is acceptable. > > http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf > http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf > > Thanks to Jesse Brandeburg and Ben Hutchings for providing insight into > the problem. > > Reported-by: Avi Kivity<avi@redhat.com> > Signed-off-by: Jon Mason<mason@myri.com> > > + > + if (!(val& (1<< 10))) { > + done = true; > + return; > + } Here, you bail out if bit 10 is clear. So if we're here, it's set. > + > + val |= (1<< 10); Now it's even more set? > + err = pci_bus_write_config_word(bus, 0, 0x48, val); > + if (err) { > + dev_err(&bus->dev, "Error attempting to write the read " > + "completion coalescing register.\n"); > + return; > + } > + > + dev_info(&bus->dev, "Read completion coalescing disabled due " > + "to hardware errata relating to 256B MPS.\n"); > + > + done = true; > + } > +} > + > -- error compiling committee.c: too many arguments to function ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-10-04 9:46 ` Avi Kivity @ 2011-10-04 13:06 ` Avi Kivity 2011-10-04 13:11 ` Jon Mason ` (2 more replies) 0 siblings, 3 replies; 26+ messages in thread From: Avi Kivity @ 2011-10-04 13:06 UTC (permalink / raw) To: Jon Mason Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On 10/04/2011 11:46 AM, Avi Kivity wrote: > On 10/03/2011 05:12 PM, Jon Mason wrote: >> PCI: Workaround for Intel MPS errata >> >> Intel 5000 and 5100 series memory controllers have a known issue >> if read >> completion coalescing is enabled (the default setting) and the >> PCI-E >> Maximum Payload Size is set to 256B. To work around this issue, >> disable >> read completion coalescing if the MPS is 256B. >> >> It is worth noting that there is no function to undo the disable >> of read >> completion coalescing, and the performance benefit of read >> completion >> coalescing will be lost if the MPS is set from 256B to 128B. It >> is only >> possible to have this issue via hotplug removing the only 256B MPS >> device in the system (thus making all of the other devices in >> the system >> have a performance degradation without the benefit of any 256B >> transfers). Therefore, this trade off is acceptable. >> >> >> http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf >> >> http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf >> >> Thanks to Jesse Brandeburg and Ben Hutchings for providing >> insight into >> the problem. >> >> Reported-by: Avi Kivity<avi@redhat.com> >> Signed-off-by: Jon Mason<mason@myri.com> >> >> + >> + if (!(val& (1<< 10))) { >> + done = true; >> + return; >> + } > > Here, you bail out if bit 10 is clear. So if we're here, it's set. > >> + >> + val |= (1<< 10); > > Now it's even more set? > Even with this line changed to clear bit 10, I still get a hard lockup. Do we need to clear this bit on the other 5000 devices? I notice they have similar values in word 0x48, with bits 10 set in them. What does "Device 7-2,0" refer to in the workaround description? Seems to me we need to apply the workaround to the PCIe ports as well. -- error compiling committee.c: too many arguments to function ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-10-04 13:06 ` Avi Kivity @ 2011-10-04 13:11 ` Jon Mason 2011-10-04 20:12 ` Jon Mason 2011-10-05 3:46 ` Jon Mason 2 siblings, 0 replies; 26+ messages in thread From: Jon Mason @ 2011-10-04 13:11 UTC (permalink / raw) To: Avi Kivity Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On Tue, Oct 4, 2011 at 8:06 AM, Avi Kivity <avi@redhat.com> wrote: > On 10/04/2011 11:46 AM, Avi Kivity wrote: >> >> On 10/03/2011 05:12 PM, Jon Mason wrote: >>> >>> PCI: Workaround for Intel MPS errata >>> >>> Intel 5000 and 5100 series memory controllers have a known issue if >>> read >>> completion coalescing is enabled (the default setting) and the PCI-E >>> Maximum Payload Size is set to 256B. To work around this issue, >>> disable >>> read completion coalescing if the MPS is 256B. >>> >>> It is worth noting that there is no function to undo the disable of >>> read >>> completion coalescing, and the performance benefit of read completion >>> coalescing will be lost if the MPS is set from 256B to 128B. It is >>> only >>> possible to have this issue via hotplug removing the only 256B MPS >>> device in the system (thus making all of the other devices in the >>> system >>> have a performance degradation without the benefit of any 256B >>> transfers). Therefore, this trade off is acceptable. >>> >>> >>> http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf >>> >>> http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf >>> >>> Thanks to Jesse Brandeburg and Ben Hutchings for providing insight >>> into >>> the problem. >>> >>> Reported-by: Avi Kivity<avi@redhat.com> >>> Signed-off-by: Jon Mason<mason@myri.com> >>> >>> + >>> + if (!(val& (1<< 10))) { >>> + done = true; >>> + return; >>> + } >> >> Here, you bail out if bit 10 is clear. So if we're here, it's set. >> >>> + >>> + val |= (1<< 10); >> >> Now it's even more set? >> > > Even with this line changed to clear bit 10, I still get a hard lockup. Do That stinks, thanks for finding that issue and fixing it. > we need to clear this bit on the other 5000 devices? I notice they have > similar values in word 0x48, with bits 10 set in them. > > What does "Device 7-2,0" refer to in the workaround description? Seems to > me we need to apply the workaround to the PCIe ports as well. I have no idea what that means, but it would make sense. I'll modify the patch to do this as well. Thanks for being so much help :) > > -- > error compiling committee.c: too many arguments to function > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-10-04 13:06 ` Avi Kivity 2011-10-04 13:11 ` Jon Mason @ 2011-10-04 20:12 ` Jon Mason 2011-10-05 3:46 ` Jon Mason 2 siblings, 0 replies; 26+ messages in thread From: Jon Mason @ 2011-10-04 20:12 UTC (permalink / raw) To: Avi Kivity Cc: Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On Tue, Oct 4, 2011 at 8:06 AM, Avi Kivity <avi@redhat.com> wrote: > On 10/04/2011 11:46 AM, Avi Kivity wrote: >> >> On 10/03/2011 05:12 PM, Jon Mason wrote: >>> >>> PCI: Workaround for Intel MPS errata >>> >>> Intel 5000 and 5100 series memory controllers have a known issue if >>> read >>> completion coalescing is enabled (the default setting) and the PCI-E >>> Maximum Payload Size is set to 256B. To work around this issue, >>> disable >>> read completion coalescing if the MPS is 256B. >>> >>> It is worth noting that there is no function to undo the disable of >>> read >>> completion coalescing, and the performance benefit of read completion >>> coalescing will be lost if the MPS is set from 256B to 128B. It is >>> only >>> possible to have this issue via hotplug removing the only 256B MPS >>> device in the system (thus making all of the other devices in the >>> system >>> have a performance degradation without the benefit of any 256B >>> transfers). Therefore, this trade off is acceptable. >>> >>> >>> http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf >>> >>> http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf >>> >>> Thanks to Jesse Brandeburg and Ben Hutchings for providing insight >>> into >>> the problem. >>> >>> Reported-by: Avi Kivity<avi@redhat.com> >>> Signed-off-by: Jon Mason<mason@myri.com> >>> >>> + >>> + if (!(val& (1<< 10))) { >>> + done = true; >>> + return; >>> + } >> >> Here, you bail out if bit 10 is clear. So if we're here, it's set. >> >>> + >>> + val |= (1<< 10); >> >> Now it's even more set? >> > > Even with this line changed to clear bit 10, I still get a hard lockup. Do > we need to clear this bit on the other 5000 devices? I notice they have > similar values in word 0x48, with bits 10 set in them. > > What does "Device 7-2,0" refer to in the workaround description? Seems to > me we need to apply the workaround to the PCIe ports as well. I believe you are correct. On my system (which I still can't get to fail by enabling the RCC bit), I have 00:00.0 Host bridge: Intel Corporation 5000X Chipset Memory Controller Hub (rev 12) 00:02.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x4 Port 2 (rev 12) 00:03.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x4 Port 3 (rev 12) 00:04.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x8 Port 4-5 (rev 12) 00:05.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x4 Port 5 (rev 12) 00:06.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x8 Port 6-7 (rev 12) 00:07.0 PCI bridge: Intel Corporation 5000 Series Chipset PCI Express x4 Port 7 (rev 12) Those PCI devices numbers match perfectly to the ones from the erratum. Patch to disable the bit on those devices coming shortly. Thanks, Jon > > -- > error compiling committee.c: too many arguments to function > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-10-04 13:06 ` Avi Kivity 2011-10-04 13:11 ` Jon Mason 2011-10-04 20:12 ` Jon Mason @ 2011-10-05 3:46 ` Jon Mason 2011-10-05 12:09 ` Avi Kivity 2 siblings, 1 reply; 26+ messages in thread From: Jon Mason @ 2011-10-05 3:46 UTC (permalink / raw) To: Avi Kivity Cc: Jon Mason, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings Hey Avi, I believe this will fix the issue (assuming the errata is the issue in the first place). You'll need to apply the patch on top of Linus' latest code and re-enable the MPS tuning (as it is now off by default). This can be done by adding "pci=pcie_bus_safe" to your boot args. After thinking about it some more, a PCI quark is the correct way of doing things. We must always disable read completion coalescing due to the possibility of hotplugging a device with a MPS of 256B. Also, I believe everyone will think this is much cleaner. Let me know how it goes and thanks again for testing this for me. Thanks, Jon commit ada901c643c7d0978a762fbadc2a6526e4ddf860 Author: Jon Mason <mason@myri.com> Date: Thu Sep 29 16:56:37 2011 -0500 PCI: Workaround for Intel MPS errata Intel 5000 and 5100 series memory controllers have a known issue if read completion coalescing is enabled and the PCI-E Maximum Payload Size is set to 256B. To work around this issue, disable read completion coalescing in the memory controller and root complexes. Unfortunately, it must always be disabled, even if no 256B MPS devices are precent, due to the possiblity of one being hotplugged. Links to erratas: http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf Thanks to Jesse Brandeburg and Ben Hutchings for providing insight into the problem. Tested-and-Reported-by: Avi Kivity <avi@redhat.com> Signed-off-by: Jon Mason <mason@myri.com> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 6ab6bd3..c223d95 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1452,7 +1452,7 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data) return 0; } -/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down, +/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, * parents then children fashion. If this changes, then this code will not * work as designed. */ diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 1196f61..70da3f5 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2822,6 +2822,75 @@ static void __devinit fixup_ti816x_class(struct pci_dev* dev) } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class); +/* Intel 5000 and 5100 Memory controllers have an errata with read completion + * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. + * Since there is no way of knowing what the PCIE MPS on each fabric will be + * until all of the devices are discovered and buses walked, read completion + * coalescing must be disabled. Unfortunately, it cannot be re-enabled because + * it is possible to hotplug a device with MPS of 256B. + */ +static void __devinit quirk_intel_mc_errata(struct pci_dev *dev) +{ + int err; + u16 rcc; + + if (pcie_bus_config == PCIE_BUS_TUNE_OFF) + return; + + /* Intel errata specifies bits to change but does not say what they are. + * Keeping them magical until such time as the registers and values can + * be explained. + */ + err = pci_read_config_word(dev, 0x48, &rcc); + if (err) { + dev_err(&dev->dev, "Error attempting to read the read " + "completion coalescing register.\n"); + return; + } + + if (!(rcc & (1 << 10))) + return; + + rcc &= ~(1 << 10); + + err = pci_write_config_word(dev, 0x48, rcc); + if (err) { + dev_err(&dev->dev, "Error attempting to write the read " + "completion coalescing register.\n"); + return; + } + + pr_info_once("Read completion coalescing disabled due to hardware " + "errata relating to 256B MPS.\n"); +} +/* Intel 5000 series memory controllers and ports 2-7 */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); +/* Intel 5100 series memory controllers and ports 2-7 */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); + static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) { ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: Workaround for Intel MPS errata 2011-10-05 3:46 ` Jon Mason @ 2011-10-05 12:09 ` Avi Kivity 0 siblings, 0 replies; 26+ messages in thread From: Avi Kivity @ 2011-10-05 12:09 UTC (permalink / raw) To: Jon Mason Cc: Jon Mason, Sven Schnelle, Simon Kirby, Eric Dumazet, Niels Ole Salscheider, Jesse Barnes, Linus Torvalds, linux-kernel, linux-pci, Ben Hutchings On 10/05/2011 05:46 AM, Jon Mason wrote: > Hey Avi, > I believe this will fix the issue (assuming the errata is the issue in > the first place). You'll need to apply the patch on top of Linus' > latest code and re-enable the MPS tuning (as it is now off by > default). This can be done by adding "pci=pcie_bus_safe" to your boot > args. > > After thinking about it some more, a PCI quark is the correct way of > doing things. We must always disable read completion coalescing due > to the possibility of hotplugging a device with a MPS of 256B. Also, > I believe everyone will think this is much cleaner. Agree. > Let me know how it goes and thanks again for testing this for me. Works perfectly now. Thanks. -- error compiling committee.c: too many arguments to function ^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2011-10-05 12:10 UTC | newest] Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2011-09-27 17:01 [REGRESSION] e1000e failure triggered by "PCI: Remove MRRS modification from MPS setting code" Avi Kivity 2011-09-27 17:59 ` Jon Mason 2011-09-27 18:28 ` Avi Kivity 2011-09-27 20:11 ` Jon Mason 2011-09-29 4:33 ` Benjamin Herrenschmidt 2011-09-29 13:53 ` Jon Mason 2011-09-30 0:16 ` Workaround for Intel MPS errata Jon Mason 2011-09-30 2:21 ` Jesse Brandeburg 2011-09-30 2:51 ` Jon Mason 2011-09-30 5:01 ` Bjorn Helgaas 2011-09-30 15:35 ` Jon Mason 2011-09-30 17:17 ` Bjorn Helgaas 2011-09-30 17:38 ` Jon Mason 2011-09-30 17:57 ` Bjorn Helgaas 2011-09-30 7:03 ` Rolf Eike Beer 2011-09-30 15:39 ` Jon Mason 2011-10-02 9:26 ` Avi Kivity 2011-10-03 4:58 ` Jon Mason 2011-10-03 10:11 ` Avi Kivity 2011-10-03 15:12 ` Jon Mason 2011-10-04 9:46 ` Avi Kivity 2011-10-04 13:06 ` Avi Kivity 2011-10-04 13:11 ` Jon Mason 2011-10-04 20:12 ` Jon Mason 2011-10-05 3:46 ` Jon Mason 2011-10-05 12:09 ` Avi Kivity
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