* [PATCH 0/2] riscv: improve unaligned memory accesses
@ 2021-09-13 12:19 ` Chen Huang
0 siblings, 0 replies; 10+ messages in thread
From: Chen Huang @ 2021-09-13 12:19 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Chen Huang, Kefeng Wang, linux-riscv, linux-kernel
The RISCV ISA can support unaligned memory accesses, so the patchset
selects HAVE_EFFICIENT_UNALIGNED_ACCESS and supports DCACHE_WORD_ACCESS
to improve the efficiency of unaligned memory accesses.
Chen Huang (2):
riscv: Kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS
riscv: Support DCACHE_WORD_ACCESS
arch/riscv/Kconfig | 2 ++
arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++
2 files changed, 38 insertions(+)
--
2.18.0.huawei.25
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* [PATCH 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
2021-09-13 12:19 ` Chen Huang
@ 2021-09-13 12:19 ` Chen Huang
-1 siblings, 0 replies; 10+ messages in thread
From: Chen Huang @ 2021-09-13 12:19 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Chen Huang, Kefeng Wang, linux-riscv, linux-kernel
The RISCV ISA can perform efficient unaligned memory accesses
in hardware. This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS
for that.
Signed-off-by: Chen Huang <chenhuang5@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aac669a6c3d8..6e70bf50b02a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -81,6 +81,7 @@ config RISCV
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_CONTIGUOUS if MMU
select HAVE_EBPF_JIT if MMU
+ select HAVE_EFFICIENT_UNALIGNED_ACCESS
select HAVE_FUNCTION_ERROR_INJECTION
select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_GCC_PLUGINS
--
2.18.0.huawei.25
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
@ 2021-09-13 12:19 ` Chen Huang
0 siblings, 0 replies; 10+ messages in thread
From: Chen Huang @ 2021-09-13 12:19 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Chen Huang, Kefeng Wang, linux-riscv, linux-kernel
The RISCV ISA can perform efficient unaligned memory accesses
in hardware. This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS
for that.
Signed-off-by: Chen Huang <chenhuang5@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aac669a6c3d8..6e70bf50b02a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -81,6 +81,7 @@ config RISCV
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_CONTIGUOUS if MMU
select HAVE_EBPF_JIT if MMU
+ select HAVE_EFFICIENT_UNALIGNED_ACCESS
select HAVE_FUNCTION_ERROR_INJECTION
select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_GCC_PLUGINS
--
2.18.0.huawei.25
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
2021-09-13 12:19 ` Chen Huang
@ 2021-09-14 17:08 ` Darius Rad
-1 siblings, 0 replies; 10+ messages in thread
From: Darius Rad @ 2021-09-14 17:08 UTC (permalink / raw)
To: Chen Huang, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Kefeng Wang, linux-riscv, linux-kernel
On 9/13/21 8:19 AM, Chen Huang wrote:
> The RISCV ISA can perform efficient unaligned memory accesses
> in hardware. This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS
> for that.
>
Not all implementations do, so it seems like this is not appropriate.
> Signed-off-by: Chen Huang <chenhuang5@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
> arch/riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index aac669a6c3d8..6e70bf50b02a 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -81,6 +81,7 @@ config RISCV
> select HAVE_DEBUG_KMEMLEAK
> select HAVE_DMA_CONTIGUOUS if MMU
> select HAVE_EBPF_JIT if MMU
> + select HAVE_EFFICIENT_UNALIGNED_ACCESS
> select HAVE_FUNCTION_ERROR_INJECTION
> select HAVE_FUTEX_CMPXCHG if FUTEX
> select HAVE_GCC_PLUGINS
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
@ 2021-09-14 17:08 ` Darius Rad
0 siblings, 0 replies; 10+ messages in thread
From: Darius Rad @ 2021-09-14 17:08 UTC (permalink / raw)
To: Chen Huang, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Kefeng Wang, linux-riscv, linux-kernel
On 9/13/21 8:19 AM, Chen Huang wrote:
> The RISCV ISA can perform efficient unaligned memory accesses
> in hardware. This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS
> for that.
>
Not all implementations do, so it seems like this is not appropriate.
> Signed-off-by: Chen Huang <chenhuang5@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
> arch/riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index aac669a6c3d8..6e70bf50b02a 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -81,6 +81,7 @@ config RISCV
> select HAVE_DEBUG_KMEMLEAK
> select HAVE_DMA_CONTIGUOUS if MMU
> select HAVE_EBPF_JIT if MMU
> + select HAVE_EFFICIENT_UNALIGNED_ACCESS
> select HAVE_FUNCTION_ERROR_INJECTION
> select HAVE_FUTEX_CMPXCHG if FUTEX
> select HAVE_GCC_PLUGINS
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/2] riscv: Support DCACHE_WORD_ACCESS
2021-09-13 12:19 ` Chen Huang
@ 2021-09-13 12:19 ` Chen Huang
-1 siblings, 0 replies; 10+ messages in thread
From: Chen Huang @ 2021-09-13 12:19 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Chen Huang, Kefeng Wang, linux-riscv, linux-kernel
This patch selects DCACHE_WORD_ACCESS on riscv and implements support
for load_unaligned_zeropad.
DCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string
comparisons in the vfs layer.
Signed-off-by: Chen Huang <chenhuang5@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6e70bf50b02a..f6f0da0f436b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -44,6 +44,7 @@ config RISCV
select CLONE_BACKWARDS
select CLINT_TIMER if !MMU
select COMMON_CLK
+ select DCACHE_WORD_ACCESS
select EDAC_SUPPORT
select GENERIC_ARCH_TOPOLOGY if SMP
select GENERIC_ATOMIC64 if !64BIT
diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/asm/word-at-a-time.h
index 7c086ac6ecd4..0b77ce654f56 100644
--- a/arch/riscv/include/asm/word-at-a-time.h
+++ b/arch/riscv/include/asm/word-at-a-time.h
@@ -11,6 +11,8 @@
#include <linux/kernel.h>
+#include <asm/asm.h>
+
struct word_at_a_time {
const unsigned long one_bits, high_bits;
};
@@ -45,4 +47,38 @@ static inline unsigned long find_zero(unsigned long mask)
/* The mask we created is directly usable as a bytemask */
#define zero_bytemask(mask) (mask)
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+ unsigned long ret, tmp;
+
+ /* Load word from unaligned pointer addr */
+ asm(
+ "1: " REG_L " %0, %3\n"
+ "2:\n"
+ " .section .fixup,\"ax\"\n"
+ " .balign 2\n"
+ "3: andi %1, %2, ~0x7\n"
+ " " REG_L " %0, (%1)\n"
+ " andi %1, %2, 0x7\n"
+ " slli %1, %1, 0x3\n"
+ " srl %0, %0, %1\n"
+ " jump 2b, %1\n"
+ " .previous\n"
+ " .section __ex_table,\"a\"\n"
+ " .balign " RISCV_SZPTR "\n"
+ " " RISCV_PTR " 1b, 3b\n"
+ " .previous"
+ : "=&r" (ret), "=&r" (tmp)
+ : "r" (addr), "m" (*(unsigned long *)addr));
+
+ return ret;
+}
+
#endif /* _ASM_RISCV_WORD_AT_A_TIME_H */
--
2.18.0.huawei.25
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/2] riscv: Support DCACHE_WORD_ACCESS
@ 2021-09-13 12:19 ` Chen Huang
0 siblings, 0 replies; 10+ messages in thread
From: Chen Huang @ 2021-09-13 12:19 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Chen Huang, Kefeng Wang, linux-riscv, linux-kernel
This patch selects DCACHE_WORD_ACCESS on riscv and implements support
for load_unaligned_zeropad.
DCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string
comparisons in the vfs layer.
Signed-off-by: Chen Huang <chenhuang5@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6e70bf50b02a..f6f0da0f436b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -44,6 +44,7 @@ config RISCV
select CLONE_BACKWARDS
select CLINT_TIMER if !MMU
select COMMON_CLK
+ select DCACHE_WORD_ACCESS
select EDAC_SUPPORT
select GENERIC_ARCH_TOPOLOGY if SMP
select GENERIC_ATOMIC64 if !64BIT
diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/asm/word-at-a-time.h
index 7c086ac6ecd4..0b77ce654f56 100644
--- a/arch/riscv/include/asm/word-at-a-time.h
+++ b/arch/riscv/include/asm/word-at-a-time.h
@@ -11,6 +11,8 @@
#include <linux/kernel.h>
+#include <asm/asm.h>
+
struct word_at_a_time {
const unsigned long one_bits, high_bits;
};
@@ -45,4 +47,38 @@ static inline unsigned long find_zero(unsigned long mask)
/* The mask we created is directly usable as a bytemask */
#define zero_bytemask(mask) (mask)
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+ unsigned long ret, tmp;
+
+ /* Load word from unaligned pointer addr */
+ asm(
+ "1: " REG_L " %0, %3\n"
+ "2:\n"
+ " .section .fixup,\"ax\"\n"
+ " .balign 2\n"
+ "3: andi %1, %2, ~0x7\n"
+ " " REG_L " %0, (%1)\n"
+ " andi %1, %2, 0x7\n"
+ " slli %1, %1, 0x3\n"
+ " srl %0, %0, %1\n"
+ " jump 2b, %1\n"
+ " .previous\n"
+ " .section __ex_table,\"a\"\n"
+ " .balign " RISCV_SZPTR "\n"
+ " " RISCV_PTR " 1b, 3b\n"
+ " .previous"
+ : "=&r" (ret), "=&r" (tmp)
+ : "r" (addr), "m" (*(unsigned long *)addr));
+
+ return ret;
+}
+
#endif /* _ASM_RISCV_WORD_AT_A_TIME_H */
--
2.18.0.huawei.25
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [SPAM] [PATCH 0/2] riscv: improve unaligned memory accesses
2021-09-13 12:19 ` Chen Huang
` (2 preceding siblings ...)
(?)
@ 2021-09-15 14:13 ` Jisheng Zhang
2021-09-16 2:54 ` Chen Huang
-1 siblings, 1 reply; 10+ messages in thread
From: Jisheng Zhang @ 2021-09-15 14:13 UTC (permalink / raw)
To: Chen Huang
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Kefeng Wang,
linux-riscv, linux-kernel
On Mon, 13 Sep 2021 12:19:54 +0000
Chen Huang <chenhuang5@huawei.com> wrote:
> The RISCV ISA can support unaligned memory accesses, so the patchset
> selects HAVE_EFFICIENT_UNALIGNED_ACCESS and supports DCACHE_WORD_ACCESS
NO, per the spec, "Even when misaligned loads and stores complete
successfully, these accesses might run extremely slowly depending on the
implementation". it's far away from "efficient"
> to improve the efficiency of unaligned memory accesses.
>
> Chen Huang (2):
> riscv: Kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS
> riscv: Support DCACHE_WORD_ACCESS
>
> arch/riscv/Kconfig | 2 ++
> arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++
> 2 files changed, 38 insertions(+)
>
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [SPAM] [PATCH 0/2] riscv: improve unaligned memory accesses
2021-09-15 14:13 ` [SPAM] [PATCH 0/2] riscv: improve unaligned memory accesses Jisheng Zhang
@ 2021-09-16 2:54 ` Chen Huang
0 siblings, 0 replies; 10+ messages in thread
From: Chen Huang @ 2021-09-16 2:54 UTC (permalink / raw)
To: Jisheng Zhang, Darius Rad
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Kefeng Wang,
linux-riscv, linux-kernel
Like ARM，powerpc and m68K，some CPUs don't support the unaligned memory access,
offer this as an option that CPU can choose it depending on its own design. I will
send v2 soon.
在 2021/9/15 22:13, Jisheng Zhang 写道:
> On Mon, 13 Sep 2021 12:19:54 +0000
> Chen Huang <chenhuang5@huawei.com> wrote:
>
>> The RISCV ISA can support unaligned memory accesses, so the patchset
>> selects HAVE_EFFICIENT_UNALIGNED_ACCESS and supports DCACHE_WORD_ACCESS
>
> NO, per the spec, "Even when misaligned loads and stores complete
> successfully, these accesses might run extremely slowly depending on the
> implementation". it's far away from "efficient"
>
>> to improve the efficiency of unaligned memory accesses.
>>
>> Chen Huang (2):
>> riscv: Kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS
>> riscv: Support DCACHE_WORD_ACCESS
>>
>> arch/riscv/Kconfig | 2 ++
>> arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++
>> 2 files changed, 38 insertions(+)
>>
>
>
> .
>
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^ permalink raw reply [flat|nested] 10+ messages in thread