From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> To: Marc Kleine-Budde <mkl@pengutronix.de>, netdev@vger.kernel.org, wg@grandegger.com, linux-can@vger.kernel.org Cc: linux-sh@vger.kernel.org, vksavl@gmail.com Subject: Re: [PATCH v5] can: add Renesas R-Car CAN driver Date: Fri, 28 Feb 2014 11:16:23 +0000 [thread overview] Message-ID: <53107007.7050802@cogentembedded.com> (raw) In-Reply-To: <5310521E.6000708@pengutronix.de> Hello. On 28-02-2014 13:08, Marc Kleine-Budde wrote: >>>> 1. According to documentation BCR is the 24-bit register. >>>> Actually we can consider some 32-bit register that combines BCR and >>>> CLKR but according to documentation there are two separate registers. >>>> 2. BCR has 8- ,16-, and 32-bit access (according to documentation). >>>> 3. This is the algorithm that the documentation suggests. >>>> 4. We had a driver version with byte access but 32-bit access seems >>>> shorter. >>> Please use a normal read-modify-write 32 bit access. >> IMO, reading 32-bits is futile, as we're going to completely >> overwrite those 24 bits that constitute BCR. So I kept the 8-bit CLKR >> read but removed the CLKR write in the end. I've also added a comment >> clarifying why CLKR is positioned in the LSBs of 32-bit word (while it's >> address would assume MSBs). >> The host bus is big-endian but byte-swaps at least 16- and 32-bit >> accesses, so that read[wl]()/write[wl]() work. 8-bit accesses are not >> byte swapped, despite what the figure in the manual shows. > A 32 bit read/modify/write is a standard operation, nothing special, no > need to worry about byte swapping or anything like this. Oh, really? 8-) Don't you know that read[bwlq]() assume little-endian memory layout and to read from big-endian 32-bit register one normally needs readl_be()? > Marc WBR, Sergei
WARNING: multiple messages have this Message-ID (diff)
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> To: Marc Kleine-Budde <mkl@pengutronix.de>, netdev@vger.kernel.org, wg@grandegger.com, linux-can@vger.kernel.org Cc: linux-sh@vger.kernel.org, vksavl@gmail.com Subject: Re: [PATCH v5] can: add Renesas R-Car CAN driver Date: Fri, 28 Feb 2014 15:16:23 +0400 [thread overview] Message-ID: <53107007.7050802@cogentembedded.com> (raw) In-Reply-To: <5310521E.6000708@pengutronix.de> Hello. On 28-02-2014 13:08, Marc Kleine-Budde wrote: >>>> 1. According to documentation BCR is the 24-bit register. >>>> Actually we can consider some 32-bit register that combines BCR and >>>> CLKR but according to documentation there are two separate registers. >>>> 2. BCR has 8- ,16-, and 32-bit access (according to documentation). >>>> 3. This is the algorithm that the documentation suggests. >>>> 4. We had a driver version with byte access but 32-bit access seems >>>> shorter. >>> Please use a normal read-modify-write 32 bit access. >> IMO, reading 32-bits is futile, as we're going to completely >> overwrite those 24 bits that constitute BCR. So I kept the 8-bit CLKR >> read but removed the CLKR write in the end. I've also added a comment >> clarifying why CLKR is positioned in the LSBs of 32-bit word (while it's >> address would assume MSBs). >> The host bus is big-endian but byte-swaps at least 16- and 32-bit >> accesses, so that read[wl]()/write[wl]() work. 8-bit accesses are not >> byte swapped, despite what the figure in the manual shows. > A 32 bit read/modify/write is a standard operation, nothing special, no > need to worry about byte swapping or anything like this. Oh, really? 8-) Don't you know that read[bwlq]() assume little-endian memory layout and to read from big-endian 32-bit register one normally needs readl_be()? > Marc WBR, Sergei
next prev parent reply other threads:[~2014-02-28 11:16 UTC|newest] Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-12-26 20:37 [PATCH v5] can: add Renesas R-Car CAN driver Sergei Shtylyov 2013-12-26 21:37 ` Sergei Shtylyov 2014-01-13 13:46 ` Sergei Shtylyov 2014-01-13 13:46 ` Sergei Shtylyov 2014-01-20 9:18 ` Marc Kleine-Budde 2014-01-20 9:18 ` Marc Kleine-Budde 2014-01-25 0:34 ` Sergei Shtylyov 2014-01-25 1:34 ` Sergei Shtylyov 2014-02-13 12:12 ` Marc Kleine-Budde 2014-02-13 12:12 ` Marc Kleine-Budde 2014-02-20 22:48 ` Sergei Shtylyov 2014-02-20 23:48 ` Sergei Shtylyov 2014-02-28 9:08 ` Marc Kleine-Budde 2014-02-28 9:08 ` Marc Kleine-Budde 2014-02-28 11:16 ` Sergei Shtylyov [this message] 2014-02-28 11:16 ` Sergei Shtylyov 2014-02-28 11:37 ` Marc Kleine-Budde 2014-02-28 11:37 ` Marc Kleine-Budde 2014-02-28 11:41 ` Geert Uytterhoeven 2014-02-28 11:41 ` Geert Uytterhoeven 2014-02-28 11:47 ` David Laight 2014-02-28 11:47 ` David Laight 2014-02-28 11:50 ` Marc Kleine-Budde 2014-02-28 11:50 ` Marc Kleine-Budde 2014-02-28 12:02 ` David Laight 2014-02-28 12:02 ` David Laight 2014-02-28 11:49 ` Marc Kleine-Budde 2014-02-28 11:49 ` Marc Kleine-Budde 2014-02-28 12:05 ` Sergei Shtylyov 2014-02-28 12:05 ` Sergei Shtylyov 2014-02-28 12:17 ` David Laight 2014-02-28 12:17 ` David Laight 2014-02-28 12:34 ` Sergei Shtylyov 2014-02-28 12:34 ` Sergei Shtylyov 2014-01-20 11:43 ` Geert Uytterhoeven 2014-01-20 11:43 ` Geert Uytterhoeven 2014-01-20 11:47 ` Marc Kleine-Budde 2014-01-20 11:47 ` Marc Kleine-Budde 2014-01-20 11:52 ` Geert Uytterhoeven 2014-01-20 11:52 ` Geert Uytterhoeven 2014-01-20 11:58 ` Marc Kleine-Budde 2014-01-20 11:58 ` Marc Kleine-Budde 2014-01-20 12:02 ` Ben Dooks 2014-01-20 12:05 ` Geert Uytterhoeven 2014-01-20 12:05 ` Geert Uytterhoeven 2014-01-20 12:08 ` Marc Kleine-Budde 2014-01-20 12:08 ` Marc Kleine-Budde 2014-01-20 12:05 ` Marc Kleine-Budde 2014-01-20 12:05 ` Marc Kleine-Budde 2014-01-20 12:13 ` David Laight 2014-01-20 12:13 ` David Laight 2014-01-20 12:35 ` Marc Kleine-Budde 2014-01-20 12:35 ` Marc Kleine-Budde 2014-01-20 19:16 ` David Miller 2014-01-20 19:16 ` David Miller 2014-01-20 21:12 ` Sergei Shtylyov 2014-01-20 22:12 ` Sergei Shtylyov 2014-01-20 21:17 ` Marc Kleine-Budde 2014-01-20 21:17 ` Marc Kleine-Budde 2014-01-22 11:52 ` Ben Dooks 2014-01-22 11:54 ` Geert Uytterhoeven 2014-01-22 11:54 ` Geert Uytterhoeven 2014-01-22 11:58 ` David Laight 2014-01-22 11:58 ` David Laight 2014-01-20 12:12 ` Sergei Shtylyov 2014-01-20 12:12 ` Sergei Shtylyov
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