[U-Boot] [PATCH 0/3] ARM: at91: add PLLB handle functions

[U-Boot] [PATCH 0/3] ARM: at91: add PLLB handle functions

[Wenyou Yang]

To reduce the duplicated code, add PLLB enable/disable functions,
replace the UTMI PLL handle code with these functions.

It is based on the following patch set.
	[PATCH 0/5] ARM: at91: improve peripheral and system clock handle functions
	[PATCH 0/4] ARM: at91: add UTMI PLL handle functions


Wenyou Yang (3):
  ARM: at91: clock: add PLLB enable/disable functions
  drivers: usb: ohci-at91: clean up the PLLB code
  board: atmel: siemens: clean up PLLB code

 arch/arm/mach-at91/arm926ejs/clock.c  |   38 +++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/include/mach/clk.h |    2 ++
 board/siemens/smartweb/smartweb.c     |    6 +-----
 board/siemens/taurus/taurus.c         |    6 +-----
 drivers/usb/host/ohci-at91.c          |   20 +++++------------
 5 files changed, 47 insertions(+), 25 deletions(-)

-- 
1.7.9.5

[U-Boot] [PATCH 1/3] ARM: at91: clock: add PLLB enable/disable functions

[Wenyou Yang]

To avoid the duplicated code, add the PLLB handle functions.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

 arch/arm/mach-at91/arm926ejs/clock.c  |   38 +++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/include/mach/clk.h |    2 ++
 2 files changed, 40 insertions(+)

diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
index c8b5e10..c8d24ae 100644
--- a/arch/arm/mach-at91/arm926ejs/clock.c
+++ b/arch/arm/mach-at91/arm926ejs/clock.c
@@ -18,6 +18,8 @@
 # error You need to define CONFIG_AT91FAMILY in your board config!
 #endif
 
+#define EN_PLLB_TIMEOUT	500
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static unsigned long at91_css_to_rate(unsigned long css)
@@ -242,3 +244,39 @@ void at91_mck_init(u32 mckr)
 	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
 		;
 }
+
+int at91_pllb_clk_enable(u32 pllbr)
+{
+	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+	ulong start_time, tmp_time;
+
+	start_time = get_timer(0);
+	writel(pllbr, &pmc->pllbr);
+	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
+		tmp_time = get_timer(0);
+		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
+			printf("ERROR: failed to enable PLLB\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+int at91_pllb_clk_disable(void)
+{
+	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+	ulong start_time, tmp_time;
+
+	start_time = get_timer(0);
+	writel(0, &pmc->pllbr);
+	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
+		tmp_time = get_timer(0);
+		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
+			printf("ERROR: failed to disable PLLB\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h
index b2604ef..64dec52 100644
--- a/arch/arm/mach-at91/include/mach/clk.h
+++ b/arch/arm/mach-at91/include/mach/clk.h
@@ -133,5 +133,7 @@ void at91_system_clk_disable(int sys_clk);
 int at91_upll_clk_enable(void);
 int at91_upll_clk_disable(void);
 void at91_usb_clk_init(u32 value);
+int at91_pllb_clk_enable(u32 pllbr);
+int at91_pllb_clk_disable(void);
 
 #endif /* __ASM_ARM_ARCH_CLK_H__ */
-- 
1.7.9.5

[U-Boot] [PATCH 2/3] drivers: usb: ohci-at91: clean up the PLLB code

[Wenyou Yang]

Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable/disable code.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

 drivers/usb/host/ohci-at91.c |   20 +++++---------------
 1 file changed, 5 insertions(+), 15 deletions(-)

diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 6ae6959..6431802 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -9,20 +9,13 @@
 
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
 
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
 
 int usb_cpu_init(void)
 {
-	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
-
 #ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
-	/* Enable PLLB */
-	writel(get_pllb_init(), &pmc->pllbr);
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
-		;
+	at91_pllb_clk_enable(get_pllb_init());
+
 #ifdef CONFIG_AT91SAM9N12
 	at91_usb_clk_init(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2);
 #endif
@@ -45,8 +38,6 @@ int usb_cpu_init(void)
 
 int usb_cpu_stop(void)
 {
-	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
-
 	at91_periph_clk_disable(ATMEL_ID_UHP);
 
 	at91_system_clk_disable(ATMEL_PMC_UHP);
@@ -58,10 +49,9 @@ int usb_cpu_stop(void)
 #ifdef CONFIG_AT91SAM9N12
 	at91_usb_clk_init(0);
 #endif
-	/* Disable PLLB */
-	writel(0, &pmc->pllbr);
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
-		;
+
+	at91_pllb_clk_disable();
+
 #elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL)
 	if (at91_upll_clk_disable())
 		return -1;
-- 
1.7.9.5

[U-Boot] [PATCH 3/3] board: atmel: siemens: clean up PLLB code

[Wenyou Yang]

Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable code.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

 board/siemens/smartweb/smartweb.c |    6 +-----
 board/siemens/taurus/taurus.c     |    6 +-----
 2 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
index e7ee65c..47a60a7 100644
--- a/board/siemens/smartweb/smartweb.c
+++ b/board/siemens/smartweb/smartweb.c
@@ -115,12 +115,8 @@ static void smartweb_macb_hw_init(void)
 
 void at91_udp_hw_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
 	/* Enable PLLB */
-	writel(get_pllb_init(), &pmc->pllbr);
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
-		;
+	at91_pllb_clk_enable(get_pllb_init());
 
 	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
 	at91_periph_clk_enable(ATMEL_ID_UDP);
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 9374064..b0385d8 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -289,12 +289,8 @@ void spi_cs_deactivate(struct spi_slave *slave)
 
 void at91_udp_hw_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
 	/* Enable PLLB */
-	writel(get_pllb_init(), &pmc->pllbr);
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
-		;
+	at91_pllb_clk_enable(get_pllb_init());
 
 	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
 	at91_periph_clk_enable(ATMEL_ID_UDP);
-- 
1.7.9.5

[U-Boot] [PATCH 1/3] ARM: at91: clock: add PLLB enable/disable functions

[Heiko Schocher]

Hello Wenyou,

Am 09.12.2015 um 05:29 schrieb Wenyou Yang:
> To avoid the duplicated code, add the PLLB handle functions.
>
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> ---
>
>   arch/arm/mach-at91/arm926ejs/clock.c  |   38 +++++++++++++++++++++++++++++++++
>   arch/arm/mach-at91/include/mach/clk.h |    2 ++
>   2 files changed, 40 insertions(+)

Tested on the smartweb board, see log:
http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/29/steps/shell/logs/tbotlog

Tested-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
>
> diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
> index c8b5e10..c8d24ae 100644
> --- a/arch/arm/mach-at91/arm926ejs/clock.c
> +++ b/arch/arm/mach-at91/arm926ejs/clock.c
> @@ -18,6 +18,8 @@
>   # error You need to define CONFIG_AT91FAMILY in your board config!
>   #endif
>
> +#define EN_PLLB_TIMEOUT	500
> +
>   DECLARE_GLOBAL_DATA_PTR;
>
>   static unsigned long at91_css_to_rate(unsigned long css)
> @@ -242,3 +244,39 @@ void at91_mck_init(u32 mckr)
>   	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
>   		;
>   }
> +
> +int at91_pllb_clk_enable(u32 pllbr)
> +{
> +	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> +	ulong start_time, tmp_time;
> +
> +	start_time = get_timer(0);
> +	writel(pllbr, &pmc->pllbr);
> +	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
> +		tmp_time = get_timer(0);
> +		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
> +			printf("ERROR: failed to enable PLLB\n");
> +			return -1;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +int at91_pllb_clk_disable(void)
> +{
> +	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> +	ulong start_time, tmp_time;
> +
> +	start_time = get_timer(0);
> +	writel(0, &pmc->pllbr);
> +	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
> +		tmp_time = get_timer(0);
> +		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
> +			printf("ERROR: failed to disable PLLB\n");
> +			return -1;
> +		}
> +	}
> +
> +	return 0;
> +}
> diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h
> index b2604ef..64dec52 100644
> --- a/arch/arm/mach-at91/include/mach/clk.h
> +++ b/arch/arm/mach-at91/include/mach/clk.h
> @@ -133,5 +133,7 @@ void at91_system_clk_disable(int sys_clk);
>   int at91_upll_clk_enable(void);
>   int at91_upll_clk_disable(void);
>   void at91_usb_clk_init(u32 value);
> +int at91_pllb_clk_enable(u32 pllbr);
> +int at91_pllb_clk_disable(void);
>
>   #endif /* __ASM_ARM_ARCH_CLK_H__ */
>

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH 2/3] drivers: usb: ohci-at91: clean up the PLLB code

[Heiko Schocher]

Hello Wenyou,

Am 09.12.2015 um 05:29 schrieb Wenyou Yang:
> Due to introducing the new PLLB clock handle functions,
> use these functions to clean up the PLLB enable/disable code.
>
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> ---
>
>   drivers/usb/host/ohci-at91.c |   20 +++++---------------
>   1 file changed, 5 insertions(+), 15 deletions(-)

Tested on the smartweb board, see log:
http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/29/steps/shell/logs/tbotlog

Tested-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
>
> diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
> index 6ae6959..6431802 100644
> --- a/drivers/usb/host/ohci-at91.c
> +++ b/drivers/usb/host/ohci-at91.c
> @@ -9,20 +9,13 @@
>
>   #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
>
> -#include <asm/io.h>
> -#include <asm/arch/hardware.h>
> -#include <asm/arch/at91_pmc.h>
>   #include <asm/arch/clk.h>
>
>   int usb_cpu_init(void)
>   {
> -	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
> -
>   #ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
> -	/* Enable PLLB */
> -	writel(get_pllb_init(), &pmc->pllbr);
> -	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
> -		;
> +	at91_pllb_clk_enable(get_pllb_init());
> +
>   #ifdef CONFIG_AT91SAM9N12
>   	at91_usb_clk_init(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2);
>   #endif
> @@ -45,8 +38,6 @@ int usb_cpu_init(void)
>
>   int usb_cpu_stop(void)
>   {
> -	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
> -
>   	at91_periph_clk_disable(ATMEL_ID_UHP);
>
>   	at91_system_clk_disable(ATMEL_PMC_UHP);
> @@ -58,10 +49,9 @@ int usb_cpu_stop(void)
>   #ifdef CONFIG_AT91SAM9N12
>   	at91_usb_clk_init(0);
>   #endif
> -	/* Disable PLLB */
> -	writel(0, &pmc->pllbr);
> -	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
> -		;
> +
> +	at91_pllb_clk_disable();
> +
>   #elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL)
>   	if (at91_upll_clk_disable())
>   		return -1;
>

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH 3/3] board: atmel: siemens: clean up PLLB code

[Heiko Schocher]

Hello Wenyou,

Am 09.12.2015 um 05:29 schrieb Wenyou Yang:
> Due to introducing the new PLLB clock handle functions,
> use these functions to clean up the PLLB enable code.
>
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> ---
>
>   board/siemens/smartweb/smartweb.c |    6 +-----
>   board/siemens/taurus/taurus.c     |    6 +-----
>   2 files changed, 2 insertions(+), 10 deletions(-)

Tested on the smartweb board, see log:
http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/29/steps/shell/logs/tbotlog

Tested-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
>
> diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
> index e7ee65c..47a60a7 100644
> --- a/board/siemens/smartweb/smartweb.c
> +++ b/board/siemens/smartweb/smartweb.c
> @@ -115,12 +115,8 @@ static void smartweb_macb_hw_init(void)
>
>   void at91_udp_hw_init(void)
>   {
> -	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> -
>   	/* Enable PLLB */
> -	writel(get_pllb_init(), &pmc->pllbr);
> -	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
> -		;
> +	at91_pllb_clk_enable(get_pllb_init());
>
>   	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
>   	at91_periph_clk_enable(ATMEL_ID_UDP);
> diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
> index 9374064..b0385d8 100644
> --- a/board/siemens/taurus/taurus.c
> +++ b/board/siemens/taurus/taurus.c
> @@ -289,12 +289,8 @@ void spi_cs_deactivate(struct spi_slave *slave)
>
>   void at91_udp_hw_init(void)
>   {
> -	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> -
>   	/* Enable PLLB */
> -	writel(get_pllb_init(), &pmc->pllbr);
> -	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
> -		;
> +	at91_pllb_clk_enable(get_pllb_init());
>
>   	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
>   	at91_periph_clk_enable(ATMEL_ID_UDP);
>

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH 1/3] ARM: at91: clock: add PLLB enable/disable functions

[Yang, Wenyou]

Hi Heiko,

> -----Original Message-----
> From: Heiko Schocher [mailto:hs at denx.de]
> Sent: 2015?12?10? 17:34
> To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>
> Subject: Re: [U-Boot] [PATCH 1/3] ARM: at91: clock: add PLLB enable/disable
> functions
> 
> Hello Wenyou,
> 
> Am 09.12.2015 um 05:29 schrieb Wenyou Yang:
> > To avoid the duplicated code, add the PLLB handle functions.
> >
> > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> > ---
> >
> >   arch/arm/mach-at91/arm926ejs/clock.c  |   38
> +++++++++++++++++++++++++++++++++
> >   arch/arm/mach-at91/include/mach/clk.h |    2 ++
> >   2 files changed, 40 insertions(+)
> 
> Tested on the smartweb board, see log:
> http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/29/steps/shell/logs/tb
> otlog
> 
> Tested-by: Heiko Schocher <hs@denx.de>

Thank you very much for your effort for ALL series.

> 
> bye,
> Heiko
> >
> > diff --git a/arch/arm/mach-at91/arm926ejs/clock.c
> > b/arch/arm/mach-at91/arm926ejs/clock.c
> > index c8b5e10..c8d24ae 100644
> > --- a/arch/arm/mach-at91/arm926ejs/clock.c
> > +++ b/arch/arm/mach-at91/arm926ejs/clock.c
> > @@ -18,6 +18,8 @@
> >   # error You need to define CONFIG_AT91FAMILY in your board config!
> >   #endif
> >
> > +#define EN_PLLB_TIMEOUT	500
> > +
> >   DECLARE_GLOBAL_DATA_PTR;
> >
> >   static unsigned long at91_css_to_rate(unsigned long css) @@ -242,3
> > +244,39 @@ void at91_mck_init(u32 mckr)
> >   	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
> >   		;
> >   }
> > +
> > +int at91_pllb_clk_enable(u32 pllbr)
> > +{
> > +	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> > +	ulong start_time, tmp_time;
> > +
> > +	start_time = get_timer(0);
> > +	writel(pllbr, &pmc->pllbr);
> > +	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
> > +		tmp_time = get_timer(0);
> > +		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
> > +			printf("ERROR: failed to enable PLLB\n");
> > +			return -1;
> > +		}
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +int at91_pllb_clk_disable(void)
> > +{
> > +	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> > +	ulong start_time, tmp_time;
> > +
> > +	start_time = get_timer(0);
> > +	writel(0, &pmc->pllbr);
> > +	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
> > +		tmp_time = get_timer(0);
> > +		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
> > +			printf("ERROR: failed to disable PLLB\n");
> > +			return -1;
> > +		}
> > +	}
> > +
> > +	return 0;
> > +}
> > diff --git a/arch/arm/mach-at91/include/mach/clk.h
> > b/arch/arm/mach-at91/include/mach/clk.h
> > index b2604ef..64dec52 100644
> > --- a/arch/arm/mach-at91/include/mach/clk.h
> > +++ b/arch/arm/mach-at91/include/mach/clk.h
> > @@ -133,5 +133,7 @@ void at91_system_clk_disable(int sys_clk);
> >   int at91_upll_clk_enable(void);
> >   int at91_upll_clk_disable(void);
> >   void at91_usb_clk_init(u32 value);
> > +int at91_pllb_clk_enable(u32 pllbr);
> > +int at91_pllb_clk_disable(void);
> >
> >   #endif /* __ASM_ARM_ARCH_CLK_H__ */
> >
> 
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Best Regards,
Wenyou Yang

[U-Boot] [PATCH 2/3] drivers: usb: ohci-at91: clean up the PLLB code

[Andreas Bießmann]

Hi Wenyou,

On 09.12.2015 05:29, Wenyou Yang wrote:
> Due to introducing the new PLLB clock handle functions,
> use these functions to clean up the PLLB enable/disable code.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> ---
> 
>  drivers/usb/host/ohci-at91.c |   20 +++++---------------
>  1 file changed, 5 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
> index 6ae6959..6431802 100644
> --- a/drivers/usb/host/ohci-at91.c
> +++ b/drivers/usb/host/ohci-at91.c
> @@ -9,20 +9,13 @@
>  
>  #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
>  
> -#include <asm/io.h>
> -#include <asm/arch/hardware.h>
> -#include <asm/arch/at91_pmc.h>
>  #include <asm/arch/clk.h>
>  
>  int usb_cpu_init(void)
>  {
> -	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
> -
>  #ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
> -	/* Enable PLLB */
> -	writel(get_pllb_init(), &pmc->pllbr);
> -	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
> -		;
> +	at91_pllb_clk_enable(get_pllb_init());
> +

you introduced this function in 'ARM: at91: clock: add PLLB
enable/disable functions' with some timeout checking and respective
return value. Please respect this return value here and exit from
usb_cpu_init() on wrong PLLB setup.

>  #ifdef CONFIG_AT91SAM9N12
>  	at91_usb_clk_init(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2);
>  #endif
> @@ -45,8 +38,6 @@ int usb_cpu_init(void)
>  
>  int usb_cpu_stop(void)
>  {
> -	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
> -
>  	at91_periph_clk_disable(ATMEL_ID_UHP);
>  
>  	at91_system_clk_disable(ATMEL_PMC_UHP);
> @@ -58,10 +49,9 @@ int usb_cpu_stop(void)
>  #ifdef CONFIG_AT91SAM9N12
>  	at91_usb_clk_init(0);
>  #endif
> -	/* Disable PLLB */
> -	writel(0, &pmc->pllbr);
> -	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
> -		;
> +
> +	at91_pllb_clk_disable();
> +

same for the disable function.

>  #elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL)
>  	if (at91_upll_clk_disable())
>  		return -1;
> 

Andreas

[U-Boot] [PATCH 1/3] ARM: at91: clock: add PLLB enable/disable functions

[Andreas Bießmann]

On 09.12.2015 05:29, Wenyou Yang wrote:
> To avoid the duplicated code, add the PLLB handle functions.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>

Reviewed-by: Andreas Bie?mann <andreas.devel@googlemail.com>

> ---
> 
>  arch/arm/mach-at91/arm926ejs/clock.c  |   38 +++++++++++++++++++++++++++++++++
>  arch/arm/mach-at91/include/mach/clk.h |    2 ++
>  2 files changed, 40 insertions(+)
> 
> diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
> index c8b5e10..c8d24ae 100644
> --- a/arch/arm/mach-at91/arm926ejs/clock.c
> +++ b/arch/arm/mach-at91/arm926ejs/clock.c
> @@ -18,6 +18,8 @@
>  # error You need to define CONFIG_AT91FAMILY in your board config!
>  #endif
>  
> +#define EN_PLLB_TIMEOUT	500
> +
>  DECLARE_GLOBAL_DATA_PTR;
>  
>  static unsigned long at91_css_to_rate(unsigned long css)
> @@ -242,3 +244,39 @@ void at91_mck_init(u32 mckr)
>  	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
>  		;
>  }
> +
> +int at91_pllb_clk_enable(u32 pllbr)
> +{
> +	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> +	ulong start_time, tmp_time;
> +
> +	start_time = get_timer(0);
> +	writel(pllbr, &pmc->pllbr);
> +	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
> +		tmp_time = get_timer(0);
> +		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
> +			printf("ERROR: failed to enable PLLB\n");
> +			return -1;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +int at91_pllb_clk_disable(void)
> +{
> +	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> +	ulong start_time, tmp_time;
> +
> +	start_time = get_timer(0);
> +	writel(0, &pmc->pllbr);
> +	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
> +		tmp_time = get_timer(0);
> +		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
> +			printf("ERROR: failed to disable PLLB\n");
> +			return -1;
> +		}
> +	}
> +
> +	return 0;
> +}
> diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h
> index b2604ef..64dec52 100644
> --- a/arch/arm/mach-at91/include/mach/clk.h
> +++ b/arch/arm/mach-at91/include/mach/clk.h
> @@ -133,5 +133,7 @@ void at91_system_clk_disable(int sys_clk);
>  int at91_upll_clk_enable(void);
>  int at91_upll_clk_disable(void);
>  void at91_usb_clk_init(u32 value);
> +int at91_pllb_clk_enable(u32 pllbr);
> +int at91_pllb_clk_disable(void);
>  
>  #endif /* __ASM_ARM_ARCH_CLK_H__ */
> 

[U-Boot] [PATCH 3/3] board: atmel: siemens: clean up PLLB code

[Andreas Bießmann]

On 09.12.2015 05:29, Wenyou Yang wrote:
> Due to introducing the new PLLB clock handle functions,
> use these functions to clean up the PLLB enable code.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>

Reviewed-by: Andreas Bie?mann <andreas.devel@googlemail.com>

> ---
> 
>  board/siemens/smartweb/smartweb.c |    6 +-----
>  board/siemens/taurus/taurus.c     |    6 +-----
>  2 files changed, 2 insertions(+), 10 deletions(-)
> 
> diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
> index e7ee65c..47a60a7 100644
> --- a/board/siemens/smartweb/smartweb.c
> +++ b/board/siemens/smartweb/smartweb.c
> @@ -115,12 +115,8 @@ static void smartweb_macb_hw_init(void)
>  
>  void at91_udp_hw_init(void)
>  {
> -	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> -
>  	/* Enable PLLB */
> -	writel(get_pllb_init(), &pmc->pllbr);
> -	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
> -		;
> +	at91_pllb_clk_enable(get_pllb_init());
>  
>  	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
>  	at91_periph_clk_enable(ATMEL_ID_UDP);
> diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
> index 9374064..b0385d8 100644
> --- a/board/siemens/taurus/taurus.c
> +++ b/board/siemens/taurus/taurus.c
> @@ -289,12 +289,8 @@ void spi_cs_deactivate(struct spi_slave *slave)
>  
>  void at91_udp_hw_init(void)
>  {
> -	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> -
>  	/* Enable PLLB */
> -	writel(get_pllb_init(), &pmc->pllbr);
> -	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
> -		;
> +	at91_pllb_clk_enable(get_pllb_init());
>  
>  	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
>  	at91_periph_clk_enable(ATMEL_ID_UDP);
>