* [PATCH v2 0/3] Adding NPS400 drivers
@ 2016-02-02 13:14 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-02 13:14 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Change Log--
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent registration
since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for ARC)
Note: in order to build we need to merge drivers into srctree which includes new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
Noam Camus (3):
soc: Support for EZchip SoC
clocksource: Add NPS400 timers driver
irqchip: add nps Internal and external irqchips
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++
drivers/clocksource/Kconfig | 7 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 84 +++++++++++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 151 ++++++++++++++++++++
include/soc/nps/common.h | 140 ++++++++++++++++++
9 files changed, 422 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
create mode 100644 drivers/irqchip/irq-eznps.c
create mode 100644 include/soc/nps/common.h
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v2 1/3] soc: Support for EZchip SoC
2016-02-02 13:14 ` Noam Camus
@ 2016-02-02 13:14 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-02 13:14 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus
From: Noam Camus <noamc@ezchip.com>
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus <noamc@ezchip.com>
---
include/soc/nps/common.h | 140 ++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 140 insertions(+), 0 deletions(-)
create mode 100644 include/soc/nps/common.h
diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 0000000..ffd5c04
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ 5
+#endif
+
+#define NPS_HOST_REG_BASE 0xF6000000
+
+#define NPS_MSU_BLKID 0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifndef __arc__
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+ union {
+ struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+ u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+ u32 __reserved:24, cluster:4, core:4;
+#endif
+ };
+ u32 value;
+ };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ * ----------------- ------------------
+ * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)|
+ *
+ * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)|
+ * ----------------- ------------------
+ * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)|
+ *
+ * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)|
+ * ----------------- ------------------
+ * 0 1 2 3
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+ __asm__ __volatile__(
+ " mov r3,%0\n"
+ " .short %1\n"
+ " .word %2\n"
+ " mov %0,r3\n"
+ : "+r"(cluster)
+ : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+ : "r3");
+#endif
+
+ return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+ ({ struct global_id gid; gid.value = cpu; \
+ nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+ union {
+ struct {
+ u32 base:8, cl_x:4, cl_y:4,
+ blkid:6, reg:8, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+struct nps_host_reg_address_non_cl {
+ union {
+ struct {
+ u32 base:7, blkid:11, reg:12, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address_non_cl reg_address;
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address reg_address;
+ u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.cl_x = (cl >> 2) & 0x3;
+ reg_address.cl_y = cl & 0x3;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* SOC_NPS_COMMON_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v2 1/3] soc: Support for EZchip SoC
@ 2016-02-02 13:14 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-02 13:14 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus <noamc at ezchip.com>
---
include/soc/nps/common.h | 140 ++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 140 insertions(+), 0 deletions(-)
create mode 100644 include/soc/nps/common.h
diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 0000000..ffd5c04
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ 5
+#endif
+
+#define NPS_HOST_REG_BASE 0xF6000000
+
+#define NPS_MSU_BLKID 0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifndef __arc__
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+ union {
+ struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+ u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+ u32 __reserved:24, cluster:4, core:4;
+#endif
+ };
+ u32 value;
+ };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ * ----------------- ------------------
+ * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)|
+ *
+ * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)|
+ * ----------------- ------------------
+ * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)|
+ *
+ * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)|
+ * ----------------- ------------------
+ * 0 1 2 3
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+ __asm__ __volatile__(
+ " mov r3,%0\n"
+ " .short %1\n"
+ " .word %2\n"
+ " mov %0,r3\n"
+ : "+r"(cluster)
+ : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+ : "r3");
+#endif
+
+ return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+ ({ struct global_id gid; gid.value = cpu; \
+ nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+ union {
+ struct {
+ u32 base:8, cl_x:4, cl_y:4,
+ blkid:6, reg:8, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+struct nps_host_reg_address_non_cl {
+ union {
+ struct {
+ u32 base:7, blkid:11, reg:12, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address_non_cl reg_address;
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address reg_address;
+ u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.cl_x = (cl >> 2) & 0x3;
+ reg_address.cl_y = cl & 0x3;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* SOC_NPS_COMMON_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 2/3] clocksource: Add NPS400 timers driver
2016-02-02 13:14 ` Noam Camus
@ 2016-02-02 13:14 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-02 13:14 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus, Rob Herring, Thomas Gleixner, John Stultz
From: Noam Camus <noamc@ezchip.com>
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: John Stultz <john.stultz@linaro.org>
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++++
drivers/clocksource/Kconfig | 7 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 84 ++++++++++++++++++++
4 files changed, 107 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 0000000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..859e83d 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,13 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
+config CLKSRC_NPS
+ bool "NPS400 clocksource driver" if COMPILE_TEST
+ select CLKSRC_OF if OF
+ help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 0000000..bf9a490
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/cpu.h>
+#include <soc/nps/common.h>
+
+#define NPS_MSU_TICK_LOW 0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM 16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+ int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+ return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static struct clocksource nps_counter = {
+ .name = "EZnps-tick",
+ .rating = 301,
+ .read = nps_clksrc_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init nps_setup_clocksource(struct device_node *node,
+ struct clk *clk)
+{
+ struct clocksource *clksrc = &nps_counter;
+ int ret, cluster;
+
+ for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+ nps_msu_reg_low_addr[cluster] =
+ nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+ NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ pr_err("Couldn't enable parent clock\n");
+
+ nps_timer_rate = clk_get_rate(clk);
+
+ ret = clocksource_register_hz(clksrc, nps_timer_rate);
+ if (ret)
+ pr_err("Couldn't register clock source.\n");
+}
+
+static void __init nps_timer_init(struct device_node *node)
+{
+ struct clk *clk;
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk))
+ panic("Can't get timer clock");
+
+ nps_setup_clocksource(node, clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
+ nps_timer_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v2 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-02 13:14 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-02 13:14 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus <noamc at ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
Cc: Rob Herring <robh+dt at kernel.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: John Stultz <john.stultz at linaro.org>
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++++
drivers/clocksource/Kconfig | 7 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 84 ++++++++++++++++++++
4 files changed, 107 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 0000000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..859e83d 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,13 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
+config CLKSRC_NPS
+ bool "NPS400 clocksource driver" if COMPILE_TEST
+ select CLKSRC_OF if OF
+ help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 0000000..bf9a490
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/cpu.h>
+#include <soc/nps/common.h>
+
+#define NPS_MSU_TICK_LOW 0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM 16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+ int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+ return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static struct clocksource nps_counter = {
+ .name = "EZnps-tick",
+ .rating = 301,
+ .read = nps_clksrc_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init nps_setup_clocksource(struct device_node *node,
+ struct clk *clk)
+{
+ struct clocksource *clksrc = &nps_counter;
+ int ret, cluster;
+
+ for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+ nps_msu_reg_low_addr[cluster] =
+ nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+ NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ pr_err("Couldn't enable parent clock\n");
+
+ nps_timer_rate = clk_get_rate(clk);
+
+ ret = clocksource_register_hz(clksrc, nps_timer_rate);
+ if (ret)
+ pr_err("Couldn't register clock source.\n");
+}
+
+static void __init nps_timer_init(struct device_node *node)
+{
+ struct clk *clk;
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk))
+ panic("Can't get timer clock");
+
+ nps_setup_clocksource(node, clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
+ nps_timer_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH v2 2/3] clocksource: Add NPS400 timers driver
2016-02-02 13:14 ` Noam Camus
@ 2016-02-02 14:36 ` kbuild test robot
-1 siblings, 0 replies; 60+ messages in thread
From: kbuild test robot @ 2016-02-02 14:36 UTC (permalink / raw)
To: Noam Camus
Cc: kbuild-all, linux-kernel, linux-snps-arc, daniel.lezcano,
marc.zyngier, cmetcalf, talz, giladb, Noam Camus, Rob Herring,
Thomas Gleixner, John Stultz
[-- Attachment #1: Type: text/plain, Size: 2878 bytes --]
Hi Noam,
[auto build test WARNING on tip/irq/core]
[also build test WARNING on v4.5-rc2 next-20160201]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/Noam-Camus/Adding-NPS400-drivers/20160202-213530
config: x86_64-allmodconfig (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
In file included from drivers/clocksource/timer-nps.c:24:0:
include/soc/nps/common.h: In function 'nps_host_reg_non_cl':
>> include/soc/nps/common.h:122:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
return (void *)reg_address.value;
^
include/soc/nps/common.h: In function 'nps_host_reg':
include/soc/nps/common.h:136:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
return (void *)reg_address.value;
^
vim +122 include/soc/nps/common.h
f44c724c Noam Camus 2016-02-02 106 union {
f44c724c Noam Camus 2016-02-02 107 struct {
f44c724c Noam Camus 2016-02-02 108 u32 base:7, blkid:11, reg:12, __reserved:2;
f44c724c Noam Camus 2016-02-02 109 };
f44c724c Noam Camus 2016-02-02 110 u32 value;
f44c724c Noam Camus 2016-02-02 111 };
f44c724c Noam Camus 2016-02-02 112 };
f44c724c Noam Camus 2016-02-02 113
f44c724c Noam Camus 2016-02-02 114 static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
f44c724c Noam Camus 2016-02-02 115 {
f44c724c Noam Camus 2016-02-02 116 struct nps_host_reg_address_non_cl reg_address;
f44c724c Noam Camus 2016-02-02 117
f44c724c Noam Camus 2016-02-02 118 reg_address.value = NPS_HOST_REG_BASE;
f44c724c Noam Camus 2016-02-02 119 reg_address.blkid = blkid;
f44c724c Noam Camus 2016-02-02 120 reg_address.reg = reg;
f44c724c Noam Camus 2016-02-02 121
f44c724c Noam Camus 2016-02-02 @122 return (void *)reg_address.value;
f44c724c Noam Camus 2016-02-02 123 }
f44c724c Noam Camus 2016-02-02 124
f44c724c Noam Camus 2016-02-02 125 static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
f44c724c Noam Camus 2016-02-02 126 {
f44c724c Noam Camus 2016-02-02 127 struct nps_host_reg_address reg_address;
f44c724c Noam Camus 2016-02-02 128 u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
f44c724c Noam Camus 2016-02-02 129
f44c724c Noam Camus 2016-02-02 130 reg_address.value = NPS_HOST_REG_BASE;
:::::: The code at line 122 was first introduced by commit
:::::: f44c724ca34c57edebb15cae51eaa8d9b6976526 soc: Support for EZchip SoC
:::::: TO: Noam Camus <noamc@ezchip.com>
:::::: CC: 0day robot <fengguang.wu@intel.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 51085 bytes --]
^ permalink raw reply [flat|nested] 60+ messages in thread* [PATCH v2 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-02 14:36 ` kbuild test robot
0 siblings, 0 replies; 60+ messages in thread
From: kbuild test robot @ 2016-02-02 14:36 UTC (permalink / raw)
To: linux-snps-arc
Hi Noam,
[auto build test WARNING on tip/irq/core]
[also build test WARNING on v4.5-rc2 next-20160201]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/Noam-Camus/Adding-NPS400-drivers/20160202-213530
config: x86_64-allmodconfig (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
In file included from drivers/clocksource/timer-nps.c:24:0:
include/soc/nps/common.h: In function 'nps_host_reg_non_cl':
>> include/soc/nps/common.h:122:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
return (void *)reg_address.value;
^
include/soc/nps/common.h: In function 'nps_host_reg':
include/soc/nps/common.h:136:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
return (void *)reg_address.value;
^
vim +122 include/soc/nps/common.h
f44c724c Noam Camus 2016-02-02 106 union {
f44c724c Noam Camus 2016-02-02 107 struct {
f44c724c Noam Camus 2016-02-02 108 u32 base:7, blkid:11, reg:12, __reserved:2;
f44c724c Noam Camus 2016-02-02 109 };
f44c724c Noam Camus 2016-02-02 110 u32 value;
f44c724c Noam Camus 2016-02-02 111 };
f44c724c Noam Camus 2016-02-02 112 };
f44c724c Noam Camus 2016-02-02 113
f44c724c Noam Camus 2016-02-02 114 static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
f44c724c Noam Camus 2016-02-02 115 {
f44c724c Noam Camus 2016-02-02 116 struct nps_host_reg_address_non_cl reg_address;
f44c724c Noam Camus 2016-02-02 117
f44c724c Noam Camus 2016-02-02 118 reg_address.value = NPS_HOST_REG_BASE;
f44c724c Noam Camus 2016-02-02 119 reg_address.blkid = blkid;
f44c724c Noam Camus 2016-02-02 120 reg_address.reg = reg;
f44c724c Noam Camus 2016-02-02 121
f44c724c Noam Camus 2016-02-02 @122 return (void *)reg_address.value;
f44c724c Noam Camus 2016-02-02 123 }
f44c724c Noam Camus 2016-02-02 124
f44c724c Noam Camus 2016-02-02 125 static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
f44c724c Noam Camus 2016-02-02 126 {
f44c724c Noam Camus 2016-02-02 127 struct nps_host_reg_address reg_address;
f44c724c Noam Camus 2016-02-02 128 u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
f44c724c Noam Camus 2016-02-02 129
f44c724c Noam Camus 2016-02-02 130 reg_address.value = NPS_HOST_REG_BASE;
:::::: The code at line 122 was first introduced by commit
:::::: f44c724ca34c57edebb15cae51eaa8d9b6976526 soc: Support for EZchip SoC
:::::: TO: Noam Camus <noamc at ezchip.com>
:::::: CC: 0day robot <fengguang.wu at intel.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
-------------- next part --------------
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^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v2 3/3] irqchip: add nps Internal and external irqchips
2016-02-02 13:14 ` Noam Camus
@ 2016-02-02 13:14 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-02 13:14 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus, Thomas Gleixner, Jason Cooper
From: Noam Camus <noamc@ezchip.com>
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
---
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 151 ++++++++++++++++++++
4 files changed, 175 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 drivers/irqchip/irq-eznps.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 0000000..888b2b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "ezchip,nps400-ic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+ bool "NPS400 Global Interrupt Manager (GIM)"
+ select IRQ_DOMAIN
+ help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 0000000..ac29f32
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <soc/nps/common.h>
+
+#undef NR_CPU_IRQS
+#define NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
+#define TIMER0_IRQ 3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb &= ~(1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb |= (1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+ /* Don't ack before all device access attempts are done */
+ mb();
+
+#ifdef __arc__
+ __asm__ __volatile__ (
+ " .word %0\n"
+ :
+ : "i"(CTOP_INST_RSPI_GIC_0_R12)
+ : "memory");
+#endif
+}
+
+static void nps400_irq_eoi(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+}
+
+static struct irq_chip nps400_irq_chip_fasteoi = {
+ .name = "NPS400 IC Global",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi_global,
+};
+
+static struct irq_chip nps400_irq_chip_percpu = {
+ .name = "NPS400 IC",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi,
+};
+
+static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ switch (hw) {
+ case TIMER0_IRQ:
+#ifdef CONFIG_SMP
+ case IPI_IRQ:
+#endif
+ irq_set_percpu_devid(virq);
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
+ handle_percpu_devid_irq);
+ break;
+ default:
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
+ handle_fasteoi_irq);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops nps400_irq_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = nps400_irq_map,
+};
+
+static int __init nps400_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ static struct irq_domain *nps400_root_domain;
+
+ if (parent)
+ panic("DeviceTree incore ic not a root irq controller\n");
+
+ nps400_root_domain = irq_domain_add_linear(node, NR_CPU_IRQS,
+ &nps400_irq_ops, NULL);
+
+ if (!nps400_root_domain)
+ panic("nps400 root irq domain not avail\n");
+
+ /*
+ * Needed for primary domain lookup to succeed
+ * This is a primary irqchip, and can never have a parent
+ */
+ irq_set_default_host(nps400_root_domain);
+
+#ifdef CONFIG_SMP
+ irq_create_mapping(nps400_root_domain, IPI_IRQ);
+#endif
+
+ return 0;
+}
+IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v2 3/3] irqchip: add nps Internal and external irqchips
@ 2016-02-02 13:14 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-02 13:14 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noam Camus <noamc at ezchip.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier at arm.com>
---
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 151 ++++++++++++++++++++
4 files changed, 175 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 drivers/irqchip/irq-eznps.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 0000000..888b2b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "ezchip,nps400-ic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+ bool "NPS400 Global Interrupt Manager (GIM)"
+ select IRQ_DOMAIN
+ help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 0000000..ac29f32
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <soc/nps/common.h>
+
+#undef NR_CPU_IRQS
+#define NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
+#define TIMER0_IRQ 3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb &= ~(1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb |= (1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+ /* Don't ack before all device access attempts are done */
+ mb();
+
+#ifdef __arc__
+ __asm__ __volatile__ (
+ " .word %0\n"
+ :
+ : "i"(CTOP_INST_RSPI_GIC_0_R12)
+ : "memory");
+#endif
+}
+
+static void nps400_irq_eoi(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+}
+
+static struct irq_chip nps400_irq_chip_fasteoi = {
+ .name = "NPS400 IC Global",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi_global,
+};
+
+static struct irq_chip nps400_irq_chip_percpu = {
+ .name = "NPS400 IC",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi,
+};
+
+static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ switch (hw) {
+ case TIMER0_IRQ:
+#ifdef CONFIG_SMP
+ case IPI_IRQ:
+#endif
+ irq_set_percpu_devid(virq);
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
+ handle_percpu_devid_irq);
+ break;
+ default:
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
+ handle_fasteoi_irq);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops nps400_irq_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = nps400_irq_map,
+};
+
+static int __init nps400_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ static struct irq_domain *nps400_root_domain;
+
+ if (parent)
+ panic("DeviceTree incore ic not a root irq controller\n");
+
+ nps400_root_domain = irq_domain_add_linear(node, NR_CPU_IRQS,
+ &nps400_irq_ops, NULL);
+
+ if (!nps400_root_domain)
+ panic("nps400 root irq domain not avail\n");
+
+ /*
+ * Needed for primary domain lookup to succeed
+ * This is a primary irqchip, and can never have a parent
+ */
+ irq_set_default_host(nps400_root_domain);
+
+#ifdef CONFIG_SMP
+ irq_create_mapping(nps400_root_domain, IPI_IRQ);
+#endif
+
+ return 0;
+}
+IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH v2 3/3] irqchip: add nps Internal and external irqchips
2016-02-02 13:14 ` Noam Camus
@ 2016-02-02 13:35 ` Thomas Gleixner
-1 siblings, 0 replies; 60+ messages in thread
From: Thomas Gleixner @ 2016-02-02 13:35 UTC (permalink / raw)
To: Noam Camus
Cc: linux-kernel, linux-snps-arc, daniel.lezcano, marc.zyngier,
cmetcalf, talz, giladb, Jason Cooper
On Tue, 2 Feb 2016, Noam Camus wrote:
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/irqdomain.h>
> +#include <linux/irqchip.h>
> +#include <soc/nps/common.h>
> +
> +#undef NR_CPU_IRQS
What's that #undef for?
> +#define NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
> +#define TIMER0_IRQ 3
> +static void nps400_irq_eoi_global(struct irq_data *irqd)
> +{
> + unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
> +
> + write_aux_reg(CTOP_AUX_IACK, 1 << irq);
> +
> + /* Don't ack before all device access attempts are done */
> + mb();
And what is that memory barrier for if this is not on ARC?
> +
> +#ifdef __arc__
> + __asm__ __volatile__ (
> + " .word %0\n"
First of all this wants to be .inst not .word.
> + :
> + : "i"(CTOP_INST_RSPI_GIC_0_R12)
> + : "memory");
And this needs be defined as an inline somewhere in arch/arc and not in the
driver. In the driver you do:
#ifdef CONFIG_ARCH_ARC
# include <arch/....>
#else
static inline void arc_ack_gic(void) { }
#endif
static void nps400_irq_eoi_global
{
....
arc_ack_gic();
}
Hmm?
> +static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
> + irq_hw_number_t hw)
> +{
> + switch (hw) {
> + case TIMER0_IRQ:
> +#ifdef CONFIG_SMP
> + case IPI_IRQ:
> +#endif
> + irq_set_percpu_devid(virq);
> + irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
> + handle_percpu_devid_irq);
> + break;
break;
Please
> + default:
> + irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
> + handle_fasteoi_irq);
> + break;
Ditto.
Thanks,
tglx
^ permalink raw reply [flat|nested] 60+ messages in thread* [PATCH v2 3/3] irqchip: add nps Internal and external irqchips
@ 2016-02-02 13:35 ` Thomas Gleixner
0 siblings, 0 replies; 60+ messages in thread
From: Thomas Gleixner @ 2016-02-02 13:35 UTC (permalink / raw)
To: linux-snps-arc
On Tue, 2 Feb 2016, Noam Camus wrote:
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/irqdomain.h>
> +#include <linux/irqchip.h>
> +#include <soc/nps/common.h>
> +
> +#undef NR_CPU_IRQS
What's that #undef for?
> +#define NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
> +#define TIMER0_IRQ 3
> +static void nps400_irq_eoi_global(struct irq_data *irqd)
> +{
> + unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
> +
> + write_aux_reg(CTOP_AUX_IACK, 1 << irq);
> +
> + /* Don't ack before all device access attempts are done */
> + mb();
And what is that memory barrier for if this is not on ARC?
> +
> +#ifdef __arc__
> + __asm__ __volatile__ (
> + " .word %0\n"
First of all this wants to be .inst not .word.
> + :
> + : "i"(CTOP_INST_RSPI_GIC_0_R12)
> + : "memory");
And this needs be defined as an inline somewhere in arch/arc and not in the
driver. In the driver you do:
#ifdef CONFIG_ARCH_ARC
# include <arch/....>
#else
static inline void arc_ack_gic(void) { }
#endif
static void nps400_irq_eoi_global
{
....
arc_ack_gic();
}
Hmm?
> +static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
> + irq_hw_number_t hw)
> +{
> + switch (hw) {
> + case TIMER0_IRQ:
> +#ifdef CONFIG_SMP
> + case IPI_IRQ:
> +#endif
> + irq_set_percpu_devid(virq);
> + irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
> + handle_percpu_devid_irq);
> + break;
break;
Please
> + default:
> + irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
> + handle_fasteoi_irq);
> + break;
Ditto.
Thanks,
tglx
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v2 3/3] irqchip: add nps Internal and external irqchips
2016-02-02 13:14 ` Noam Camus
@ 2016-02-02 20:40 ` kbuild test robot
-1 siblings, 0 replies; 60+ messages in thread
From: kbuild test robot @ 2016-02-02 20:40 UTC (permalink / raw)
To: Noam Camus
Cc: kbuild-all, linux-kernel, linux-snps-arc, daniel.lezcano,
marc.zyngier, cmetcalf, talz, giladb, Noam Camus,
Thomas Gleixner, Jason Cooper
[-- Attachment #1: Type: text/plain, Size: 7266 bytes --]
Hi Noam,
[auto build test ERROR on tip/irq/core]
[cannot apply to v4.5-rc2 next-20160202]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/Noam-Camus/Adding-NPS400-drivers/20160202-213530
config: arm-allmodconfig (attached as .config)
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All error/warnings (new ones prefixed by >>):
drivers/irqchip/irq-eznps.c: In function 'nps400_irq_mask':
>> drivers/irqchip/irq-eznps.c:43:2: error: implicit declaration of function 'irqd_to_hwirq' [-Werror=implicit-function-declaration]
unsigned int irq = irqd_to_hwirq(irqd);
^
drivers/irqchip/irq-eznps.c: At top level:
>> drivers/irqchip/irq-eznps.c:85:15: error: variable 'nps400_irq_chip_fasteoi' has initializer but incomplete type
static struct irq_chip nps400_irq_chip_fasteoi = {
^
>> drivers/irqchip/irq-eznps.c:86:2: error: unknown field 'name' specified in initializer
.name = "NPS400 IC Global",
^
>> drivers/irqchip/irq-eznps.c:86:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:86:2: warning: (near initialization for 'nps400_irq_chip_fasteoi')
>> drivers/irqchip/irq-eznps.c:87:2: error: unknown field 'irq_mask' specified in initializer
.irq_mask = nps400_irq_mask,
^
drivers/irqchip/irq-eznps.c:87:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:87:2: warning: (near initialization for 'nps400_irq_chip_fasteoi')
>> drivers/irqchip/irq-eznps.c:88:2: error: unknown field 'irq_unmask' specified in initializer
.irq_unmask = nps400_irq_unmask,
^
drivers/irqchip/irq-eznps.c:88:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:88:2: warning: (near initialization for 'nps400_irq_chip_fasteoi')
>> drivers/irqchip/irq-eznps.c:89:2: error: unknown field 'irq_eoi' specified in initializer
.irq_eoi = nps400_irq_eoi_global,
^
drivers/irqchip/irq-eznps.c:89:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:89:2: warning: (near initialization for 'nps400_irq_chip_fasteoi')
>> drivers/irqchip/irq-eznps.c:92:15: error: variable 'nps400_irq_chip_percpu' has initializer but incomplete type
static struct irq_chip nps400_irq_chip_percpu = {
^
drivers/irqchip/irq-eznps.c:93:2: error: unknown field 'name' specified in initializer
.name = "NPS400 IC",
^
drivers/irqchip/irq-eznps.c:93:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:93:2: warning: (near initialization for 'nps400_irq_chip_percpu')
drivers/irqchip/irq-eznps.c:94:2: error: unknown field 'irq_mask' specified in initializer
.irq_mask = nps400_irq_mask,
^
drivers/irqchip/irq-eznps.c:94:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:94:2: warning: (near initialization for 'nps400_irq_chip_percpu')
drivers/irqchip/irq-eznps.c:95:2: error: unknown field 'irq_unmask' specified in initializer
.irq_unmask = nps400_irq_unmask,
^
drivers/irqchip/irq-eznps.c:95:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:95:2: warning: (near initialization for 'nps400_irq_chip_percpu')
drivers/irqchip/irq-eznps.c:96:2: error: unknown field 'irq_eoi' specified in initializer
.irq_eoi = nps400_irq_eoi,
^
drivers/irqchip/irq-eznps.c:96:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:96:2: warning: (near initialization for 'nps400_irq_chip_percpu')
drivers/irqchip/irq-eznps.c: In function 'nps400_irq_map':
>> drivers/irqchip/irq-eznps.c:107:3: error: implicit declaration of function 'irq_set_percpu_devid' [-Werror=implicit-function-declaration]
irq_set_percpu_devid(virq);
^
>> drivers/irqchip/irq-eznps.c:108:3: error: implicit declaration of function 'irq_set_chip_and_handler' [-Werror=implicit-function-declaration]
irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
^
>> drivers/irqchip/irq-eznps.c:109:7: error: 'handle_percpu_devid_irq' undeclared (first use in this function)
handle_percpu_devid_irq);
^
drivers/irqchip/irq-eznps.c:109:7: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/irqchip/irq-eznps.c:113:7: error: 'handle_fasteoi_irq' undeclared (first use in this function)
handle_fasteoi_irq);
^
cc1: some warnings being treated as errors
vim +/irqd_to_hwirq +43 drivers/irqchip/irq-eznps.c
37 * with private HW copy per CPU.
38 */
39
40 static void nps400_irq_mask(struct irq_data *irqd)
41 {
42 unsigned int ienb;
> 43 unsigned int irq = irqd_to_hwirq(irqd);
44
45 ienb = read_aux_reg(AUX_IENABLE);
46 ienb &= ~(1 << irq);
47 write_aux_reg(AUX_IENABLE, ienb);
48 }
49
50 static void nps400_irq_unmask(struct irq_data *irqd)
51 {
52 unsigned int ienb;
53 unsigned int irq = irqd_to_hwirq(irqd);
54
55 ienb = read_aux_reg(AUX_IENABLE);
56 ienb |= (1 << irq);
57 write_aux_reg(AUX_IENABLE, ienb);
58 }
59
60 static void nps400_irq_eoi_global(struct irq_data *irqd)
61 {
62 unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
63
64 write_aux_reg(CTOP_AUX_IACK, 1 << irq);
65
66 /* Don't ack before all device access attempts are done */
67 mb();
68
69 #ifdef __arc__
70 __asm__ __volatile__ (
71 " .word %0\n"
72 :
73 : "i"(CTOP_INST_RSPI_GIC_0_R12)
74 : "memory");
75 #endif
76 }
77
78 static void nps400_irq_eoi(struct irq_data *irqd)
79 {
80 unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
81
82 write_aux_reg(CTOP_AUX_IACK, 1 << irq);
83 }
84
> 85 static struct irq_chip nps400_irq_chip_fasteoi = {
> 86 .name = "NPS400 IC Global",
> 87 .irq_mask = nps400_irq_mask,
> 88 .irq_unmask = nps400_irq_unmask,
> 89 .irq_eoi = nps400_irq_eoi_global,
90 };
91
> 92 static struct irq_chip nps400_irq_chip_percpu = {
93 .name = "NPS400 IC",
94 .irq_mask = nps400_irq_mask,
> 95 .irq_unmask = nps400_irq_unmask,
> 96 .irq_eoi = nps400_irq_eoi,
97 };
98
99 static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
100 irq_hw_number_t hw)
101 {
102 switch (hw) {
103 case TIMER0_IRQ:
104 #ifdef CONFIG_SMP
105 case IPI_IRQ:
106 #endif
> 107 irq_set_percpu_devid(virq);
> 108 irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
> 109 handle_percpu_devid_irq);
110 break;
111 default:
112 irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
> 113 handle_fasteoi_irq);
114 break;
115 }
116
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 54615 bytes --]
^ permalink raw reply [flat|nested] 60+ messages in thread* [PATCH v2 3/3] irqchip: add nps Internal and external irqchips
@ 2016-02-02 20:40 ` kbuild test robot
0 siblings, 0 replies; 60+ messages in thread
From: kbuild test robot @ 2016-02-02 20:40 UTC (permalink / raw)
To: linux-snps-arc
Hi Noam,
[auto build test ERROR on tip/irq/core]
[cannot apply to v4.5-rc2 next-20160202]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/Noam-Camus/Adding-NPS400-drivers/20160202-213530
config: arm-allmodconfig (attached as .config)
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All error/warnings (new ones prefixed by >>):
drivers/irqchip/irq-eznps.c: In function 'nps400_irq_mask':
>> drivers/irqchip/irq-eznps.c:43:2: error: implicit declaration of function 'irqd_to_hwirq' [-Werror=implicit-function-declaration]
unsigned int irq = irqd_to_hwirq(irqd);
^
drivers/irqchip/irq-eznps.c: At top level:
>> drivers/irqchip/irq-eznps.c:85:15: error: variable 'nps400_irq_chip_fasteoi' has initializer but incomplete type
static struct irq_chip nps400_irq_chip_fasteoi = {
^
>> drivers/irqchip/irq-eznps.c:86:2: error: unknown field 'name' specified in initializer
.name = "NPS400 IC Global",
^
>> drivers/irqchip/irq-eznps.c:86:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:86:2: warning: (near initialization for 'nps400_irq_chip_fasteoi')
>> drivers/irqchip/irq-eznps.c:87:2: error: unknown field 'irq_mask' specified in initializer
.irq_mask = nps400_irq_mask,
^
drivers/irqchip/irq-eznps.c:87:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:87:2: warning: (near initialization for 'nps400_irq_chip_fasteoi')
>> drivers/irqchip/irq-eznps.c:88:2: error: unknown field 'irq_unmask' specified in initializer
.irq_unmask = nps400_irq_unmask,
^
drivers/irqchip/irq-eznps.c:88:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:88:2: warning: (near initialization for 'nps400_irq_chip_fasteoi')
>> drivers/irqchip/irq-eznps.c:89:2: error: unknown field 'irq_eoi' specified in initializer
.irq_eoi = nps400_irq_eoi_global,
^
drivers/irqchip/irq-eznps.c:89:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:89:2: warning: (near initialization for 'nps400_irq_chip_fasteoi')
>> drivers/irqchip/irq-eznps.c:92:15: error: variable 'nps400_irq_chip_percpu' has initializer but incomplete type
static struct irq_chip nps400_irq_chip_percpu = {
^
drivers/irqchip/irq-eznps.c:93:2: error: unknown field 'name' specified in initializer
.name = "NPS400 IC",
^
drivers/irqchip/irq-eznps.c:93:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:93:2: warning: (near initialization for 'nps400_irq_chip_percpu')
drivers/irqchip/irq-eznps.c:94:2: error: unknown field 'irq_mask' specified in initializer
.irq_mask = nps400_irq_mask,
^
drivers/irqchip/irq-eznps.c:94:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:94:2: warning: (near initialization for 'nps400_irq_chip_percpu')
drivers/irqchip/irq-eznps.c:95:2: error: unknown field 'irq_unmask' specified in initializer
.irq_unmask = nps400_irq_unmask,
^
drivers/irqchip/irq-eznps.c:95:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:95:2: warning: (near initialization for 'nps400_irq_chip_percpu')
drivers/irqchip/irq-eznps.c:96:2: error: unknown field 'irq_eoi' specified in initializer
.irq_eoi = nps400_irq_eoi,
^
drivers/irqchip/irq-eznps.c:96:2: warning: excess elements in struct initializer
drivers/irqchip/irq-eznps.c:96:2: warning: (near initialization for 'nps400_irq_chip_percpu')
drivers/irqchip/irq-eznps.c: In function 'nps400_irq_map':
>> drivers/irqchip/irq-eznps.c:107:3: error: implicit declaration of function 'irq_set_percpu_devid' [-Werror=implicit-function-declaration]
irq_set_percpu_devid(virq);
^
>> drivers/irqchip/irq-eznps.c:108:3: error: implicit declaration of function 'irq_set_chip_and_handler' [-Werror=implicit-function-declaration]
irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
^
>> drivers/irqchip/irq-eznps.c:109:7: error: 'handle_percpu_devid_irq' undeclared (first use in this function)
handle_percpu_devid_irq);
^
drivers/irqchip/irq-eznps.c:109:7: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/irqchip/irq-eznps.c:113:7: error: 'handle_fasteoi_irq' undeclared (first use in this function)
handle_fasteoi_irq);
^
cc1: some warnings being treated as errors
vim +/irqd_to_hwirq +43 drivers/irqchip/irq-eznps.c
37 * with private HW copy per CPU.
38 */
39
40 static void nps400_irq_mask(struct irq_data *irqd)
41 {
42 unsigned int ienb;
> 43 unsigned int irq = irqd_to_hwirq(irqd);
44
45 ienb = read_aux_reg(AUX_IENABLE);
46 ienb &= ~(1 << irq);
47 write_aux_reg(AUX_IENABLE, ienb);
48 }
49
50 static void nps400_irq_unmask(struct irq_data *irqd)
51 {
52 unsigned int ienb;
53 unsigned int irq = irqd_to_hwirq(irqd);
54
55 ienb = read_aux_reg(AUX_IENABLE);
56 ienb |= (1 << irq);
57 write_aux_reg(AUX_IENABLE, ienb);
58 }
59
60 static void nps400_irq_eoi_global(struct irq_data *irqd)
61 {
62 unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
63
64 write_aux_reg(CTOP_AUX_IACK, 1 << irq);
65
66 /* Don't ack before all device access attempts are done */
67 mb();
68
69 #ifdef __arc__
70 __asm__ __volatile__ (
71 " .word %0\n"
72 :
73 : "i"(CTOP_INST_RSPI_GIC_0_R12)
74 : "memory");
75 #endif
76 }
77
78 static void nps400_irq_eoi(struct irq_data *irqd)
79 {
80 unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
81
82 write_aux_reg(CTOP_AUX_IACK, 1 << irq);
83 }
84
> 85 static struct irq_chip nps400_irq_chip_fasteoi = {
> 86 .name = "NPS400 IC Global",
> 87 .irq_mask = nps400_irq_mask,
> 88 .irq_unmask = nps400_irq_unmask,
> 89 .irq_eoi = nps400_irq_eoi_global,
90 };
91
> 92 static struct irq_chip nps400_irq_chip_percpu = {
93 .name = "NPS400 IC",
94 .irq_mask = nps400_irq_mask,
> 95 .irq_unmask = nps400_irq_unmask,
> 96 .irq_eoi = nps400_irq_eoi,
97 };
98
99 static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
100 irq_hw_number_t hw)
101 {
102 switch (hw) {
103 case TIMER0_IRQ:
104 #ifdef CONFIG_SMP
105 case IPI_IRQ:
106 #endif
> 107 irq_set_percpu_devid(virq);
> 108 irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
> 109 handle_percpu_devid_irq);
110 break;
111 default:
112 irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
> 113 handle_fasteoi_irq);
114 break;
115 }
116
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v3 0/3] Adding NPS400 drivers
2016-02-02 13:14 ` Noam Camus
@ 2016-02-06 16:16 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-06 16:16 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus
From: Noam Camus <noamc@ezchip.com>
Change Log--
v3
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency !PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 bit arch's.
irqchip - Apply all Thomas comments (Thank you)
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent registration
since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for ARC)
Note: in order to build we need to merge drivers into srctree which includes new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
Noam Camus (3):
soc: Support for EZchip SoC
clocksource: Add NPS400 timers driver
irqchip: add nps Internal and external irqchips
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 84 +++++++++++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 145 +++++++++++++++++++
include/soc/nps/common.h | 150 ++++++++++++++++++++
9 files changed, 428 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
create mode 100644 drivers/irqchip/irq-eznps.c
create mode 100644 include/soc/nps/common.h
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v3 0/3] Adding NPS400 drivers
@ 2016-02-06 16:16 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-06 16:16 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Change Log--
v3
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency !PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 bit arch's.
irqchip - Apply all Thomas comments (Thank you)
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent registration
since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for ARC)
Note: in order to build we need to merge drivers into srctree which includes new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
Noam Camus (3):
soc: Support for EZchip SoC
clocksource: Add NPS400 timers driver
irqchip: add nps Internal and external irqchips
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 84 +++++++++++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 145 +++++++++++++++++++
include/soc/nps/common.h | 150 ++++++++++++++++++++
9 files changed, 428 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
create mode 100644 drivers/irqchip/irq-eznps.c
create mode 100644 include/soc/nps/common.h
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v4 0/3] Adding NPS400 drivers
2016-02-06 16:16 ` Noam Camus
@ 2016-02-11 3:02 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 3:02 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus
From: Noam Camus <noamc@ezchip.com>
Change Log--
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using clocksoure mmio driver
v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency !PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 bit arch's.
irqchip - Apply all Thomas comments (Thank you)
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent registration
since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for ARC)
Note: in order to build we need to merge drivers into srctree which includes new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
Noam Camus (3):
soc: Support for EZchip SoC
clocksource: Add NPS400 timers driver
irqchip: add nps Internal and external irqchips
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 80 +++++++++++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 145 +++++++++++++++++++
include/soc/nps/common.h | 150 ++++++++++++++++++++
9 files changed, 425 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
create mode 100644 drivers/irqchip/irq-eznps.c
create mode 100644 include/soc/nps/common.h
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v4 0/3] Adding NPS400 drivers
@ 2016-02-11 3:02 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 3:02 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Change Log--
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using clocksoure mmio driver
v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency !PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 bit arch's.
irqchip - Apply all Thomas comments (Thank you)
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent registration
since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for ARC)
Note: in order to build we need to merge drivers into srctree which includes new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
Noam Camus (3):
soc: Support for EZchip SoC
clocksource: Add NPS400 timers driver
irqchip: add nps Internal and external irqchips
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 80 +++++++++++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 145 +++++++++++++++++++
include/soc/nps/common.h | 150 ++++++++++++++++++++
9 files changed, 425 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
create mode 100644 drivers/irqchip/irq-eznps.c
create mode 100644 include/soc/nps/common.h
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v5 0/3] Adding NPS400 drivers
2016-02-11 3:02 ` Noam Camus
@ 2016-02-11 18:40 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 18:40 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus
From: Noam Camus <noamc@ezchip.com>
Change Log--
v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and proper return value.
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using clocksoure mmio driver at init
v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency !PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 bit arch's.
irqchip - Apply all Thomas comments (Thank you)
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent registration
since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for ARC)
Note: in order to build we need to merge drivers into srctree which includes new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
Noam Camus (3):
soc: Support for EZchip SoC
clocksource: Add NPS400 timers driver
irqchip: add nps Internal and external irqchips
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 82 +++++++++++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 149 +++++++++++++++++++
include/soc/nps/common.h | 150 ++++++++++++++++++++
9 files changed, 431 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
create mode 100644 drivers/irqchip/irq-eznps.c
create mode 100644 include/soc/nps/common.h
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v5 0/3] Adding NPS400 drivers
@ 2016-02-11 18:40 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 18:40 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Change Log--
v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and proper return value.
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using clocksoure mmio driver at init
v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency !PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 bit arch's.
irqchip - Apply all Thomas comments (Thank you)
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent registration
since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for ARC)
Note: in order to build we need to merge drivers into srctree which includes new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
Noam Camus (3):
soc: Support for EZchip SoC
clocksource: Add NPS400 timers driver
irqchip: add nps Internal and external irqchips
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 82 +++++++++++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 149 +++++++++++++++++++
include/soc/nps/common.h | 150 ++++++++++++++++++++
9 files changed, 431 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
create mode 100644 drivers/irqchip/irq-eznps.c
create mode 100644 include/soc/nps/common.h
^ permalink raw reply [flat|nested] 60+ messages in thread
* RE: [PATCH v5 0/3] Adding NPS400 drivers
2016-02-11 18:40 ` Noam Camus
@ 2016-02-17 7:05 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-17 7:05 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, Chris Metcalf,
Tal Zilcer, Gilad Ben Yossef
Waiting for your feedback on my v5 patch set :)
-----Original Message-----
From: Noam Camus
Sent: Thursday, February 11, 2016 8:41 PM
To: linux-kernel@vger.kernel.org
Cc: linux-snps-arc@lists.infradead.org; daniel.lezcano@linaro.org; marc.zyngier@arm.com; Chris Metcalf; Tal Zilcer; Gilad Ben Yossef; Noam Camus
Subject: [PATCH v5 0/3] Adding NPS400 drivers
From: Noam Camus <noamc@ezchip.com>
Change Log--
v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and proper return value.
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using clocksoure mmio driver at init
v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h clocksource -- Avoid 64bit arch's to build driver by adding new dependency !PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 bit arch's.
irqchip - Apply all Thomas comments (Thank you)
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent registration since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for ARC)
Note: in order to build we need to merge drivers into srctree which includes new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
Noam Camus (3):
soc: Support for EZchip SoC
clocksource: Add NPS400 timers driver
irqchip: add nps Internal and external irqchips
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 82 +++++++++++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 149 +++++++++++++++++++
include/soc/nps/common.h | 150 ++++++++++++++++++++
9 files changed, 431 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c create mode 100644 drivers/irqchip/irq-eznps.c create mode 100644 include/soc/nps/common.h
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v5 0/3] Adding NPS400 drivers
@ 2016-02-17 7:05 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-17 7:05 UTC (permalink / raw)
To: linux-snps-arc
Waiting for your feedback on my v5 patch set :)
-----Original Message-----
From: Noam Camus
Sent: Thursday, February 11, 2016 8:41 PM
To: linux-kernel at vger.kernel.org
Cc: linux-snps-arc at lists.infradead.org; daniel.lezcano at linaro.org; marc.zyngier at arm.com; Chris Metcalf; Tal Zilcer; Gilad Ben Yossef; Noam Camus
Subject: [PATCH v5 0/3] Adding NPS400 drivers
From: Noam Camus <noamc@ezchip.com>
Change Log--
v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and proper return value.
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using clocksoure mmio driver at init
v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h clocksource -- Avoid 64bit arch's to build driver by adding new dependency !PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 bit arch's.
irqchip - Apply all Thomas comments (Thank you)
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent registration since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for ARC)
Note: in order to build we need to merge drivers into srctree which includes new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
Noam Camus (3):
soc: Support for EZchip SoC
clocksource: Add NPS400 timers driver
irqchip: add nps Internal and external irqchips
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 82 +++++++++++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 149 +++++++++++++++++++
include/soc/nps/common.h | 150 ++++++++++++++++++++
9 files changed, 431 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c create mode 100644 drivers/irqchip/irq-eznps.c create mode 100644 include/soc/nps/common.h
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v5 1/3] soc: Support for EZchip SoC
2016-02-11 3:02 ` Noam Camus
@ 2016-02-11 18:40 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 18:40 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus
From: Noam Camus <noamc@ezchip.com>
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus <noamc@ezchip.com>
---
include/soc/nps/common.h | 150 ++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 150 insertions(+), 0 deletions(-)
create mode 100644 include/soc/nps/common.h
diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 0000000..35ebb00
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ 5
+#endif
+
+#define NPS_HOST_REG_BASE 0xF6000000
+
+#define NPS_MSU_BLKID 0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+ __asm__ __volatile__ (
+ " .word %0\n"
+ :
+ : "i"(CTOP_INST_RSPI_GIC_0_R12)
+ : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+ union {
+ struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+ u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+ u32 __reserved:24, cluster:4, core:4;
+#endif
+ };
+ u32 value;
+ };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ * ----------------- ------------------
+ * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)|
+ *
+ * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)|
+ * ----------------- ------------------
+ * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)|
+ *
+ * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)|
+ * ----------------- ------------------
+ * 0 1 2 3
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+ __asm__ __volatile__(
+ " mov r3,%0\n"
+ " .short %1\n"
+ " .word %2\n"
+ " mov %0,r3\n"
+ : "+r"(cluster)
+ : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+ : "r3");
+#endif
+
+ return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+ ({ struct global_id gid; gid.value = cpu; \
+ nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+ union {
+ struct {
+ u32 base:8, cl_x:4, cl_y:4,
+ blkid:6, reg:8, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+struct nps_host_reg_address_non_cl {
+ union {
+ struct {
+ u32 base:7, blkid:11, reg:12, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address_non_cl reg_address;
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address reg_address;
+ u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.cl_x = (cl >> 2) & 0x3;
+ reg_address.cl_y = cl & 0x3;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* SOC_NPS_COMMON_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v5 1/3] soc: Support for EZchip SoC
@ 2016-02-11 18:40 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 18:40 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus <noamc at ezchip.com>
---
include/soc/nps/common.h | 150 ++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 150 insertions(+), 0 deletions(-)
create mode 100644 include/soc/nps/common.h
diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 0000000..35ebb00
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ 5
+#endif
+
+#define NPS_HOST_REG_BASE 0xF6000000
+
+#define NPS_MSU_BLKID 0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+ __asm__ __volatile__ (
+ " .word %0\n"
+ :
+ : "i"(CTOP_INST_RSPI_GIC_0_R12)
+ : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+ union {
+ struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+ u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+ u32 __reserved:24, cluster:4, core:4;
+#endif
+ };
+ u32 value;
+ };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ * ----------------- ------------------
+ * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)|
+ *
+ * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)|
+ * ----------------- ------------------
+ * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)|
+ *
+ * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)|
+ * ----------------- ------------------
+ * 0 1 2 3
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+ __asm__ __volatile__(
+ " mov r3,%0\n"
+ " .short %1\n"
+ " .word %2\n"
+ " mov %0,r3\n"
+ : "+r"(cluster)
+ : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+ : "r3");
+#endif
+
+ return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+ ({ struct global_id gid; gid.value = cpu; \
+ nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+ union {
+ struct {
+ u32 base:8, cl_x:4, cl_y:4,
+ blkid:6, reg:8, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+struct nps_host_reg_address_non_cl {
+ union {
+ struct {
+ u32 base:7, blkid:11, reg:12, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address_non_cl reg_address;
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address reg_address;
+ u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.cl_x = (cl >> 2) & 0x3;
+ reg_address.cl_y = cl & 0x3;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* SOC_NPS_COMMON_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v5 2/3] clocksource: Add NPS400 timers driver
2016-02-11 3:02 ` Noam Camus
@ 2016-02-11 18:40 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 18:40 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus, Rob Herring, Thomas Gleixner, John Stultz
From: Noam Camus <noamc@ezchip.com>
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: John Stultz <john.stultz@linaro.org>
Acked-by: Vineet Gupta <vgupta@synopsys.com>
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++++
drivers/clocksource/Kconfig | 10 +++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 82 ++++++++++++++++++++
4 files changed, 108 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 0000000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..fa7be50 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,16 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
+config CLKSRC_NPS
+ bool "NPS400 clocksource driver" if COMPILE_TEST
+ depends on !PHYS_ADDR_T_64BIT
+ select CLKSRC_MMIO
+ select CLKSRC_OF if OF
+ help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+ This counter is accessed via couple of 32 bit memory mapped registers.
+
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 0000000..a89aecb
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/cpu.h>
+#include <soc/nps/common.h>
+
+#define NPS_MSU_TICK_LOW 0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM 16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+ int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+ return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static void __init nps_setup_clocksource(struct device_node *node,
+ struct clk *clk)
+{
+ int ret, cluster;
+
+ for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+ nps_msu_reg_low_addr[cluster] =
+ nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+ NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ pr_err("Couldn't enable parent clock\n");
+ return;
+ }
+
+ nps_timer_rate = clk_get_rate(clk);
+
+ ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
+ nps_timer_rate, 301, 32, nps_clksrc_read);
+ if (ret) {
+ pr_err("Couldn't register clock source.\n");
+ clk_disable_unprepare(clk);
+ }
+}
+
+static void __init nps_timer_init(struct device_node *node)
+{
+ struct clk *clk;
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk)) {
+ pr_err("Can't get timer clock.\n");
+ return;
+ }
+
+ nps_setup_clocksource(node, clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
+ nps_timer_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v5 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-11 18:40 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 18:40 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus <noamc at ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
Cc: Rob Herring <robh+dt at kernel.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: John Stultz <john.stultz at linaro.org>
Acked-by: Vineet Gupta <vgupta at synopsys.com>
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++++
drivers/clocksource/Kconfig | 10 +++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 82 ++++++++++++++++++++
4 files changed, 108 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 0000000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..fa7be50 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,16 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
+config CLKSRC_NPS
+ bool "NPS400 clocksource driver" if COMPILE_TEST
+ depends on !PHYS_ADDR_T_64BIT
+ select CLKSRC_MMIO
+ select CLKSRC_OF if OF
+ help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+ This counter is accessed via couple of 32 bit memory mapped registers.
+
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 0000000..a89aecb
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/cpu.h>
+#include <soc/nps/common.h>
+
+#define NPS_MSU_TICK_LOW 0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM 16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+ int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+ return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static void __init nps_setup_clocksource(struct device_node *node,
+ struct clk *clk)
+{
+ int ret, cluster;
+
+ for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+ nps_msu_reg_low_addr[cluster] =
+ nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+ NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ pr_err("Couldn't enable parent clock\n");
+ return;
+ }
+
+ nps_timer_rate = clk_get_rate(clk);
+
+ ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
+ nps_timer_rate, 301, 32, nps_clksrc_read);
+ if (ret) {
+ pr_err("Couldn't register clock source.\n");
+ clk_disable_unprepare(clk);
+ }
+}
+
+static void __init nps_timer_init(struct device_node *node)
+{
+ struct clk *clk;
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk)) {
+ pr_err("Can't get timer clock.\n");
+ return;
+ }
+
+ nps_setup_clocksource(node, clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
+ nps_timer_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH v5 2/3] clocksource: Add NPS400 timers driver
2016-02-11 18:40 ` Noam Camus
@ 2016-02-11 20:29 ` Daniel Lezcano
-1 siblings, 0 replies; 60+ messages in thread
From: Daniel Lezcano @ 2016-02-11 20:29 UTC (permalink / raw)
To: Noam Camus, linux-kernel
Cc: linux-snps-arc, marc.zyngier, cmetcalf, talz, giladb,
Rob Herring, Thomas Gleixner, John Stultz
On 02/11/2016 07:40 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> Add internal tick generator which is shared by all cores.
> Each cluster of cores view it through dedicated address.
> This is used for SMP system where all CPUs synced by same
> clock source.
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: John Stultz <john.stultz@linaro.org>
> Acked-by: Vineet Gupta <vgupta@synopsys.com>
> ---
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v5 3/3] irqchip: add nps Internal and external irqchips
2016-02-11 3:02 ` Noam Camus
@ 2016-02-11 18:40 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 18:40 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus, Thomas Gleixner, Jason Cooper
From: Noam Camus <noamc@ezchip.com>
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
---
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 149 ++++++++++++++++++++
4 files changed, 173 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 drivers/irqchip/irq-eznps.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 0000000..888b2b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "ezchip,nps400-ic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+ bool "NPS400 Global Interrupt Manager (GIM)"
+ select IRQ_DOMAIN
+ help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 0000000..9decd7d
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <soc/nps/common.h>
+
+#define NPS_NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
+#define NPS_TIMER0_IRQ 3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb &= ~(1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb |= (1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+ /* Don't ack GIC before all device access attempts are done */
+ mb();
+
+ nps_ack_gic();
+}
+
+static void nps400_irq_eoi(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+}
+
+static struct irq_chip nps400_irq_chip_fasteoi = {
+ .name = "NPS400 IC Global",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi_global,
+};
+
+static struct irq_chip nps400_irq_chip_percpu = {
+ .name = "NPS400 IC",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi,
+};
+
+static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ switch (hw) {
+ case NPS_TIMER0_IRQ:
+#ifdef CONFIG_SMP
+ case IPI_IRQ:
+#endif
+ irq_set_percpu_devid(virq);
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
+ handle_percpu_devid_irq);
+ break;
+ default:
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
+ handle_fasteoi_irq);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops nps400_irq_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = nps400_irq_map,
+};
+
+static int __init nps400_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ static struct irq_domain *nps400_root_domain;
+
+ if (parent) {
+ pr_err("DeviceTree incore ic not a root irq controller\n");
+ return -EINVAL;
+ }
+
+ nps400_root_domain = irq_domain_add_linear(node, NPS_NR_CPU_IRQS,
+ &nps400_irq_ops, NULL);
+
+ if (!nps400_root_domain) {
+ pr_err("nps400 root irq domain not avail\n");
+ return -ENOMEM;
+ }
+
+ /*
+ * Needed for primary domain lookup to succeed
+ * This is a primary irqchip, and can never have a parent
+ */
+ irq_set_default_host(nps400_root_domain);
+
+#ifdef CONFIG_SMP
+ irq_create_mapping(nps400_root_domain, IPI_IRQ);
+#endif
+
+ return 0;
+}
+IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v5 3/3] irqchip: add nps Internal and external irqchips
@ 2016-02-11 18:40 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 18:40 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noam Camus <noamc at ezchip.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier at arm.com>
---
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 149 ++++++++++++++++++++
4 files changed, 173 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 drivers/irqchip/irq-eznps.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 0000000..888b2b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "ezchip,nps400-ic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+ bool "NPS400 Global Interrupt Manager (GIM)"
+ select IRQ_DOMAIN
+ help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 0000000..9decd7d
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <soc/nps/common.h>
+
+#define NPS_NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
+#define NPS_TIMER0_IRQ 3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb &= ~(1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb |= (1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+ /* Don't ack GIC before all device access attempts are done */
+ mb();
+
+ nps_ack_gic();
+}
+
+static void nps400_irq_eoi(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+}
+
+static struct irq_chip nps400_irq_chip_fasteoi = {
+ .name = "NPS400 IC Global",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi_global,
+};
+
+static struct irq_chip nps400_irq_chip_percpu = {
+ .name = "NPS400 IC",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi,
+};
+
+static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ switch (hw) {
+ case NPS_TIMER0_IRQ:
+#ifdef CONFIG_SMP
+ case IPI_IRQ:
+#endif
+ irq_set_percpu_devid(virq);
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
+ handle_percpu_devid_irq);
+ break;
+ default:
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
+ handle_fasteoi_irq);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops nps400_irq_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = nps400_irq_map,
+};
+
+static int __init nps400_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ static struct irq_domain *nps400_root_domain;
+
+ if (parent) {
+ pr_err("DeviceTree incore ic not a root irq controller\n");
+ return -EINVAL;
+ }
+
+ nps400_root_domain = irq_domain_add_linear(node, NPS_NR_CPU_IRQS,
+ &nps400_irq_ops, NULL);
+
+ if (!nps400_root_domain) {
+ pr_err("nps400 root irq domain not avail\n");
+ return -ENOMEM;
+ }
+
+ /*
+ * Needed for primary domain lookup to succeed
+ * This is a primary irqchip, and can never have a parent
+ */
+ irq_set_default_host(nps400_root_domain);
+
+#ifdef CONFIG_SMP
+ irq_create_mapping(nps400_root_domain, IPI_IRQ);
+#endif
+
+ return 0;
+}
+IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH v5 3/3] irqchip: add nps Internal and external irqchips
2016-02-11 18:40 ` Noam Camus
@ 2016-02-19 14:03 ` Jason Cooper
-1 siblings, 0 replies; 60+ messages in thread
From: Jason Cooper @ 2016-02-19 14:03 UTC (permalink / raw)
To: Noam Camus
Cc: linux-kernel, linux-snps-arc, daniel.lezcano, marc.zyngier,
cmetcalf, talz, giladb, Thomas Gleixner
Hey Noam,
Could you please re-send and attach a changelog:
On Thu, Feb 11, 2016 at 08:40:59PM +0200, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> Adding EZchip NPS400 support.
> NPS internal interrupts are internally handled at
> Multi Thread Manager (MTM) that is signaled for deactivating
> an interrupt.
> External interrupts is handled also at Global Interrupt
> Controller (GIC) e.g. serial and network devices.
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> ---
* here?
> .../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
> drivers/irqchip/Kconfig | 6 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-eznps.c | 149 ++++++++++++++++++++
> 4 files changed, 173 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
> create mode 100644 drivers/irqchip/irq-eznps.c
Thanks, it greatly assists review. If you need an example, please take
a look at the patch submitted this morning by Thomas Petazzoni [1].
thx,
Jason.
[1] https://lkml.kernel.org/r/1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v5 3/3] irqchip: add nps Internal and external irqchips
@ 2016-02-19 14:03 ` Jason Cooper
0 siblings, 0 replies; 60+ messages in thread
From: Jason Cooper @ 2016-02-19 14:03 UTC (permalink / raw)
To: linux-snps-arc
Hey Noam,
Could you please re-send and attach a changelog:
On Thu, Feb 11, 2016@08:40:59PM +0200, Noam Camus wrote:
> From: Noam Camus <noamc at ezchip.com>
>
> Adding EZchip NPS400 support.
> NPS internal interrupts are internally handled at
> Multi Thread Manager (MTM) that is signaled for deactivating
> an interrupt.
> External interrupts is handled also at Global Interrupt
> Controller (GIC) e.g. serial and network devices.
>
> Signed-off-by: Noam Camus <noamc at ezchip.com>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Marc Zyngier <marc.zyngier at arm.com>
> ---
* here?
> .../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
> drivers/irqchip/Kconfig | 6 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-eznps.c | 149 ++++++++++++++++++++
> 4 files changed, 173 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
> create mode 100644 drivers/irqchip/irq-eznps.c
Thanks, it greatly assists review. If you need an example, please take
a look at the patch submitted this morning by Thomas Petazzoni [1].
thx,
Jason.
[1] https://lkml.kernel.org/r/1455888883-5127-1-git-send-email-thomas.petazzoni at free-electrons.com
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v5 3/3] irqchip: add nps Internal and external irqchips
2016-02-19 14:03 ` Jason Cooper
@ 2016-02-19 14:42 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-19 14:42 UTC (permalink / raw)
To: Jason Cooper
Cc: linux-kernel, linux-snps-arc, daniel.lezcano, marc.zyngier,
Chris Metcalf, Tal Zilcer, Gilad Ben Yossef, Thomas Gleixner
Hi Jason,
The patch set got change log, see cover letter that summarize all changes with respect to whole set.
https://lkml.org/lkml/2016/2/11/609
Let me know if it works for you.
Noam
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v4 1/3] soc: Support for EZchip SoC
2016-02-06 16:16 ` Noam Camus
@ 2016-02-11 3:02 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 3:02 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus
From: Noam Camus <noamc@ezchip.com>
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus <noamc@ezchip.com>
---
include/soc/nps/common.h | 150 ++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 150 insertions(+), 0 deletions(-)
create mode 100644 include/soc/nps/common.h
diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 0000000..35ebb00
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ 5
+#endif
+
+#define NPS_HOST_REG_BASE 0xF6000000
+
+#define NPS_MSU_BLKID 0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+ __asm__ __volatile__ (
+ " .word %0\n"
+ :
+ : "i"(CTOP_INST_RSPI_GIC_0_R12)
+ : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+ union {
+ struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+ u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+ u32 __reserved:24, cluster:4, core:4;
+#endif
+ };
+ u32 value;
+ };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ * ----------------- ------------------
+ * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)|
+ *
+ * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)|
+ * ----------------- ------------------
+ * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)|
+ *
+ * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)|
+ * ----------------- ------------------
+ * 0 1 2 3
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+ __asm__ __volatile__(
+ " mov r3,%0\n"
+ " .short %1\n"
+ " .word %2\n"
+ " mov %0,r3\n"
+ : "+r"(cluster)
+ : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+ : "r3");
+#endif
+
+ return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+ ({ struct global_id gid; gid.value = cpu; \
+ nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+ union {
+ struct {
+ u32 base:8, cl_x:4, cl_y:4,
+ blkid:6, reg:8, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+struct nps_host_reg_address_non_cl {
+ union {
+ struct {
+ u32 base:7, blkid:11, reg:12, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address_non_cl reg_address;
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address reg_address;
+ u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.cl_x = (cl >> 2) & 0x3;
+ reg_address.cl_y = cl & 0x3;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* SOC_NPS_COMMON_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v4 1/3] soc: Support for EZchip SoC
@ 2016-02-11 3:02 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 3:02 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus <noamc at ezchip.com>
---
include/soc/nps/common.h | 150 ++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 150 insertions(+), 0 deletions(-)
create mode 100644 include/soc/nps/common.h
diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 0000000..35ebb00
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ 5
+#endif
+
+#define NPS_HOST_REG_BASE 0xF6000000
+
+#define NPS_MSU_BLKID 0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+ __asm__ __volatile__ (
+ " .word %0\n"
+ :
+ : "i"(CTOP_INST_RSPI_GIC_0_R12)
+ : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+ union {
+ struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+ u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+ u32 __reserved:24, cluster:4, core:4;
+#endif
+ };
+ u32 value;
+ };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ * ----------------- ------------------
+ * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)|
+ *
+ * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)|
+ * ----------------- ------------------
+ * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)|
+ *
+ * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)|
+ * ----------------- ------------------
+ * 0 1 2 3
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+ __asm__ __volatile__(
+ " mov r3,%0\n"
+ " .short %1\n"
+ " .word %2\n"
+ " mov %0,r3\n"
+ : "+r"(cluster)
+ : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+ : "r3");
+#endif
+
+ return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+ ({ struct global_id gid; gid.value = cpu; \
+ nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+ union {
+ struct {
+ u32 base:8, cl_x:4, cl_y:4,
+ blkid:6, reg:8, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+struct nps_host_reg_address_non_cl {
+ union {
+ struct {
+ u32 base:7, blkid:11, reg:12, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address_non_cl reg_address;
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address reg_address;
+ u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.cl_x = (cl >> 2) & 0x3;
+ reg_address.cl_y = cl & 0x3;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* SOC_NPS_COMMON_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v4 2/3] clocksource: Add NPS400 timers driver
2016-02-06 16:16 ` Noam Camus
@ 2016-02-11 3:02 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 3:02 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus, Rob Herring, Thomas Gleixner, John Stultz
From: Noam Camus <noamc@ezchip.com>
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: John Stultz <john.stultz@linaro.org>
Acked-by: Vineet Gupta <vgupta@synopsys.com>
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++++
drivers/clocksource/Kconfig | 10 +++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 80 ++++++++++++++++++++
4 files changed, 106 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 0000000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..fa7be50 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,16 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
+config CLKSRC_NPS
+ bool "NPS400 clocksource driver" if COMPILE_TEST
+ depends on !PHYS_ADDR_T_64BIT
+ select CLKSRC_MMIO
+ select CLKSRC_OF if OF
+ help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+ This counter is accessed via couple of 32 bit memory mapped registers.
+
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 0000000..5a15970
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/cpu.h>
+#include <soc/nps/common.h>
+
+#define NPS_MSU_TICK_LOW 0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM 16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+ int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+ return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static void __init nps_setup_clocksource(struct device_node *node,
+ struct clk *clk)
+{
+ int ret, cluster;
+
+ for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+ nps_msu_reg_low_addr[cluster] =
+ nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+ NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ pr_err("Couldn't enable parent clock\n");
+ return;
+ }
+
+ nps_timer_rate = clk_get_rate(clk);
+
+ ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
+ nps_timer_rate, 301, 32, nps_clksrc_read);
+ if (ret) {
+ pr_err("Couldn't register clock source.\n");
+ clk_disable_unprepare(clk);
+ }
+}
+
+static void __init nps_timer_init(struct device_node *node)
+{
+ struct clk *clk;
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk))
+ panic("Can't get timer clock");
+
+ nps_setup_clocksource(node, clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
+ nps_timer_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v4 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-11 3:02 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 3:02 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus <noamc at ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
Cc: Rob Herring <robh+dt at kernel.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: John Stultz <john.stultz at linaro.org>
Acked-by: Vineet Gupta <vgupta at synopsys.com>
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++++
drivers/clocksource/Kconfig | 10 +++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 80 ++++++++++++++++++++
4 files changed, 106 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 0000000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..fa7be50 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,16 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
+config CLKSRC_NPS
+ bool "NPS400 clocksource driver" if COMPILE_TEST
+ depends on !PHYS_ADDR_T_64BIT
+ select CLKSRC_MMIO
+ select CLKSRC_OF if OF
+ help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+ This counter is accessed via couple of 32 bit memory mapped registers.
+
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 0000000..5a15970
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/cpu.h>
+#include <soc/nps/common.h>
+
+#define NPS_MSU_TICK_LOW 0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM 16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+ int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+ return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static void __init nps_setup_clocksource(struct device_node *node,
+ struct clk *clk)
+{
+ int ret, cluster;
+
+ for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+ nps_msu_reg_low_addr[cluster] =
+ nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+ NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ pr_err("Couldn't enable parent clock\n");
+ return;
+ }
+
+ nps_timer_rate = clk_get_rate(clk);
+
+ ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
+ nps_timer_rate, 301, 32, nps_clksrc_read);
+ if (ret) {
+ pr_err("Couldn't register clock source.\n");
+ clk_disable_unprepare(clk);
+ }
+}
+
+static void __init nps_timer_init(struct device_node *node)
+{
+ struct clk *clk;
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk))
+ panic("Can't get timer clock");
+
+ nps_setup_clocksource(node, clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
+ nps_timer_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH v4 2/3] clocksource: Add NPS400 timers driver
2016-02-11 3:02 ` Noam Camus
@ 2016-02-11 8:18 ` Daniel Lezcano
-1 siblings, 0 replies; 60+ messages in thread
From: Daniel Lezcano @ 2016-02-11 8:18 UTC (permalink / raw)
To: Noam Camus, linux-kernel
Cc: linux-snps-arc, marc.zyngier, cmetcalf, talz, giladb,
Rob Herring, Thomas Gleixner, John Stultz
On 02/11/2016 04:02 AM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> Add internal tick generator which is shared by all cores.
> Each cluster of cores view it through dedicated address.
> This is used for SMP system where all CPUs synced by same
> clock source.
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: John Stultz <john.stultz@linaro.org>
> Acked-by: Vineet Gupta <vgupta@synopsys.com>
> ---
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
but ...
[ ... ]
> + clk = of_clk_get(node, 0);
> + if (IS_ERR(clk))
> + panic("Can't get timer clock");
^^^^^^
I failed to see that at in the previous review.
Thanks
-- Daniel
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 60+ messages in thread* [PATCH v4 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-11 8:18 ` Daniel Lezcano
0 siblings, 0 replies; 60+ messages in thread
From: Daniel Lezcano @ 2016-02-11 8:18 UTC (permalink / raw)
To: linux-snps-arc
On 02/11/2016 04:02 AM, Noam Camus wrote:
> From: Noam Camus <noamc at ezchip.com>
>
> Add internal tick generator which is shared by all cores.
> Each cluster of cores view it through dedicated address.
> This is used for SMP system where all CPUs synced by same
> clock source.
>
> Signed-off-by: Noam Camus <noamc at ezchip.com>
> Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
> Cc: Rob Herring <robh+dt at kernel.org>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: John Stultz <john.stultz at linaro.org>
> Acked-by: Vineet Gupta <vgupta at synopsys.com>
> ---
Acked-by: Daniel Lezcano <daniel.lezcano at linaro.org>
but ...
[ ... ]
> + clk = of_clk_get(node, 0);
> + if (IS_ERR(clk))
> + panic("Can't get timer clock");
^^^^^^
I failed to see that at in the previous review.
Thanks
-- Daniel
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v4 3/3] irqchip: add nps Internal and external irqchips
2016-02-06 16:16 ` Noam Camus
@ 2016-02-11 3:02 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 3:02 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus, Thomas Gleixner, Jason Cooper
From: Noam Camus <noamc@ezchip.com>
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
---
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 145 ++++++++++++++++++++
4 files changed, 169 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 drivers/irqchip/irq-eznps.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 0000000..888b2b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "ezchip,nps400-ic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+ bool "NPS400 Global Interrupt Manager (GIM)"
+ select IRQ_DOMAIN
+ help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 0000000..acc55a3
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <soc/nps/common.h>
+
+#define NPS_NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
+#define NPS_TIMER0_IRQ 3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb &= ~(1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb |= (1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+ /* Don't ack GIC before all device access attempts are done */
+ mb();
+
+ nps_ack_gic();
+}
+
+static void nps400_irq_eoi(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+}
+
+static struct irq_chip nps400_irq_chip_fasteoi = {
+ .name = "NPS400 IC Global",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi_global,
+};
+
+static struct irq_chip nps400_irq_chip_percpu = {
+ .name = "NPS400 IC",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi,
+};
+
+static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ switch (hw) {
+ case NPS_TIMER0_IRQ:
+#ifdef CONFIG_SMP
+ case IPI_IRQ:
+#endif
+ irq_set_percpu_devid(virq);
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
+ handle_percpu_devid_irq);
+ break;
+ default:
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
+ handle_fasteoi_irq);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops nps400_irq_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = nps400_irq_map,
+};
+
+static int __init nps400_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ static struct irq_domain *nps400_root_domain;
+
+ if (parent)
+ panic("DeviceTree incore ic not a root irq controller\n");
+
+ nps400_root_domain = irq_domain_add_linear(node, NPS_NR_CPU_IRQS,
+ &nps400_irq_ops, NULL);
+
+ if (!nps400_root_domain)
+ panic("nps400 root irq domain not avail\n");
+
+ /*
+ * Needed for primary domain lookup to succeed
+ * This is a primary irqchip, and can never have a parent
+ */
+ irq_set_default_host(nps400_root_domain);
+
+#ifdef CONFIG_SMP
+ irq_create_mapping(nps400_root_domain, IPI_IRQ);
+#endif
+
+ return 0;
+}
+IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v4 3/3] irqchip: add nps Internal and external irqchips
@ 2016-02-11 3:02 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-11 3:02 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noam Camus <noamc at ezchip.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier at arm.com>
---
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 145 ++++++++++++++++++++
4 files changed, 169 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 drivers/irqchip/irq-eznps.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 0000000..888b2b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "ezchip,nps400-ic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+ bool "NPS400 Global Interrupt Manager (GIM)"
+ select IRQ_DOMAIN
+ help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 0000000..acc55a3
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <soc/nps/common.h>
+
+#define NPS_NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
+#define NPS_TIMER0_IRQ 3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb &= ~(1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb |= (1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+ /* Don't ack GIC before all device access attempts are done */
+ mb();
+
+ nps_ack_gic();
+}
+
+static void nps400_irq_eoi(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+}
+
+static struct irq_chip nps400_irq_chip_fasteoi = {
+ .name = "NPS400 IC Global",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi_global,
+};
+
+static struct irq_chip nps400_irq_chip_percpu = {
+ .name = "NPS400 IC",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi,
+};
+
+static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ switch (hw) {
+ case NPS_TIMER0_IRQ:
+#ifdef CONFIG_SMP
+ case IPI_IRQ:
+#endif
+ irq_set_percpu_devid(virq);
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
+ handle_percpu_devid_irq);
+ break;
+ default:
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
+ handle_fasteoi_irq);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops nps400_irq_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = nps400_irq_map,
+};
+
+static int __init nps400_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ static struct irq_domain *nps400_root_domain;
+
+ if (parent)
+ panic("DeviceTree incore ic not a root irq controller\n");
+
+ nps400_root_domain = irq_domain_add_linear(node, NPS_NR_CPU_IRQS,
+ &nps400_irq_ops, NULL);
+
+ if (!nps400_root_domain)
+ panic("nps400 root irq domain not avail\n");
+
+ /*
+ * Needed for primary domain lookup to succeed
+ * This is a primary irqchip, and can never have a parent
+ */
+ irq_set_default_host(nps400_root_domain);
+
+#ifdef CONFIG_SMP
+ irq_create_mapping(nps400_root_domain, IPI_IRQ);
+#endif
+
+ return 0;
+}
+IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 1/3] soc: Support for EZchip SoC
2016-02-02 13:14 ` Noam Camus
@ 2016-02-06 16:16 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-06 16:16 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus
From: Noam Camus <noamc@ezchip.com>
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus <noamc@ezchip.com>
---
include/soc/nps/common.h | 150 ++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 150 insertions(+), 0 deletions(-)
create mode 100644 include/soc/nps/common.h
diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 0000000..35ebb00
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ 5
+#endif
+
+#define NPS_HOST_REG_BASE 0xF6000000
+
+#define NPS_MSU_BLKID 0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+ __asm__ __volatile__ (
+ " .word %0\n"
+ :
+ : "i"(CTOP_INST_RSPI_GIC_0_R12)
+ : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+ union {
+ struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+ u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+ u32 __reserved:24, cluster:4, core:4;
+#endif
+ };
+ u32 value;
+ };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ * ----------------- ------------------
+ * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)|
+ *
+ * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)|
+ * ----------------- ------------------
+ * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)|
+ *
+ * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)|
+ * ----------------- ------------------
+ * 0 1 2 3
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+ __asm__ __volatile__(
+ " mov r3,%0\n"
+ " .short %1\n"
+ " .word %2\n"
+ " mov %0,r3\n"
+ : "+r"(cluster)
+ : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+ : "r3");
+#endif
+
+ return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+ ({ struct global_id gid; gid.value = cpu; \
+ nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+ union {
+ struct {
+ u32 base:8, cl_x:4, cl_y:4,
+ blkid:6, reg:8, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+struct nps_host_reg_address_non_cl {
+ union {
+ struct {
+ u32 base:7, blkid:11, reg:12, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address_non_cl reg_address;
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address reg_address;
+ u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.cl_x = (cl >> 2) & 0x3;
+ reg_address.cl_y = cl & 0x3;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* SOC_NPS_COMMON_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 1/3] soc: Support for EZchip SoC
@ 2016-02-06 16:16 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-06 16:16 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus <noamc at ezchip.com>
---
include/soc/nps/common.h | 150 ++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 150 insertions(+), 0 deletions(-)
create mode 100644 include/soc/nps/common.h
diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 0000000..35ebb00
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ 5
+#endif
+
+#define NPS_HOST_REG_BASE 0xF6000000
+
+#define NPS_MSU_BLKID 0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+ __asm__ __volatile__ (
+ " .word %0\n"
+ :
+ : "i"(CTOP_INST_RSPI_GIC_0_R12)
+ : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+ union {
+ struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+ u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+ u32 __reserved:24, cluster:4, core:4;
+#endif
+ };
+ u32 value;
+ };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ * ----------------- ------------------
+ * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)|
+ *
+ * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)|
+ * ----------------- ------------------
+ * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)|
+ *
+ * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)|
+ * ----------------- ------------------
+ * 0 1 2 3
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+ __asm__ __volatile__(
+ " mov r3,%0\n"
+ " .short %1\n"
+ " .word %2\n"
+ " mov %0,r3\n"
+ : "+r"(cluster)
+ : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+ : "r3");
+#endif
+
+ return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+ ({ struct global_id gid; gid.value = cpu; \
+ nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+ union {
+ struct {
+ u32 base:8, cl_x:4, cl_y:4,
+ blkid:6, reg:8, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+struct nps_host_reg_address_non_cl {
+ union {
+ struct {
+ u32 base:7, blkid:11, reg:12, __reserved:2;
+ };
+ u32 value;
+ };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address_non_cl reg_address;
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+ struct nps_host_reg_address reg_address;
+ u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+ reg_address.value = NPS_HOST_REG_BASE;
+ reg_address.cl_x = (cl >> 2) & 0x3;
+ reg_address.cl_y = cl & 0x3;
+ reg_address.blkid = blkid;
+ reg_address.reg = reg;
+
+ return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* SOC_NPS_COMMON_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v3 2/3] clocksource: Add NPS400 timers driver
2016-02-02 13:14 ` Noam Camus
@ 2016-02-06 16:16 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-06 16:16 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus, Rob Herring, Thomas Gleixner, John Stultz
From: Noam Camus <noamc@ezchip.com>
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: John Stultz <john.stultz@linaro.org>
Acked-by: Vineet Gupta <vgupta@synopsys.com>
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++++
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 84 ++++++++++++++++++++
4 files changed, 109 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 0000000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..0d0ba91 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,15 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
+config CLKSRC_NPS
+ bool "NPS400 clocksource driver" if COMPILE_TEST
+ depends on !PHYS_ADDR_T_64BIT
+ select CLKSRC_OF if OF
+ help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+ This counter is accessed via couple of 32 bit memory mapped registers.
+
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 0000000..bf9a490
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/cpu.h>
+#include <soc/nps/common.h>
+
+#define NPS_MSU_TICK_LOW 0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM 16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+ int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+ return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static struct clocksource nps_counter = {
+ .name = "EZnps-tick",
+ .rating = 301,
+ .read = nps_clksrc_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init nps_setup_clocksource(struct device_node *node,
+ struct clk *clk)
+{
+ struct clocksource *clksrc = &nps_counter;
+ int ret, cluster;
+
+ for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+ nps_msu_reg_low_addr[cluster] =
+ nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+ NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ pr_err("Couldn't enable parent clock\n");
+
+ nps_timer_rate = clk_get_rate(clk);
+
+ ret = clocksource_register_hz(clksrc, nps_timer_rate);
+ if (ret)
+ pr_err("Couldn't register clock source.\n");
+}
+
+static void __init nps_timer_init(struct device_node *node)
+{
+ struct clk *clk;
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk))
+ panic("Can't get timer clock");
+
+ nps_setup_clocksource(node, clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
+ nps_timer_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-06 16:16 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-06 16:16 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus <noamc at ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
Cc: Rob Herring <robh+dt at kernel.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: John Stultz <john.stultz at linaro.org>
Acked-by: Vineet Gupta <vgupta at synopsys.com>
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 ++++
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-nps.c | 84 ++++++++++++++++++++
4 files changed, 109 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 0000000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..0d0ba91 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,15 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
+config CLKSRC_NPS
+ bool "NPS400 clocksource driver" if COMPILE_TEST
+ depends on !PHYS_ADDR_T_64BIT
+ select CLKSRC_OF if OF
+ help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+ This counter is accessed via couple of 32 bit memory mapped registers.
+
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 0000000..bf9a490
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/cpu.h>
+#include <soc/nps/common.h>
+
+#define NPS_MSU_TICK_LOW 0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM 16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+ int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+ return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static struct clocksource nps_counter = {
+ .name = "EZnps-tick",
+ .rating = 301,
+ .read = nps_clksrc_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init nps_setup_clocksource(struct device_node *node,
+ struct clk *clk)
+{
+ struct clocksource *clksrc = &nps_counter;
+ int ret, cluster;
+
+ for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+ nps_msu_reg_low_addr[cluster] =
+ nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+ NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ pr_err("Couldn't enable parent clock\n");
+
+ nps_timer_rate = clk_get_rate(clk);
+
+ ret = clocksource_register_hz(clksrc, nps_timer_rate);
+ if (ret)
+ pr_err("Couldn't register clock source.\n");
+}
+
+static void __init nps_timer_init(struct device_node *node)
+{
+ struct clk *clk;
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk))
+ panic("Can't get timer clock");
+
+ nps_setup_clocksource(node, clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
+ nps_timer_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH v3 2/3] clocksource: Add NPS400 timers driver
2016-02-06 16:16 ` Noam Camus
@ 2016-02-08 14:21 ` Daniel Lezcano
-1 siblings, 0 replies; 60+ messages in thread
From: Daniel Lezcano @ 2016-02-08 14:21 UTC (permalink / raw)
To: Noam Camus, linux-kernel
Cc: linux-snps-arc, marc.zyngier, cmetcalf, talz, giladb,
Rob Herring, Thomas Gleixner, John Stultz
On 02/06/2016 05:16 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> Add internal tick generator which is shared by all cores.
> Each cluster of cores view it through dedicated address.
> This is used for SMP system where all CPUs synced by same
> clock source.
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: John Stultz <john.stultz@linaro.org>
> Acked-by: Vineet Gupta <vgupta@synopsys.com>
> ---
[ ... ]
> +static cycle_t nps_clksrc_read(struct clocksource *clksrc)
> +{
> + int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
> +
> + return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
> +}
> +
> +static struct clocksource nps_counter = {
> + .name = "EZnps-tick",
> + .rating = 301,
> + .read = nps_clksrc_read,
> + .mask = CLOCKSOURCE_MASK(32),
> + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> +};
> +
> +static void __init nps_setup_clocksource(struct device_node *node,
> + struct clk *clk)
> +{
> + struct clocksource *clksrc = &nps_counter;
> + int ret, cluster;
> +
> + for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
> + nps_msu_reg_low_addr[cluster] =
> + nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
> + NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
> +
> + ret = clk_prepare_enable(clk);
> + if (ret)
> + pr_err("Couldn't enable parent clock\n");
> +
> + nps_timer_rate = clk_get_rate(clk);
If there is an error, you continue the execution of the code. I guess
you expect the system to hang in any case with the error in the console,
right ?
> + ret = clocksource_register_hz(clksrc, nps_timer_rate);
You can simplify the driver even more by using clocksource_mmio_init.
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
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<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 60+ messages in thread* [PATCH v3 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-08 14:21 ` Daniel Lezcano
0 siblings, 0 replies; 60+ messages in thread
From: Daniel Lezcano @ 2016-02-08 14:21 UTC (permalink / raw)
To: linux-snps-arc
On 02/06/2016 05:16 PM, Noam Camus wrote:
> From: Noam Camus <noamc at ezchip.com>
>
> Add internal tick generator which is shared by all cores.
> Each cluster of cores view it through dedicated address.
> This is used for SMP system where all CPUs synced by same
> clock source.
>
> Signed-off-by: Noam Camus <noamc at ezchip.com>
> Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
> Cc: Rob Herring <robh+dt at kernel.org>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: John Stultz <john.stultz at linaro.org>
> Acked-by: Vineet Gupta <vgupta at synopsys.com>
> ---
[ ... ]
> +static cycle_t nps_clksrc_read(struct clocksource *clksrc)
> +{
> + int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
> +
> + return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
> +}
> +
> +static struct clocksource nps_counter = {
> + .name = "EZnps-tick",
> + .rating = 301,
> + .read = nps_clksrc_read,
> + .mask = CLOCKSOURCE_MASK(32),
> + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> +};
> +
> +static void __init nps_setup_clocksource(struct device_node *node,
> + struct clk *clk)
> +{
> + struct clocksource *clksrc = &nps_counter;
> + int ret, cluster;
> +
> + for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
> + nps_msu_reg_low_addr[cluster] =
> + nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
> + NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
> +
> + ret = clk_prepare_enable(clk);
> + if (ret)
> + pr_err("Couldn't enable parent clock\n");
> +
> + nps_timer_rate = clk_get_rate(clk);
If there is an error, you continue the execution of the code. I guess
you expect the system to hang in any case with the error in the console,
right ?
> + ret = clocksource_register_hz(clksrc, nps_timer_rate);
You can simplify the driver even more by using clocksource_mmio_init.
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 60+ messages in thread* RE: [PATCH v3 2/3] clocksource: Add NPS400 timers driver
2016-02-08 14:21 ` Daniel Lezcano
@ 2016-02-09 12:36 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-09 12:36 UTC (permalink / raw)
To: Daniel Lezcano, linux-kernel
Cc: linux-snps-arc, marc.zyngier, Chris Metcalf, Tal Zilcer,
Gilad Ben Yossef, Rob Herring, Thomas Gleixner, John Stultz
>From: Daniel Lezcano [mailto:daniel.lezcano@linaro.org]
>Sent: Monday, February 08, 2016 4:22 PM
>> + ret = clk_prepare_enable(clk);
>> + if (ret)
>> + pr_err("Couldn't enable parent clock\n");
>> +
>> + nps_timer_rate = clk_get_rate(clk);
>If there is an error, you continue the execution of the code. I guess you expect the system to hang in any case with the error in the >console, right ?
Since our clock is root then returned value will always be valid.
I am far from being expert here, but no one checks for clk_get_rate() return value for error.
Could you refer to a single place at clocksource drivers that checks for error in the return value.
>> + ret = clocksource_register_hz(clksrc, nps_timer_rate);
>You can simplify the driver even more by using clocksource_mmio_init.
Since my base address depends on cluster number, which CPU is part of, this interface is not much of a use. On top of that it assumes that I am little endian by using readl family accessories.
-Noam
^ permalink raw reply [flat|nested] 60+ messages in thread* [PATCH v3 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-09 12:36 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-09 12:36 UTC (permalink / raw)
To: linux-snps-arc
>From: Daniel Lezcano [mailto:daniel.lezcano at linaro.org]
>Sent: Monday, February 08, 2016 4:22 PM
>> + ret = clk_prepare_enable(clk);
>> + if (ret)
>> + pr_err("Couldn't enable parent clock\n");
>> +
>> + nps_timer_rate = clk_get_rate(clk);
>If there is an error, you continue the execution of the code. I guess you expect the system to hang in any case with the error in the >console, right ?
Since our clock is root then returned value will always be valid.
I am far from being expert here, but no one checks for clk_get_rate() return value for error.
Could you refer to a single place at clocksource drivers that checks for error in the return value.
>> + ret = clocksource_register_hz(clksrc, nps_timer_rate);
>You can simplify the driver even more by using clocksource_mmio_init.
Since my base address depends on cluster number, which CPU is part of, this interface is not much of a use. On top of that it assumes that I am little endian by using readl family accessories.
-Noam
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 2/3] clocksource: Add NPS400 timers driver
2016-02-09 12:36 ` Noam Camus
@ 2016-02-09 13:38 ` Daniel Lezcano
-1 siblings, 0 replies; 60+ messages in thread
From: Daniel Lezcano @ 2016-02-09 13:38 UTC (permalink / raw)
To: Noam Camus, linux-kernel
Cc: linux-snps-arc, marc.zyngier, Chris Metcalf, Tal Zilcer,
Gilad Ben Yossef, Rob Herring, Thomas Gleixner, John Stultz
On 02/09/2016 01:36 PM, Noam Camus wrote:
>> From: Daniel Lezcano [mailto:daniel.lezcano@linaro.org] Sent:
>> Monday, February 08, 2016 4:22 PM
>
>>> + ret = clk_prepare_enable(clk); + if (ret) + pr_err("Couldn't
>>> enable parent clock\n"); + + nps_timer_rate = clk_get_rate(clk);
>
>> If there is an error, you continue the execution of the code. I
>> guess you expect the system to hang in any case with the error in
>> the >console, right ?
>
> Since our clock is root then returned value will always be valid. I
> am far from being expert here, but no one checks for clk_get_rate()
> return value for error. Could you refer to a single place at
> clocksource drivers that checks for error in the return value.
Actually I was referring to clk_prepare_enable, clocksource_register_hz.
Agree clk_get_rate is always valid.
>>> + ret = clocksource_register_hz(clksrc, nps_timer_rate);
>
>> You can simplify the driver even more by using
>> clocksource_mmio_init.
> Since my base address depends on cluster number, which CPU is part
> of, this interface is not much of a use. On top of that it assumes
> that I am little endian by using readl family accessories.
Why can't you use ?
clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
nps_timer_rate, 32, nps_clksrc_read);
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 60+ messages in thread* [PATCH v3 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-09 13:38 ` Daniel Lezcano
0 siblings, 0 replies; 60+ messages in thread
From: Daniel Lezcano @ 2016-02-09 13:38 UTC (permalink / raw)
To: linux-snps-arc
On 02/09/2016 01:36 PM, Noam Camus wrote:
>> From: Daniel Lezcano [mailto:daniel.lezcano at linaro.org] Sent:
>> Monday, February 08, 2016 4:22 PM
>
>>> + ret = clk_prepare_enable(clk); + if (ret) + pr_err("Couldn't
>>> enable parent clock\n"); + + nps_timer_rate = clk_get_rate(clk);
>
>> If there is an error, you continue the execution of the code. I
>> guess you expect the system to hang in any case with the error in
>> the >console, right ?
>
> Since our clock is root then returned value will always be valid. I
> am far from being expert here, but no one checks for clk_get_rate()
> return value for error. Could you refer to a single place at
> clocksource drivers that checks for error in the return value.
Actually I was referring to clk_prepare_enable, clocksource_register_hz.
Agree clk_get_rate is always valid.
>>> + ret = clocksource_register_hz(clksrc, nps_timer_rate);
>
>> You can simplify the driver even more by using
>> clocksource_mmio_init.
> Since my base address depends on cluster number, which CPU is part
> of, this interface is not much of a use. On top of that it assumes
> that I am little endian by using readl family accessories.
Why can't you use ?
clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
nps_timer_rate, 32, nps_clksrc_read);
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v3 2/3] clocksource: Add NPS400 timers driver
2016-02-09 13:38 ` Daniel Lezcano
@ 2016-02-09 21:47 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-09 21:47 UTC (permalink / raw)
To: Daniel Lezcano, linux-kernel
Cc: linux-snps-arc, marc.zyngier, Chris Metcalf, Tal Zilcer,
Gilad Ben Yossef, Rob Herring, Thomas Gleixner, John Stultz
>From: Daniel Lezcano <daniel.lezcano@linaro.org>
>Sent: Tuesday, February 9, 2016 3:38 PM
>Actually I was referring to clk_prepare_enable, clocksource_register_hz.
>Agree clk_get_rate is always valid.
Thanks for making this clear.
Any way as you can see I do call pr_err() in case of error just like most drivers around.
By "hang" do you mean calling panic()?
What if there is another clocksource in DT (even with worse rating)?
I still prefer using it then having non workable machine.
>>
>>> You can simplify the driver even more by using
>>> clocksource_mmio_init.
>> Since my base address depends on cluster number, which CPU is part
>> of, this interface is not much of a use. On top of that it assumes
>> that I am little endian by using readl family accessories.
>Why can't you use ?
>clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
>nps_timer_rate, 32, nps_clksrc_read);
I believe that the simplification is meant for drivers that can actually use the clocksource_mmio..() accessories. Could you explain what is the advantage here, for my case, to use clocksource_mmio driver?
Thanks for your patience
-Noam
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v3 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-09 21:47 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-09 21:47 UTC (permalink / raw)
To: linux-snps-arc
>From: Daniel Lezcano <daniel.lezcano at linaro.org>
>Sent: Tuesday, February 9, 2016 3:38 PM
>Actually I was referring to clk_prepare_enable, clocksource_register_hz.
>Agree clk_get_rate is always valid.
Thanks for making this clear.
Any way as you can see I do call pr_err() in case of error just like most drivers around.
By "hang" do you mean calling panic()?
What if there is another clocksource in DT (even with worse rating)?
I still prefer using it then having non workable machine.
>>
>>> You can simplify the driver even more by using
>>> clocksource_mmio_init.
>> Since my base address depends on cluster number, which CPU is part
>> of, this interface is not much of a use. On top of that it assumes
>> that I am little endian by using readl family accessories.
>Why can't you use ?
>clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
>nps_timer_rate, 32, nps_clksrc_read);
I believe that the simplification is meant for drivers that can actually use the clocksource_mmio..() accessories. Could you explain what is the advantage here, for my case, to use clocksource_mmio driver?
Thanks for your patience
-Noam
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v3 2/3] clocksource: Add NPS400 timers driver
2016-02-09 21:47 ` Noam Camus
@ 2016-02-09 22:55 ` Daniel Lezcano
-1 siblings, 0 replies; 60+ messages in thread
From: Daniel Lezcano @ 2016-02-09 22:55 UTC (permalink / raw)
To: Noam Camus, linux-kernel
Cc: linux-snps-arc, marc.zyngier, Chris Metcalf, Tal Zilcer,
Gilad Ben Yossef, Rob Herring, Thomas Gleixner, John Stultz
On 02/09/2016 10:47 PM, Noam Camus wrote:
>> From: Daniel Lezcano <daniel.lezcano@linaro.org> Sent: Tuesday,
>> February 9, 2016 3:38 PM
>
>> Actually I was referring to clk_prepare_enable,
>> clocksource_register_hz. Agree clk_get_rate is always valid.
> Thanks for making this clear. Any way as you can see I do call
> pr_err() in case of error just like most drivers around. By "hang" do
> you mean calling panic()?
No. I meant the errors are caught but no action is taken, the execution
continues normally as nothing wrong happened. This is why I asked if you
expect the host to hang at boot time with the last error as a hint.
I was expecting to see a call to clk_disable_unprepare if
clocksource_register_hz fails, and returning 'ret' if clk_prepare_enable
fails.
> What if there is another clocksource in DT (even with worse rating)?
> I still prefer using it then having non workable machine.
You are right. This is why failing gracefully in the init function is
important.
>>>> You can simplify the driver even more by using
>>>> clocksource_mmio_init.
>>> Since my base address depends on cluster number, which CPU is
>>> part of, this interface is not much of a use. On top of that it
>>> assumes that I am little endian by using readl family
>>> accessories.
>
>> Why can't you use ?
>
>> clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
>> nps_timer_rate, 32, nps_clksrc_read);
>
> I believe that the simplification is meant for drivers that can
> actually use the clocksource_mmio..() accessories. Could you explain
> what is the advantage here, for my case, to use clocksource_mmio
> driver?
Using the mmio generic code will save:
+static struct clocksource nps_counter = {
+ .name = "EZnps-tick",
+ .rating = 301,
+ .read = nps_clksrc_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
Up to you.
-- Daniel
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 60+ messages in thread* [PATCH v3 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-09 22:55 ` Daniel Lezcano
0 siblings, 0 replies; 60+ messages in thread
From: Daniel Lezcano @ 2016-02-09 22:55 UTC (permalink / raw)
To: linux-snps-arc
On 02/09/2016 10:47 PM, Noam Camus wrote:
>> From: Daniel Lezcano <daniel.lezcano at linaro.org> Sent: Tuesday,
>> February 9, 2016 3:38 PM
>
>> Actually I was referring to clk_prepare_enable,
>> clocksource_register_hz. Agree clk_get_rate is always valid.
> Thanks for making this clear. Any way as you can see I do call
> pr_err() in case of error just like most drivers around. By "hang" do
> you mean calling panic()?
No. I meant the errors are caught but no action is taken, the execution
continues normally as nothing wrong happened. This is why I asked if you
expect the host to hang at boot time with the last error as a hint.
I was expecting to see a call to clk_disable_unprepare if
clocksource_register_hz fails, and returning 'ret' if clk_prepare_enable
fails.
> What if there is another clocksource in DT (even with worse rating)?
> I still prefer using it then having non workable machine.
You are right. This is why failing gracefully in the init function is
important.
>>>> You can simplify the driver even more by using
>>>> clocksource_mmio_init.
>>> Since my base address depends on cluster number, which CPU is
>>> part of, this interface is not much of a use. On top of that it
>>> assumes that I am little endian by using readl family
>>> accessories.
>
>> Why can't you use ?
>
>> clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
>> nps_timer_rate, 32, nps_clksrc_read);
>
> I believe that the simplification is meant for drivers that can
> actually use the clocksource_mmio..() accessories. Could you explain
> what is the advantage here, for my case, to use clocksource_mmio
> driver?
Using the mmio generic code will save:
+static struct clocksource nps_counter = {
+ .name = "EZnps-tick",
+ .rating = 301,
+ .read = nps_clksrc_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
Up to you.
-- Daniel
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 60+ messages in thread* RE: [PATCH v3 2/3] clocksource: Add NPS400 timers driver
2016-02-09 22:55 ` Daniel Lezcano
@ 2016-02-10 8:01 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-10 8:01 UTC (permalink / raw)
To: Daniel Lezcano, linux-kernel
Cc: linux-snps-arc, marc.zyngier, Chris Metcalf, Tal Zilcer,
Gilad Ben Yossef, Rob Herring, Thomas Gleixner, John Stultz
>From: Daniel Lezcano [mailto:daniel.lezcano@linaro.org]
>Sent: Wednesday, February 10, 2016 12:55 AM
>> pr_err() in case of error just like most drivers around. By "hang" do
>> you mean calling panic()?
>No. I meant the errors are caught but no action is taken, the execution continues normally as nothing wrong happened. This is why I asked if you expect the host to hang at boot time with the last error as a hint.
>I was expecting to see a call to clk_disable_unprepare if clocksource_register_hz fails, and returning 'ret' if clk_prepare_enable fails.
Ok, I will fix that, and handle gracefull return. Thanks
>Using the mmio generic code will save:
>+static struct clocksource nps_counter = {
>+ .name = "EZnps-tick",
>+ .rating = 301,
>+ .read = nps_clksrc_read,
>+ .mask = CLOCKSOURCE_MASK(32),
>+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
>+};
>Up to you.
I will do that, thanks again
Noam
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 60+ messages in thread* [PATCH v3 2/3] clocksource: Add NPS400 timers driver
@ 2016-02-10 8:01 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-10 8:01 UTC (permalink / raw)
To: linux-snps-arc
>From: Daniel Lezcano [mailto:daniel.lezcano at linaro.org]
>Sent: Wednesday, February 10, 2016 12:55 AM
>> pr_err() in case of error just like most drivers around. By "hang" do
>> you mean calling panic()?
>No. I meant the errors are caught but no action is taken, the execution continues normally as nothing wrong happened. This is why I asked if you expect the host to hang at boot time with the last error as a hint.
>I was expecting to see a call to clk_disable_unprepare if clocksource_register_hz fails, and returning 'ret' if clk_prepare_enable fails.
Ok, I will fix that, and handle gracefull return. Thanks
>Using the mmio generic code will save:
>+static struct clocksource nps_counter = {
>+ .name = "EZnps-tick",
>+ .rating = 301,
>+ .read = nps_clksrc_read,
>+ .mask = CLOCKSOURCE_MASK(32),
>+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
>+};
>Up to you.
I will do that, thanks again
Noam
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v3 3/3] irqchip: add nps Internal and external irqchips
2016-02-02 13:14 ` Noam Camus
@ 2016-02-06 16:16 ` Noam Camus
-1 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-06 16:16 UTC (permalink / raw)
To: linux-kernel
Cc: linux-snps-arc, daniel.lezcano, marc.zyngier, cmetcalf, talz,
giladb, Noam Camus, Thomas Gleixner, Jason Cooper
From: Noam Camus <noamc@ezchip.com>
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
---
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 145 ++++++++++++++++++++
4 files changed, 169 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 drivers/irqchip/irq-eznps.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 0000000..888b2b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "ezchip,nps400-ic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+ bool "NPS400 Global Interrupt Manager (GIM)"
+ select IRQ_DOMAIN
+ help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 0000000..acc55a3
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <soc/nps/common.h>
+
+#define NPS_NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
+#define NPS_TIMER0_IRQ 3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb &= ~(1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb |= (1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+ /* Don't ack GIC before all device access attempts are done */
+ mb();
+
+ nps_ack_gic();
+}
+
+static void nps400_irq_eoi(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+}
+
+static struct irq_chip nps400_irq_chip_fasteoi = {
+ .name = "NPS400 IC Global",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi_global,
+};
+
+static struct irq_chip nps400_irq_chip_percpu = {
+ .name = "NPS400 IC",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi,
+};
+
+static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ switch (hw) {
+ case NPS_TIMER0_IRQ:
+#ifdef CONFIG_SMP
+ case IPI_IRQ:
+#endif
+ irq_set_percpu_devid(virq);
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
+ handle_percpu_devid_irq);
+ break;
+ default:
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
+ handle_fasteoi_irq);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops nps400_irq_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = nps400_irq_map,
+};
+
+static int __init nps400_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ static struct irq_domain *nps400_root_domain;
+
+ if (parent)
+ panic("DeviceTree incore ic not a root irq controller\n");
+
+ nps400_root_domain = irq_domain_add_linear(node, NPS_NR_CPU_IRQS,
+ &nps400_irq_ops, NULL);
+
+ if (!nps400_root_domain)
+ panic("nps400 root irq domain not avail\n");
+
+ /*
+ * Needed for primary domain lookup to succeed
+ * This is a primary irqchip, and can never have a parent
+ */
+ irq_set_default_host(nps400_root_domain);
+
+#ifdef CONFIG_SMP
+ irq_create_mapping(nps400_root_domain, IPI_IRQ);
+#endif
+
+ return 0;
+}
+IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v3 3/3] irqchip: add nps Internal and external irqchips
@ 2016-02-06 16:16 ` Noam Camus
0 siblings, 0 replies; 60+ messages in thread
From: Noam Camus @ 2016-02-06 16:16 UTC (permalink / raw)
To: linux-snps-arc
From: Noam Camus <noamc@ezchip.com>
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noam Camus <noamc at ezchip.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier at arm.com>
---
.../interrupt-controller/ezchip,nps400-ic.txt | 17 +++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eznps.c | 145 ++++++++++++++++++++
4 files changed, 169 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 drivers/irqchip/irq-eznps.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 0000000..888b2b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "ezchip,nps400-ic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+ bool "NPS400 Global Interrupt Manager (GIM)"
+ select IRQ_DOMAIN
+ help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 0000000..acc55a3
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <soc/nps/common.h>
+
+#define NPS_NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
+#define NPS_TIMER0_IRQ 3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb &= ~(1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+ unsigned int ienb;
+ unsigned int irq = irqd_to_hwirq(irqd);
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb |= (1 << irq);
+ write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+ /* Don't ack GIC before all device access attempts are done */
+ mb();
+
+ nps_ack_gic();
+}
+
+static void nps400_irq_eoi(struct irq_data *irqd)
+{
+ unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+ write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+}
+
+static struct irq_chip nps400_irq_chip_fasteoi = {
+ .name = "NPS400 IC Global",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi_global,
+};
+
+static struct irq_chip nps400_irq_chip_percpu = {
+ .name = "NPS400 IC",
+ .irq_mask = nps400_irq_mask,
+ .irq_unmask = nps400_irq_unmask,
+ .irq_eoi = nps400_irq_eoi,
+};
+
+static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ switch (hw) {
+ case NPS_TIMER0_IRQ:
+#ifdef CONFIG_SMP
+ case IPI_IRQ:
+#endif
+ irq_set_percpu_devid(virq);
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
+ handle_percpu_devid_irq);
+ break;
+ default:
+ irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
+ handle_fasteoi_irq);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops nps400_irq_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = nps400_irq_map,
+};
+
+static int __init nps400_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ static struct irq_domain *nps400_root_domain;
+
+ if (parent)
+ panic("DeviceTree incore ic not a root irq controller\n");
+
+ nps400_root_domain = irq_domain_add_linear(node, NPS_NR_CPU_IRQS,
+ &nps400_irq_ops, NULL);
+
+ if (!nps400_root_domain)
+ panic("nps400 root irq domain not avail\n");
+
+ /*
+ * Needed for primary domain lookup to succeed
+ * This is a primary irqchip, and can never have a parent
+ */
+ irq_set_default_host(nps400_root_domain);
+
+#ifdef CONFIG_SMP
+ irq_create_mapping(nps400_root_domain, IPI_IRQ);
+#endif
+
+ return 0;
+}
+IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 60+ messages in thread