From: James Morse <james.morse@arm.com> To: Will Deacon <will.deacon@arm.com> Cc: Jonathan.Zhang@cavium.com, Marc Zyngier <marc.zyngier@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Julien Thierry <julien.thierry@arm.com>, wangxiongfeng2@huawei.com, linux-arm-kernel@lists.infradead.org, Dongjiu Geng <gengdongjiu@huawei.com>, kvmarm@lists.cs.columbia.edu Subject: Re: [PATCH v4 11/21] arm64: cpufeature: Detect CPU RAS Extentions Date: Thu, 02 Nov 2017 12:15:50 +0000 [thread overview] Message-ID: <59FB0C76.2000608@arm.com> (raw) In-Reply-To: <20171031131403.GJ5584@arm.com> Hi Will, On 31/10/17 13:14, Will Deacon wrote: > On Thu, Oct 19, 2017 at 03:57:57PM +0100, James Morse wrote: >> From: Xie XiuQi <xiexiuqi@huawei.com> >> >> ARM's v8.2 Extentions add support for Reliability, Availability and >> Serviceability (RAS). On CPUs with these extensions system software >> can use additional barriers to isolate errors and determine if faults >> are pending. >> >> Add cpufeature detection and a barrier in the context-switch code. >> There is no need to use alternatives for this as CPUs that don't >> support this feature will treat the instruction as a nop. >> >> Platform level RAS support may require additional firmware support. >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index cd52d365d1f0..0fc017b55cb1 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -125,6 +125,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { >> }; >> >> static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_RAS_SHIFT, 4, 0), > We probably want FTR_LOWER_SAFE here now, right? (we changed the other > fields in for-next/core). Ah, yes. (Looks like some copy-and-paste) >> diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c >> index 2dc0f8482210..5e5d2f0a1d0a 100644 >> --- a/arch/arm64/kernel/process.c >> +++ b/arch/arm64/kernel/process.c >> @@ -365,6 +365,9 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, >> */ >> dsb(ish); >> >> + /* Deliver any pending SError from prev */ >> + esb(); > I'm assuming this is going to be expensive. I'm hoping not, but without numbers to prove otherwise... > What if we moved it to switch_mm > instead. Do we actually need thread granularity for error isolation? (after a verbal discussion with Will:) This would be needed to blame the correct thread, but until we have kernel-first handling this is moot as do_serror() will panic() regardless. So, lets drop the esb() here and decide what to do if/when we get kernel-first handling. If that only acts on groups of threads, then switch_mm is a better place for it. In the meantime if we see RAS SError panic()s we should remember it may have just switched task, which in practice will probably be obvious from the stack trace. There is no firmware-first angle here as SError is unmasked either side of this, unlike in the KVM example. I'll apply the same logic to the KVM version in patch 20... Thanks, James
WARNING: multiple messages have this Message-ID (diff)
From: james.morse@arm.com (James Morse) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 11/21] arm64: cpufeature: Detect CPU RAS Extentions Date: Thu, 02 Nov 2017 12:15:50 +0000 [thread overview] Message-ID: <59FB0C76.2000608@arm.com> (raw) In-Reply-To: <20171031131403.GJ5584@arm.com> Hi Will, On 31/10/17 13:14, Will Deacon wrote: > On Thu, Oct 19, 2017 at 03:57:57PM +0100, James Morse wrote: >> From: Xie XiuQi <xiexiuqi@huawei.com> >> >> ARM's v8.2 Extentions add support for Reliability, Availability and >> Serviceability (RAS). On CPUs with these extensions system software >> can use additional barriers to isolate errors and determine if faults >> are pending. >> >> Add cpufeature detection and a barrier in the context-switch code. >> There is no need to use alternatives for this as CPUs that don't >> support this feature will treat the instruction as a nop. >> >> Platform level RAS support may require additional firmware support. >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index cd52d365d1f0..0fc017b55cb1 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -125,6 +125,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { >> }; >> >> static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_RAS_SHIFT, 4, 0), > We probably want FTR_LOWER_SAFE here now, right? (we changed the other > fields in for-next/core). Ah, yes. (Looks like some copy-and-paste) >> diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c >> index 2dc0f8482210..5e5d2f0a1d0a 100644 >> --- a/arch/arm64/kernel/process.c >> +++ b/arch/arm64/kernel/process.c >> @@ -365,6 +365,9 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, >> */ >> dsb(ish); >> >> + /* Deliver any pending SError from prev */ >> + esb(); > I'm assuming this is going to be expensive. I'm hoping not, but without numbers to prove otherwise... > What if we moved it to switch_mm > instead. Do we actually need thread granularity for error isolation? (after a verbal discussion with Will:) This would be needed to blame the correct thread, but until we have kernel-first handling this is moot as do_serror() will panic() regardless. So, lets drop the esb() here and decide what to do if/when we get kernel-first handling. If that only acts on groups of threads, then switch_mm is a better place for it. In the meantime if we see RAS SError panic()s we should remember it may have just switched task, which in practice will probably be obvious from the stack trace. There is no firmware-first angle here as SError is unmasked either side of this, unlike in the KVM example. I'll apply the same logic to the KVM version in patch 20... Thanks, James
next prev parent reply other threads:[~2017-11-02 12:15 UTC|newest] Thread overview: 160+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-10-19 14:57 [PATCH v4 00/21] SError rework + RAS&IESB for firmware first support James Morse 2017-10-19 14:57 ` James Morse 2017-10-19 14:57 ` [PATCH v4 01/21] arm64: explicitly mask all exceptions James Morse 2017-10-19 14:57 ` James Morse 2017-10-19 14:57 ` [PATCH v4 02/21] arm64: introduce an order for exceptions James Morse 2017-10-19 14:57 ` James Morse 2017-10-19 14:57 ` [PATCH v4 03/21] arm64: Move the async/fiq helpers to explicitly set process context flags James Morse 2017-10-19 14:57 ` James Morse 2017-10-19 14:57 ` [PATCH v4 04/21] arm64: Mask all exceptions during kernel_exit James Morse 2017-10-19 14:57 ` James Morse 2017-10-19 14:57 ` [PATCH v4 05/21] arm64: entry.S: Remove disable_dbg James Morse 2017-10-19 14:57 ` James Morse 2017-10-19 14:57 ` [PATCH v4 06/21] arm64: entry.S: convert el1_sync James Morse 2017-10-19 14:57 ` James Morse 2017-10-19 14:57 ` [PATCH v4 07/21] arm64: entry.S convert el0_sync James Morse 2017-10-19 14:57 ` James Morse 2017-10-19 14:57 ` [PATCH v4 08/21] arm64: entry.S: convert elX_irq James Morse 2017-10-19 14:57 ` James Morse 2017-10-19 14:57 ` [PATCH v4 09/21] KVM: arm/arm64: mask/unmask daif around VHE guests James Morse 2017-10-19 14:57 ` James Morse 2017-10-30 7:40 ` Christoffer Dall 2017-10-30 7:40 ` Christoffer Dall 2017-11-02 12:14 ` James Morse 2017-11-02 12:14 ` James Morse 2017-11-03 12:45 ` Christoffer Dall 2017-11-03 12:45 ` Christoffer Dall 2017-11-03 17:19 ` James Morse 2017-11-03 17:19 ` James Morse 2017-11-06 12:42 ` Christoffer Dall 2017-11-06 12:42 ` Christoffer Dall 2017-10-19 14:57 ` [PATCH v4 10/21] arm64: entry.S: move SError handling into a C function for future expansion James Morse 2017-10-19 14:57 ` James Morse 2018-01-02 21:07 ` Adam Wallis 2018-01-02 21:07 ` Adam Wallis 2018-01-03 16:00 ` James Morse 2018-01-03 16:00 ` James Morse 2017-10-19 14:57 ` [PATCH v4 11/21] arm64: cpufeature: Detect CPU RAS Extentions James Morse 2017-10-19 14:57 ` James Morse 2017-10-31 13:14 ` Will Deacon 2017-10-31 13:14 ` Will Deacon 2017-11-02 12:15 ` James Morse [this message] 2017-11-02 12:15 ` James Morse 2017-10-19 14:57 ` [PATCH v4 12/21] arm64: kernel: Survive corrected RAS errors notified by SError James Morse 2017-10-19 14:57 ` James Morse 2017-10-31 13:50 ` Will Deacon 2017-10-31 13:50 ` Will Deacon 2017-11-02 12:15 ` James Morse 2017-11-02 12:15 ` James Morse 2017-10-19 14:57 ` [PATCH v4 13/21] arm64: cpufeature: Enable IESB on exception entry/return for firmware-first James Morse 2017-10-19 14:57 ` James Morse 2017-10-31 13:56 ` Will Deacon 2017-10-31 13:56 ` Will Deacon 2017-10-19 14:58 ` [PATCH v4 14/21] arm64: kernel: Prepare for a DISR user James Morse 2017-10-19 14:58 ` James Morse 2017-10-19 14:58 ` [PATCH v4 15/21] KVM: arm64: Set an impdef ESR for Virtual-SError using VSESR_EL2 James Morse 2017-10-19 14:58 ` James Morse 2017-10-20 16:44 ` gengdongjiu 2017-10-20 16:44 ` gengdongjiu 2017-10-23 15:26 ` James Morse 2017-10-23 15:26 ` James Morse 2017-10-24 9:53 ` gengdongjiu 2017-10-24 9:53 ` gengdongjiu 2017-10-30 7:59 ` Christoffer Dall 2017-10-30 7:59 ` Christoffer Dall 2017-10-30 10:51 ` Christoffer Dall 2017-10-30 10:51 ` Christoffer Dall 2017-10-30 15:44 ` James Morse 2017-10-30 15:44 ` James Morse 2017-10-31 5:48 ` Christoffer Dall 2017-10-31 5:48 ` Christoffer Dall 2017-10-31 6:34 ` Marc Zyngier 2017-10-31 6:34 ` Marc Zyngier 2017-10-19 14:58 ` [PATCH v4 16/21] KVM: arm64: Save/Restore guest DISR_EL1 James Morse 2017-10-19 14:58 ` James Morse 2017-10-31 4:27 ` Marc Zyngier 2017-10-31 4:27 ` Marc Zyngier 2017-10-31 5:27 ` Christoffer Dall 2017-10-31 5:27 ` Christoffer Dall 2017-10-19 14:58 ` [PATCH v4 17/21] KVM: arm64: Save ESR_EL2 on guest SError James Morse 2017-10-19 14:58 ` James Morse 2017-10-31 4:26 ` Marc Zyngier 2017-10-31 4:26 ` Marc Zyngier 2017-10-31 5:47 ` Marc Zyngier 2017-10-31 5:47 ` Marc Zyngier 2017-11-01 17:42 ` James Morse 2017-11-01 17:42 ` James Morse 2017-10-19 14:58 ` [PATCH v4 18/21] KVM: arm64: Handle RAS SErrors from EL1 on guest exit James Morse 2017-10-19 14:58 ` James Morse 2017-10-31 5:55 ` Marc Zyngier 2017-10-31 5:55 ` Marc Zyngier 2017-10-31 5:56 ` Christoffer Dall 2017-10-31 5:56 ` Christoffer Dall 2017-10-19 14:58 ` [PATCH v4 19/21] KVM: arm64: Handle RAS SErrors from EL2 " James Morse 2017-10-19 14:58 ` James Morse 2017-10-27 6:26 ` gengdongjiu 2017-10-27 6:26 ` gengdongjiu 2017-10-27 17:38 ` James Morse 2017-10-27 17:38 ` James Morse 2017-10-31 6:13 ` Marc Zyngier 2017-10-31 6:13 ` Marc Zyngier 2017-10-31 6:13 ` Christoffer Dall 2017-10-31 6:13 ` Christoffer Dall 2017-10-19 14:58 ` [PATCH v4 20/21] KVM: arm64: Take any host SError before entering the guest James Morse 2017-10-19 14:58 ` James Morse 2017-10-31 6:23 ` Christoffer Dall 2017-10-31 6:23 ` Christoffer Dall 2017-10-31 11:43 ` James Morse 2017-10-31 11:43 ` James Morse 2017-11-01 4:55 ` Christoffer Dall 2017-11-01 4:55 ` Christoffer Dall 2017-11-02 12:18 ` James Morse 2017-11-02 12:18 ` James Morse 2017-11-03 12:49 ` Christoffer Dall 2017-11-03 12:49 ` Christoffer Dall 2017-11-03 16:14 ` James Morse 2017-11-03 16:14 ` James Morse 2017-11-06 12:45 ` Christoffer Dall 2017-11-06 12:45 ` Christoffer Dall 2017-10-19 14:58 ` [PATCH v4 21/21] KVM: arm64: Trap RAS error registers and set HCR_EL2's TERR & TEA James Morse 2017-10-19 14:58 ` James Morse 2017-10-31 6:32 ` Christoffer Dall 2017-10-31 6:32 ` Christoffer Dall 2017-10-31 6:32 ` Marc Zyngier 2017-10-31 6:32 ` Marc Zyngier 2017-10-31 6:35 ` [PATCH v4 00/21] SError rework + RAS&IESB for firmware first support Christoffer Dall 2017-10-31 6:35 ` Christoffer Dall 2017-10-31 10:08 ` Will Deacon 2017-10-31 10:08 ` Will Deacon 2017-11-01 15:23 ` James Morse 2017-11-01 15:23 ` James Morse 2017-11-02 8:14 ` Christoffer Dall 2017-11-02 8:14 ` Christoffer Dall 2017-11-09 18:14 ` James Morse 2017-11-09 18:14 ` James Morse 2017-11-10 12:03 ` gengdongjiu 2017-11-10 12:03 ` gengdongjiu 2017-11-13 11:29 ` Christoffer Dall 2017-11-13 11:29 ` Christoffer Dall 2017-11-13 13:05 ` Peter Maydell 2017-11-13 13:05 ` Peter Maydell 2017-11-20 8:53 ` Christoffer Dall 2017-11-20 8:53 ` Christoffer Dall 2017-11-13 16:14 ` Andrew Jones 2017-11-13 16:14 ` Andrew Jones 2017-11-13 17:56 ` Peter Maydell 2017-11-13 17:56 ` Peter Maydell 2017-11-14 16:11 ` James Morse 2017-11-14 16:11 ` James Morse 2017-11-15 9:59 ` gengdongjiu 2017-11-15 9:59 ` gengdongjiu 2017-11-14 16:03 ` James Morse 2017-11-14 16:03 ` James Morse 2017-11-15 9:15 ` gengdongjiu 2017-11-15 9:15 ` gengdongjiu 2017-11-15 18:25 ` James Morse 2017-11-15 18:25 ` James Morse 2017-11-21 11:31 ` gengdongjiu 2017-11-21 11:31 ` gengdongjiu 2017-11-20 8:55 ` Christoffer Dall 2017-11-20 8:55 ` Christoffer Dall
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