[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM and 128MB of hardwired NAND flash
memory. USB controller is available, but not presently enabled.

Additional board information is available at:
http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx

Signed-off-by: Alex Dubov <oakad@yahoo.com>
---
 board/mercury/mpq101/Makefile  |   53 ++++++
 board/mercury/mpq101/config.mk |    7 +
 board/mercury/mpq101/law.c     |   54 ++++++
 board/mercury/mpq101/mpq101.c  |  167 ++++++++++++++++++
 board/mercury/mpq101/tlb.c     |   82 +++++++++
 boards.cfg                     |    1 +
 include/configs/mpq101.h       |  381 ++++++++++++++++++++++++++++++++++++++++
 7 files changed, 745 insertions(+), 0 deletions(-)
 create mode 100644 board/mercury/mpq101/Makefile
 create mode 100644 board/mercury/mpq101/config.mk
 create mode 100644 board/mercury/mpq101/law.c
 create mode 100644 board/mercury/mpq101/mpq101.c
 create mode 100644 board/mercury/mpq101/tlb.c
 create mode 100644 include/configs/mpq101.h

diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile
new file mode 100644
index 0000000..58bc1b3
--- /dev/null
+++ b/board/mercury/mpq101/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mercury/mpq101/config.mk b/board/mercury/mpq101/config.mk
new file mode 100644
index 0000000..1870680
--- /dev/null
+++ b/board/mercury/mpq101/config.mk
@@ -0,0 +1,7 @@
+#
+# mpq101 board
+#
+
+# Make room for environment at the beginning of flash sector
+CONFIG_SYS_TEXT_BASE = 0xfffc0800
+LDFLAGS += --section-start=.ppcenv=$(CONFIG_ENV_ADDR)
diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c
new file mode 100644
index 0000000..bc89bc5
--- /dev/null
+++ b/board/mercury/mpq101/law.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x1fff_ffff     DDR                     SYS_SDRAM_SIZE
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
+	LAW_TRGT_IF_DDR_1),
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/mercury/mpq101/mpq101.c b/board/mercury/mpq101/mpq101.c
new file mode 100644
index 0000000..18fb88e
--- /dev/null
+++ b/board/mercury/mpq101/mpq101.c
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2010 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+void local_bus_init(void);
+void sdram_init(void);
+
+unsigned long get_clock_freq(void)
+{
+	return 33000000;
+}
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	puts ("Board: Mercury Computer Systems, Inc. MPQ-101 ");
+#ifdef CONFIG_PHYS_64BIT
+	puts ("(36-bit addrmap) ");
+#endif
+	putc ('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+phys_size_t
+initdram (int board_type)
+{
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+	phys_size_t dram_size = 0;
+	const char *p_mode = getenv("perf_mode");
+
+	puts("Initializing....");
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+
+	if (p_mode && !strcmp("performance", p_mode)) {
+		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
+		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
+		ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1_PERF;
+		ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_PERF;
+		ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL_PERF;
+	} else {
+		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+		ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+		ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+		ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	}
+
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+
+	asm("sync;isync");
+	udelay(500);
+
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+	asm("sync; isync");
+	udelay(500);
+
+	dram_size = setup_ddr_tlbs(1ull << (CONFIG_SYS_SDRAM_SIZE_LOG - 20));
+
+	puts("    DDR: ");
+
+	return dram_size << 20;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	gur->lbiuiplldcr1 = 0x00078080;
+	if (clkdiv == 16) {
+		gur->lbiuiplldcr0 = 0x7c0f1bf0;
+	} else if (clkdiv == 8) {
+		gur->lbiuiplldcr0 = 0x6c0f1bf0;
+	} else if (clkdiv == 4) {
+		gur->lbiuiplldcr0 = 0x5c0f1bf0;
+	}
+
+	lbc->lcrr |= 0x00030000;
+	asm("sync;isync;msync");
+
+	lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
+	lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
+}
+
+void
+pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+        ft_cpu_setup(blob, bd);
+}
+
+#endif
diff --git a/board/mercury/mpq101/tlb.c b/board/mercury/mpq101/tlb.c
new file mode 100644
index 0000000..1f1c5b1
--- /dev/null
+++ b/board/mercury/mpq101/tlb.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	256M	Non-cacheable, guarded
+	 * 0xf0000000	256M	LBC (FLASH included)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+		      CONFIG_SYS_LBC_OPTION_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 1:	1M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+	/*
+	 * TLB 2:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+		      CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 08e531e..a0baa4f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -189,6 +189,7 @@ TQM834x		powerpc	mpc83xx		tqm834x		tqc
 sbc8349		powerpc	mpc83xx		sbc8349		-		-	sbc8349
 caddy2		powerpc	mpc83xx		vme8349		esd		-	vme8349:CADDY2
 vme8349		powerpc	mpc83xx		vme8349		esd		-	vme8349
+mpq101		powerpc	mpc85xx		mpq101		mercury		-	mpq101
 PM854		powerpc	mpc85xx		pm854
 PM856		powerpc	mpc85xx		pm856
 P1022DS		powerpc	mpc85xx		p1022ds		freescale
diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h
new file mode 100644
index 0000000..7f8c5c5
--- /dev/null
+++ b/include/configs/mpq101.h
@@ -0,0 +1,381 @@
+/*
+ * Copyright 2010 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Merury Computers MPQ101 board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+//#define DEBUG         5
+//#define CMD_MEM_DEBUG 1
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE      1 /* BOOKE */
+#define CONFIG_E500       1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx    1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548    1 /* MPC8548 specific */
+#define CONFIG_MPQ101     1 /* MPQ101 board specific */
+
+#define CONFIG_RIO
+
+#define CONFIG_TSEC_ENET      1 /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE  1
+#define CONFIG_INTERRUPTS     1 /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW        1 /* Use common FSL init code */
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE 1 /* toggle L2 cache */
+#define CONFIG_BTB      1 /* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP         1
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+
+#define CONFIG_SYS_ALT_MEMTEST   1
+#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END   0x0ffffffc
+
+#define CONFIG_PANIC_HANG
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_CCSRBAR         0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define
+#define CONFIG_SYS_CCSRBAR_PHYS    0xfe0000000ull
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS    CONFIG_SYS_CCSRBAR
+#endif
+#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_SPD_EEPROM
+#undef CONFIG_DDR_SPD
+#undef CONFIG_DDR_DLL
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1  /* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE     0xDeadBeef
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE     CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS   1
+#define CONFIG_DIMM_SLOTS_PER_CTLR   1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* Fixed 512MB DDR2 parameters */
+#define CONFIG_SYS_SDRAM_SIZE_LOG       29 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS         0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014102
+#define CONFIG_SYS_DDR_TIMING_3         0x00010000
+#define CONFIG_SYS_DDR_TIMING_0         0x00260802
+#define CONFIG_SYS_DDR_TIMING_1         0x5c47a432
+#define CONFIG_SYS_DDR_TIMING_1_PERF    0x49352322
+#define CONFIG_SYS_DDR_TIMING_2         0x03984cce
+#define CONFIG_SYS_DDR_TIMING_2_PERF    0x14904cca
+#define CONFIG_SYS_DDR_MODE_1           0x00400442
+#define CONFIG_SYS_DDR_MODE_1_PERF      0x00480432
+#define CONFIG_SYS_DDR_MODE_2           0x00000000
+#define CONFIG_SYS_DDR_MODE_2_PERF      0x00000000
+#define CONFIG_SYS_DDR_INTERVAL         0x08200100
+#define CONFIG_SYS_DDR_INTERVAL_PERF    0x06180100
+#define CONFIG_SYS_DDR_CLK_CTRL         0x03800000
+#define CONFIG_SYS_DDR_CONTROL          0xc3008000 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2         0x04400000
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * One bank, 128M, using the CFI driver.
+ */
+
+#define CONFIG_SYS_BOOT_BLOCK 0xf8000000            /* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS      0xff8000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
+#endif
+
+/* 0xf8001801 */
+#define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				| BR_PS_32 | BR_V)
+
+/* 0xf8006ff7 */
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 | OR_GPCM_TRLX \
+				| OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#undef CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45   /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1    /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT  512  /* sectors per device */
+#undef  CONFIG_SYS_FLASH_CHECKSUM
+
+//#define CONFIG_SYS_BR0_PRELIM 0xff001801
+//#define CONFIG_SYS_BR1_PRELIM 0xf0001001
+
+//#define CONFIG_SYS_OR0_PRELIM 0xff006e65
+//#define CONFIG_SYS_OR1_PRELIM 0xff006e65
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500   /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+/*
+ * Local Bus
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE   0xf0000000
+#define CONFIG_SYS_LBC_CACHE_BASE    CONFIG_SYS_LBC_OPTION_BASE
+#define CONFIG_SYS_LBC_CACHE_SIZE    64
+#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf4000000
+#define CONFIG_SYS_LBC_NONCACHE_SIZE 64
+
+#define CONFIG_SYS_LBC_LCRR          0x00000004      /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR          0x00000000      /* LB config reg */
+
+#define CONFIG_SYS_INIT_RAM_LOCK     1
+#define CONFIG_SYS_INIT_RAM_ADDR     0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE     0x4000     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN       (256 * 1024)  /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN        (1024 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX           2
+#undef  CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT           1
+#define CONFIG_OF_BOARD_SETUP      1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* new uImage format support */
+#define CONFIG_FIT              1
+#define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
+
+//#define CONFIG_SYS_64BIT_VSPRINTF 1
+//#define CONFIG_SYS_64BIT_STRTOUL  1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C                 /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C                /* I2C with hardware support*/
+#undef  CONFIG_SOFT_I2C                /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED    400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE    0x7f
+#define CONFIG_SYS_I2C_OFFSET   0x3000
+#define CONFIG_SYS_I2C2_OFFSET  0x3100
+
+#ifdef CONFIG_RIO
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO_MEM_PHYS 0xfc0000000ull
+#else
+#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
+#endif
+#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI  1
+#endif
+
+#define CONFIG_MII        1       /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1      1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2      1
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define CONFIG_TSEC3      1
+#define CONFIG_TSEC3_NAME "eTSEC2"
+#define CONFIG_TSEC4      1
+#define CONFIG_TSEC4_NAME "eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR    0x10
+#define TSEC2_PHY_ADDR    0x11
+#define TSEC3_PHY_ADDR    0x12
+#define TSEC4_PHY_ADDR    0x13
+
+#define TSEC1_PHYIDX      0
+#define TSEC2_PHYIDX      0
+#define TSEC3_PHYIDX      0
+#define TSEC4_PHYIDX      0
+
+#define TSEC1_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME   "eTSEC0"
+#define CONFIG_PHY_GIGE   1 /* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_SYS_USE_PPCENV  1
+#define ENV_IS_EMBEDDED        1
+#define CONFIG_ENV_SECT_SIZE   0x40000   /* 256K */
+#define CONFIG_ENV_SIZE        0x800
+#define CONFIG_ENV_ADDR        0xfffc0000
+
+#define CONFIG_LOADS_ECHO             1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE  1 /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef  CONFIG_CMD_FPGA
+#undef  CONFIG_CMD_NFS
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_JFFS2
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING                 /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE                   /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "MPQ-101=> "    /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024                 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256                  /* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_BAUDRATE  115200
+
+#define CONFIG_LOADADDR  1000000 /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10      /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS          /* the boot command will set bootargs*/
+
+#endif /* __CONFIG_H */
-- 
1.7.3.2



      

[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Wolfgang Denk]

Dear Alex Dubov,

In message <25288.34605.qm@web37607.mail.mud.yahoo.com> you wrote:
> Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
> processor, 512MB of hardwired DDR2 RAM and 128MB of hardwired NAND flash
> memory. USB controller is available, but not presently enabled.
> 
> Additional board information is available at:
> http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx
> 
> Signed-off-by: Alex Dubov <oakad@yahoo.com>
> ---
>  board/mercury/mpq101/Makefile  |   53 ++++++
>  board/mercury/mpq101/config.mk |    7 +
>  board/mercury/mpq101/law.c     |   54 ++++++
>  board/mercury/mpq101/mpq101.c  |  167 ++++++++++++++++++
>  board/mercury/mpq101/tlb.c     |   82 +++++++++
>  boards.cfg                     |    1 +
>  include/configs/mpq101.h       |  381 ++++++++++++++++++++++++++++++++++++++++

Entry to MAINTAINERS missing.


> diff --git a/board/mercury/mpq101/config.mk b/board/mercury/mpq101/config.mk
> new file mode 100644
> index 0000000..1870680
> --- /dev/null
> +++ b/board/mercury/mpq101/config.mk
> @@ -0,0 +1,7 @@
> +#
> +# mpq101 board
> +#
> +
> +# Make room for environment at the beginning of flash sector
> +CONFIG_SYS_TEXT_BASE = 0xfffc0800
> +LDFLAGS += --section-start=.ppcenv=$(CONFIG_ENV_ADDR)

Please mode defines to board config file and get rid of config.mk

> +phys_size_t
> +initdram (int board_type)
> +{
...
> +	dram_size = setup_ddr_tlbs(1ull << (CONFIG_SYS_SDRAM_SIZE_LOG - 20));
> +
> +	puts("    DDR: ");
> +
> +	return dram_size << 20;

You should use get_ram_size().

> +local_bus_init(void)
> +{
> +	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
> +
> +	uint clkdiv;
> +	uint lbc_hz;
> +	sys_info_t sysinfo;
> +
> +	get_sys_info(&sysinfo);
> +	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
> +	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
> +
> +	gur->lbiuiplldcr1 = 0x00078080;
> +	if (clkdiv == 16) {
> +		gur->lbiuiplldcr0 = 0x7c0f1bf0;
> +	} else if (clkdiv == 8) {
> +		gur->lbiuiplldcr0 = 0x6c0f1bf0;
> +	} else if (clkdiv == 4) {
> +		gur->lbiuiplldcr0 = 0x5c0f1bf0;
> +	}
> +
> +	lbc->lcrr |= 0x00030000;
> +	asm("sync;isync;msync");
> +
> +	lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
> +	lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */

NAK.  Please use proper I/O accessors.

...
> +#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
...
> +#define CONFIG_LOADADDR  1000000 /*default location for tftp and bootm*/

You probably want to make this consistent.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
You can only live once, but if you do it right, once is enough.

[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

> > +phys_size_t
> > +initdram (int board_type)
> > +{
> ...
> > +??? dram_size = setup_ddr_tlbs(1ull
> << (CONFIG_SYS_SDRAM_SIZE_LOG - 20));
> > +
> > +??? puts("? ? DDR: ");
> > +
> > +??? return dram_size << 20;
> 
> You should use get_ram_size().

I still need to call setup_ddr_tlbs because get_ram_size won't do it for
me. So what get_ram_size actually does?


> > +??? lbc->lcrr |= 0x00030000;
> > +??? asm("sync;isync;msync");
> > +
> > +??? lbc->ltesr = 0xffffffff;?
> ? ? ? /* Clear LBC error interrupts */
> > +??? lbc->lteir = 0xffffffff;?
> ? ? ? /* Enable LBC error interrupts */
> 
> NAK.? Please use proper I/O accessors.

Do you mean out_be32 and friends?
In which case, why are not these used when writing config values to DDR
registers (for instance) even in some very recently added boards, such as
p2020ds?

> 
> ...
> > +#define
> CONFIG_SYS_LOAD_ADDR???0x2000000? ?
> ???/* default load address */
> ...
> > +#define CONFIG_LOADADDR? 1000000 /*default
> location for tftp and bootm*/
> 
> You probably want to make this consistent.
> 
> Best regards,
> 
> Wolfgang Denk
> 
> -- 
> DENX Software Engineering GmbH,? ???MD:
> Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email:
> wd at denx.de
> You can only live once, but if you do it right, once is
> enough.
> 


      

[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

> > +CONFIG_SYS_TEXT_BASE = 0xfffc0800
> > +LDFLAGS +=
> --section-start=.ppcenv=$(CONFIG_ENV_ADDR)
> 
> Please mode defines to board config file and get rid of
> config.mk

And another question: how am I supposed to specify linker flags in the
board config file (I suppose, you mean boards.cfg). There's no examples
throughout the u-boot tree where it is done and Makefile do not seem to
peek those either (they just end up in autoconf.mk).



      

[U-Boot] [PATCH v3] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
memory, real time clock and additional serial EEPROM on i2c bus (enabled).
USB controller is available, but not presently enabled.

Additional board information is available at:
http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx

Environment is configured to preceed the actual u-boot image so that it's
located at the beginning of flash erase block (made necessary by the recent
changes to the embedded environment handling).

Signed-off-by: Alex Dubov <oakad@yahoo.com>
---
 MAINTAINERS                    |    3 +
 board/mercury/mpq101/Makefile  |   53 +++++
 board/mercury/mpq101/config.mk |    6 +
 board/mercury/mpq101/law.c     |   55 ++++++
 board/mercury/mpq101/mpq101.c  |  146 ++++++++++++++
 board/mercury/mpq101/tlb.c     |   82 ++++++++
 boards.cfg                     |    1 +
 include/configs/mpq101.h       |  410 ++++++++++++++++++++++++++++++++++++++++
 8 files changed, 756 insertions(+), 0 deletions(-)
 create mode 100644 board/mercury/mpq101/Makefile
 create mode 100644 board/mercury/mpq101/config.mk
 create mode 100644 board/mercury/mpq101/law.c
 create mode 100644 board/mercury/mpq101/mpq101.c
 create mode 100644 board/mercury/mpq101/tlb.c
 create mode 100644 include/configs/mpq101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 9258cb1..e31fc5e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -138,6 +138,9 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260		MPC8260
 
+Alex Dubov <oakad@yahoo.com>
+	mpq101		MPC8548
+
 Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX
diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile
new file mode 100644
index 0000000..58bc1b3
--- /dev/null
+++ b/board/mercury/mpq101/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mercury/mpq101/config.mk b/board/mercury/mpq101/config.mk
new file mode 100644
index 0000000..1d83f9a
--- /dev/null
+++ b/board/mercury/mpq101/config.mk
@@ -0,0 +1,6 @@
+#
+# mpq101 board
+#
+
+# Make room for environment at the beginning of flash sector
+LDFLAGS += --section-start=.ppcenv=$(CONFIG_ENV_ADDR)
diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c
new file mode 100644
index 0000000..726b5c2
--- /dev/null
+++ b/board/mercury/mpq101/law.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x1fff_ffff     DDR                     SYS_SDRAM_SIZE
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
+		LAW_TRGT_IF_DDR_1),
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
+		LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/mercury/mpq101/mpq101.c b/board/mercury/mpq101/mpq101.c
new file mode 100644
index 0000000..87b2ca0
--- /dev/null
+++ b/board/mercury/mpq101/mpq101.c
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2010 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+void local_bus_init(void);
+void sdram_init(void);
+
+unsigned long get_clock_freq(void)
+{
+	return 33000000;
+}
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	puts ("Board: Mercury Computer Systems, Inc. MPQ-101 ");
+#ifdef CONFIG_PHYS_64BIT
+	puts ("(36-bit addrmap) ");
+#endif
+	putc ('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+phys_size_t
+initdram (int board_type)
+{
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+	phys_size_t dram_size = 0;
+	const char *p_mode = getenv("perf_mode");
+
+	puts("Initializing....");
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (p_mode && !strcmp("performance", p_mode)) {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
+	} else {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	}
+
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
+
+	asm("sync;isync");
+	udelay(500);
+
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+	asm("sync; isync");
+	udelay(500);
+
+	dram_size = setup_ddr_tlbs(1ull << (CONFIG_SYS_SDRAM_SIZE_LOG - 20));
+
+	puts("    DDR: ");
+
+	return get_ram_size(0, dram_size << 20);
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+}
+
+void
+pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+        ft_cpu_setup(blob, bd);
+}
+
+#endif
diff --git a/board/mercury/mpq101/tlb.c b/board/mercury/mpq101/tlb.c
new file mode 100644
index 0000000..3e3d280
--- /dev/null
+++ b/board/mercury/mpq101/tlb.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	256M	Non-cacheable, guarded
+	 * 0xf0000000	256M	LBC (FLASH included)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+		      CONFIG_SYS_LBC_OPTION_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 1:	1M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+	/*
+	 * TLB 2:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+		      CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 08e531e..a0baa4f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -189,6 +189,7 @@ TQM834x		powerpc	mpc83xx		tqm834x		tqc
 sbc8349		powerpc	mpc83xx		sbc8349		-		-	sbc8349
 caddy2		powerpc	mpc83xx		vme8349		esd		-	vme8349:CADDY2
 vme8349		powerpc	mpc83xx		vme8349		esd		-	vme8349
+mpq101		powerpc	mpc85xx		mpq101		mercury		-	mpq101
 PM854		powerpc	mpc85xx		pm854
 PM856		powerpc	mpc85xx		pm856
 P1022DS		powerpc	mpc85xx		p1022ds		freescale
diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h
new file mode 100644
index 0000000..8522b0a
--- /dev/null
+++ b/include/configs/mpq101.h
@@ -0,0 +1,410 @@
+/*
+ * Copyright 2010 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Merury Computers MPQ101 board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+//#define DEBUG         5
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE      1 /* BOOKE */
+#define CONFIG_E500       1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx    1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548    1 /* MPC8548 specific */
+#define CONFIG_MPQ101     1 /* MPQ101 board specific */
+
+#define CONFIG_RIO
+
+#define CONFIG_TSEC_ENET      1 /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE  1
+#define CONFIG_INTERRUPTS     1 /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW        1 /* Use common FSL init code */
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE 1 /* toggle L2 cache */
+#define CONFIG_BTB      1 /* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP         1
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+
+#define CONFIG_SYS_ALT_MEMTEST   1
+#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END   0x0ffffffc
+
+#define CONFIG_PANIC_HANG
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_CCSRBAR         0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define
+#define CONFIG_SYS_CCSRBAR_PHYS    0xfe0000000ull
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS    CONFIG_SYS_CCSRBAR
+#endif
+#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_SPD_EEPROM
+#undef CONFIG_DDR_SPD
+#undef CONFIG_DDR_DLL
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1  /* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE     0xDeadBeef
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE     CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS   1
+#define CONFIG_DIMM_SLOTS_PER_CTLR   1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* Fixed 512MB DDR2 parameters */
+#define CONFIG_SYS_SDRAM_SIZE_LOG       29 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS         0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014102
+#define CONFIG_SYS_DDR_TIMING_3         0x00010000
+#define CONFIG_SYS_DDR_TIMING_0         0x00260802
+#define CONFIG_SYS_DDR_TIMING_1         0x5c47a432
+#define CONFIG_SYS_DDR_TIMING_1_PERF    0x49352322
+#define CONFIG_SYS_DDR_TIMING_2         0x03984cce
+#define CONFIG_SYS_DDR_TIMING_2_PERF    0x14904cca
+#define CONFIG_SYS_DDR_MODE_1           0x00400442
+#define CONFIG_SYS_DDR_MODE_1_PERF      0x00480432
+#define CONFIG_SYS_DDR_MODE_2           0x00000000
+#define CONFIG_SYS_DDR_MODE_2_PERF      0x00000000
+#define CONFIG_SYS_DDR_INTERVAL         0x08200100
+#define CONFIG_SYS_DDR_INTERVAL_PERF    0x06180100
+#define CONFIG_SYS_DDR_CLK_CTRL         0x03800000
+#define CONFIG_SYS_DDR_CONTROL          0xc3008000 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2         0x04400000
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * One bank, 128M, using the CFI driver.
+ */
+
+#define CONFIG_SYS_BOOT_BLOCK 0xf8000000            /* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS      0xff8000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
+#endif
+
+/* 0xf8001801 */
+#define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				| BR_PS_32 | BR_V)
+
+/* 0xf8006ff7 */
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 | OR_GPCM_TRLX \
+				| OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#undef CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45   /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1    /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT  512  /* sectors per device */
+#undef  CONFIG_SYS_FLASH_CHECKSUM
+
+//#define CONFIG_SYS_BR0_PRELIM 0xff001801
+//#define CONFIG_SYS_BR1_PRELIM 0xf0001001
+
+//#define CONFIG_SYS_OR0_PRELIM 0xff006e65
+//#define CONFIG_SYS_OR1_PRELIM 0xff006e65
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500   /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+/*
+ * 16b peripherals on the Local Bus
+ * 64k
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE   0xf0000000
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_LBC_OPTION_BASE_PHYS      0xff0000000ull
+#else
+#define CONFIG_SYS_LBC_OPTION_BASE_PHYS      CONFIG_SYS_LBC_OPTION_BASE
+#endif
+
+
+/* 0xf0001001 */
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
+				| BR_PS_16 | BR_V)
+
+/* ffff7002 */
+#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(0x10000) | OR_GPCM_XAM \
+				| OR_GPCM_BCTLD | OR_GPCM_EHTR)
+
+#define CONFIG_SYS_LBC_LCRR          0x00000004 /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR          0x00000000 /* LB config reg */
+
+#define CONFIG_SYS_INIT_RAM_LOCK     1
+#define CONFIG_SYS_INIT_RAM_ADDR     0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE     0x4000     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN       (256 * 1024)  /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN        (1024 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX           2
+#undef  CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT           1
+#define CONFIG_OF_BOARD_SETUP      1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* new uImage format support */
+#define CONFIG_FIT              1
+#define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
+
+//#define CONFIG_SYS_64BIT_VSPRINTF 1
+//#define CONFIG_SYS_64BIT_STRTOUL  1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C                 /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C                /* I2C with hardware support*/
+#undef  CONFIG_SOFT_I2C                /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED    400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE    0x7f
+#define CONFIG_SYS_I2C_OFFSET   0x3000
+#define CONFIG_SYS_I2C2_OFFSET  0x3100
+
+/* I2C RTC - M41T81 */
+#define CONFIG_RTC_M41T62               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR     2000
+
+/* I2C EEPROM - 24C256 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR            0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        2
+#define CONFIG_SYS_EEPROM_BUS_NUM             1
+
+#ifdef CONFIG_RIO
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO_MEM_PHYS 0xfc0000000ull
+#else
+#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
+#endif
+#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI  1
+#endif
+
+#define CONFIG_MII        1       /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1      1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2      1
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define CONFIG_TSEC3      1
+#define CONFIG_TSEC3_NAME "eTSEC2"
+#define CONFIG_TSEC4      1
+#define CONFIG_TSEC4_NAME "eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR    0x10
+#define TSEC2_PHY_ADDR    0x11
+#define TSEC3_PHY_ADDR    0x12
+#define TSEC4_PHY_ADDR    0x13
+
+#define TSEC1_PHYIDX      0
+#define TSEC2_PHYIDX      0
+#define TSEC3_PHYIDX      0
+#define TSEC4_PHYIDX      0
+
+#define TSEC1_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME   "eTSEC0"
+#define CONFIG_PHY_GIGE   1 /* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_SYS_USE_PPCENV  1
+#define ENV_IS_EMBEDDED        1
+#define CONFIG_ENV_SECT_SIZE   0x40000   /* 256K */
+#define CONFIG_ENV_SIZE        0x800
+
+/*Environment at the start of flash sector, before text. */
+#define CONFIG_ENV_ADDR        0xfffc0000
+#define CONFIG_SYS_TEXT_BASE   0xfffc0800
+
+#define CONFIG_LOADS_ECHO             1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE  1 /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef  CONFIG_CMD_FPGA
+#undef  CONFIG_CMD_NFS
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_JFFS2
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING                 /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE                   /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "MPQ-101=> "    /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024                 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256                  /* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_BAUDRATE  115200
+
+#define CONFIG_LOADADDR  CONFIG_SYS_LOAD_ADDR /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10      /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS          /* the boot command will set bootargs*/
+
+#endif /* __CONFIG_H */
-- 
1.7.3.2




      

[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Wolfgang Denk]

Dear Alex Dubov,

In message <754013.38475.qm@web37602.mail.mud.yahoo.com> you wrote:
> > You should use get_ram_size().
> 
> I still need to call setup_ddr_tlbs because get_ram_size won't do it for
> me. So what get_ram_size actually does?

It checks the size of available memory and performs a simple, fast
and non-destuctive memory test on the way.

> > NAK.? Please use proper I/O accessors.
> 
> Do you mean out_be32 and friends?

Right.

> In which case, why are not these used when writing config values to DDR
> registers (for instance) even in some very recently added boards, such as
> p2020ds?

Because this escaped review?

Can you please point out where this was missed, so it can be fixed?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The universe, they said, depended for its operation on the balance of
four forces which they identified as charm,  persuasion,  uncertainty
and bloody-mindedness.      -- Terry Pratchett, "The Light Fantastic"

[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Wolfgang Denk]

Dear Alex Dubov,

In message <288884.88500.qm@web37608.mail.mud.yahoo.com> you wrote:
> > > +CONFIG_SYS_TEXT_BASE = 0xfffc0800
> > > +LDFLAGS +=
> > --section-start=.ppcenv=$(CONFIG_ENV_ADDR)
> > 
> > Please mode defines to board config file and get rid of
> > config.mk
> 
> And another question: how am I supposed to specify linker flags in the
> board config file (I suppose, you mean boards.cfg). There's no

No, I mean include/configs/<name>.h

> examples
> throughout the u-boot tree where it is done and Makefile do not seem
> to
> peek those either (they just end up in autoconf.mk).
...which then gets included.

Anyway - maybe you should ponder why you need to do something nobody
else needs, and then fix the code.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It is much easier to suggest solutions when you know nothing

[U-Boot] [PATCH v3] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Wolfgang Denk]

Dear Alex Dubov,

In message <294951.51594.qm@web37601.mail.mud.yahoo.com> you wrote:
> Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
> processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
> memory, real time clock and additional serial EEPROM on i2c bus (enabled).
> USB controller is available, but not presently enabled.
> 
> Additional board information is available at:
> http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx
> 
> Environment is configured to preceed the actual u-boot image so that it's
> located at the beginning of flash erase block (made necessary by the recent
> changes to the embedded environment handling).
> 
> Signed-off-by: Alex Dubov <oakad@yahoo.com>
> ---
>  MAINTAINERS                    |    3 +
>  board/mercury/mpq101/Makefile  |   53 +++++
>  board/mercury/mpq101/config.mk |    6 +
>  board/mercury/mpq101/law.c     |   55 ++++++
>  board/mercury/mpq101/mpq101.c  |  146 ++++++++++++++
>  board/mercury/mpq101/tlb.c     |   82 ++++++++
>  boards.cfg                     |    1 +
>  include/configs/mpq101.h       |  410 ++++++++++++++++++++++++++++++++++++++++
>  8 files changed, 756 insertions(+), 0 deletions(-)
>  create mode 100644 board/mercury/mpq101/Makefile
>  create mode 100644 board/mercury/mpq101/config.mk
>  create mode 100644 board/mercury/mpq101/law.c
>  create mode 100644 board/mercury/mpq101/mpq101.c
>  create mode 100644 board/mercury/mpq101/tlb.c
>  create mode 100644 include/configs/mpq101.h

I'm not going to review this again.  Why don't you explain what was
changed compared to the previous version?  Please see the second
bullet at
http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
for a detailed explanation.

And you still have a board/mercury/mpq101/config.mk even though I
asked you to get rid of it.

Please also run your patch through checkpatch.pl, remove C++
comments, remove deads code, do not #undef variables that are not
#defined, use TAB for vertical alignment and fix other Coding Style
issues.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
How can you tell when sour cream goes bad?

[U-Boot] [PATCH v3] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

> 
> And you still have a board/mercury/mpq101/config.mk even
> though I
> asked you to get rid of it.
> 

1. I want to fit an environment and the bootloader into a single flash
sector.
2. Environment must be on the sector boundary, otherwise saveenv won't
rewrite it.
3. If I don't fix up the ppcenv starting address, the resulting u-boot
image will shrink by the environment size and won't start on sector
boundary itself.
4. Other boards use handcrafted ld scripts to fit environments at right
boundaries.

That's why I need the LDFLAGS in question.
If not in config.mk, where am I supposed to put them?
Custom ld script is definitely an overshoot in this and other similar
cases.



      

[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

> > In which case, why are not these used when writing
> config values to DDR
> > registers (for instance) even in some very recently
> added boards, such as
> > p2020ds?
> 
> Because this escaped review?
> 
> Can you please point out where this was missed, so it can
> be fixed?
> 

Some of the boards in question:

atum8548
mpc8540
pm854/6
sbc8560
sbc8641d
socrates
mpc8536ds
mpc8540ads
mpc8560ads
mpc8572ds
mpc8610hpdc
mpc8641hpcn
p2020ds
tqm85xx





      

[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Wolfgang Denk]

Dear Alex Dubov,

In message <328503.45731.qm@web37602.mail.mud.yahoo.com> you wrote:
> 
> > Can you please point out where this was missed, so it can
> > be fixed?
> > 
> 
> Some of the boards in question:
> 
> atum8548
> mpc8540
> pm854/6
> sbc8560
> sbc8641d
> socrates
> mpc8536ds
> mpc8540ads
> mpc8560ads
> mpc8572ds
> mpc8610hpdc
> mpc8641hpcn
> p2020ds
> tqm85xx

Could you please be a bit more specific, i. e. like quoting file names
and line numbers?

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If it has syntax, it isn't user friendly.

[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

> > 
> > atum8548
> > mpc8540
> > pm854/6
> > sbc8560
> > sbc8641d
> > socrates
> > mpc8536ds
> > mpc8540ads
> > mpc8560ads
> > mpc8572ds
> > mpc8610hpdc
> > mpc8641hpcn
> > p2020ds
> > tqm85xx
> 
> Could you please be a bit more specific, i. e. like quoting
> file names
> and line numbers?
> 

These were produced by 
grep -nr ddr\-\> board/ | grep -v out_be

I can attach a listing, but it should be quicker this way.
Up until now it seemed a rather common practice to initialize ddr
controllers directly, bypassing io accessors.



      

[U-Boot] [PATCH v3] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Wolfgang Denk]

Dear Alex Dubov,

In message <546160.74882.qm@web37605.mail.mud.yahoo.com> you wrote:
> 
> 1. I want to fit an environment and the bootloader into a single flash
> sector.

This is a very bad idea as it will open a window brick your system at
each and every "saveenv" command.

I strongly recommend not to do that.

> 3. If I don't fix up the ppcenv starting address, the resulting u-boot
> image will shrink by the environment size and won't start on sector
> boundary itself.
> 4. Other boards use handcrafted ld scripts to fit environments at right
> boundaries.

If you stop doing 1., all other problems will just disappear.

> That's why I need the LDFLAGS in question.
> If not in config.mk, where am I supposed to put them?
> Custom ld script is definitely an overshoot in this and other similar
> cases.

If you really insist in such an unreliablke configuration, a custom
linker script would IMO be better, as it would make the image layout
more visible.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
God may be subtle, but He isn't plain mean.         - Albert Einstein

[U-Boot] [PATCH v3] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

> > 
> > 1. I want to fit an environment and the bootloader
> into a single flash
> > sector.
> 
> This is a very bad idea as it will open a window brick your
> system at
> each and every "saveenv" command.
> 
> I strongly recommend not to do that.

This issue is well understood.
Yet, we are talking an industrial mezzanine card here, of variety which
is put into the (ups-backed in most cases) rack once and forgotten.

If it was a consumer or developer oriented device, I, of course, would
use a safer approach. From what I've seen, this is more or less in line
with many other boards already supported by u-boot.

> 
> If you stop doing 1., all other problems will just
> disappear.

Unfortunately, these boards have flash chips without small boot blocks,
and considering the nature of typical board usage (as described) vs
value of some additional flash space, I see it as a reasonable trade-off.

> 
> 
> If you really insist in such an unreliablke configuration,
> a custom
> linker script would IMO be better, as it would make the
> image layout
> more visible.

Typical ld script is rather largish with many details of no direct
relevance to any specific board. Single flag modifying the section offset
has the advantage of being concise and immediately visible.

I will, of course, look at it again.



      

[U-Boot] [PATCH v4] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
memory, real time clock and additional serial EEPROM on i2c bus (enabled).
USB controller is available, but not presently enabled.

Additional board information is available at:
http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx

Environment is configured to precede the actual u-boot image so that it's
located at the beginning of flash erase block (made necessary by the recent
changes to the embedded environment handling).

Signed-off-by: Alex Dubov <oakad@yahoo.com>
---
Changes for v4:
   - Replace config.mk supplied linker flags with custom linker script.
   - Fix checkpatch errors.
Changes for v3:
   - Use io accessor functions for all mmio accesses.
   - Add configuration options for RTC and EEPROM on I2C buses.
Changes for v2:
   - Remove some stale configuration code from board initialization functions.

 MAINTAINERS                     |    3 +
 board/mercury/mpq101/Makefile   |   53 +++++
 board/mercury/mpq101/law.c      |   55 ++++++
 board/mercury/mpq101/mpq101.c   |  140 ++++++++++++++
 board/mercury/mpq101/tlb.c      |   82 ++++++++
 board/mercury/mpq101/u-boot.lds |  132 +++++++++++++
 boards.cfg                      |    1 +
 include/configs/mpq101.h        |  398 +++++++++++++++++++++++++++++++++++++++
 8 files changed, 864 insertions(+), 0 deletions(-)
 create mode 100644 board/mercury/mpq101/Makefile
 create mode 100644 board/mercury/mpq101/law.c
 create mode 100644 board/mercury/mpq101/mpq101.c
 create mode 100644 board/mercury/mpq101/tlb.c
 create mode 100644 board/mercury/mpq101/u-boot.lds
 create mode 100644 include/configs/mpq101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index d7cd09c..220c39d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -138,6 +138,9 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260		MPC8260
 
+Alex Dubov <oakad@yahoo.com>
+	mpq101		MPC8548
+
 Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX
diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile
new file mode 100644
index 0000000..58bc1b3
--- /dev/null
+++ b/board/mercury/mpq101/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c
new file mode 100644
index 0000000..726b5c2
--- /dev/null
+++ b/board/mercury/mpq101/law.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x1fff_ffff     DDR                     SYS_SDRAM_SIZE
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
+		LAW_TRGT_IF_DDR_1),
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
+		LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/mercury/mpq101/mpq101.c b/board/mercury/mpq101/mpq101.c
new file mode 100644
index 0000000..8d9b518
--- /dev/null
+++ b/board/mercury/mpq101/mpq101.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+unsigned long get_clock_freq(void)
+{
+	return 33000000;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init(void)
+{
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+}
+
+int checkboard(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+	putc('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+	phys_size_t dram_size = 0;
+	const char *p_mode = getenv("perf_mode");
+
+	puts("Initializing....");
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (p_mode && !strcmp("performance", p_mode)) {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
+	} else {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	}
+
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
+
+	asm("sync;isync");
+	udelay(500);
+
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+	asm("sync; isync");
+	udelay(500);
+
+	dram_size = setup_ddr_tlbs(1ull << (CONFIG_SYS_SDRAM_SIZE_LOG - 20));
+
+	puts("    DDR: ");
+
+	return get_ram_size(0, dram_size << 20);
+}
+
+
+void pci_init_board(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+
+#endif
diff --git a/board/mercury/mpq101/tlb.c b/board/mercury/mpq101/tlb.c
new file mode 100644
index 0000000..3e3d280
--- /dev/null
+++ b/board/mercury/mpq101/tlb.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	256M	Non-cacheable, guarded
+	 * 0xf0000000	256M	LBC (FLASH included)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+		      CONFIG_SYS_LBC_OPTION_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 1:	1M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+	/*
+	 * TLB 2:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+		      CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/mercury/mpq101/u-boot.lds b/board/mercury/mpq101/u-boot.lds
new file mode 100644
index 0000000..5b668b0
--- /dev/null
+++ b/board/mercury/mpq101/u-boot.lds
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+#include <config.h>
+
+OUTPUT_ARCH(powerpc)
+
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  /* To simplify mass deployment, environment precedes the monitor text in the
+   * same flash sector.
+   */
+  .ppcenv CONFIG_ENV_ADDR : { *(.ppcenv) }
+  .text      :
+  {
+    *(.text*)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg RESET_VECTOR_ADDRESS - 0xffc :
+  {
+    arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  .resetvec RESET_VECTOR_ADDRESS :
+  {
+    KEEP(*(.resetvec))
+  } :text = 0xffff
+
+  . = RESET_VECTOR_ADDRESS + 0x4;
+
+  /*
+   * Make sure that the bss segment isn't linked at 0x0, otherwise its
+   * address won't be updated during relocation fixups.  Note that
+   * this is a temporary fix.  Code to dynamically the fixup the bss
+   * location will be added in the future.  When the bss relocation
+   * fixup code is present this workaround should be removed.
+   */
+#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
+  . |= 0x10;
+#endif
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss*)
+   *(.bss*)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/boards.cfg b/boards.cfg
index 0574bb2..7d7814f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -502,6 +502,7 @@ P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freesca
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SPIFLASH
 P4080DS                      powerpc     mpc85xx     corenet_ds          freescale
+mpq101                       powerpc     mpc85xx     mpq101              mercury        -           mpq101:SYS_LDSCRIPT=board/mercury/mpq101/u-boot.lds
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M
diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h
new file mode 100644
index 0000000..33d6b69
--- /dev/null
+++ b/include/configs/mpq101.h
@@ -0,0 +1,398 @@
+/*
+ * Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Merury Computers MPQ101 board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+# define CONFIG_PHYS_64BIT 1
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE      1 /* BOOKE */
+#define CONFIG_E500       1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx    1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548    1 /* MPC8548 specific */
+#define CONFIG_MPQ101     1 /* MPQ101 board specific */
+
+#define CONFIG_RIO        1
+#define CONFIG_TSEC_ENET  1 /* tsec ethernet support */
+#define CONFIG_INTERRUPTS 1 /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW    1 /* Use common FSL init code */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE   1 /* toggle L2 cache */
+#define CONFIG_BTB        1 /* toggle branch predition */
+
+#define CONFIG_PANIC_HANG 1
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_ADDR_MAP         1
+# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_CCSRBAR         0xe0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_CCSRBAR_PHYS   0xfe0000000ull
+#else
+# define CONFIG_SYS_CCSRBAR_PHYS   CONFIG_SYS_CCSRBAR
+#endif
+
+#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1  /* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE        0xDeadBeef
+#define CONFIG_SYS_DDR_SDRAM_BASE    0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE        CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS   1
+#define CONFIG_DIMM_SLOTS_PER_CTLR   1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* Fixed 512MB DDR2 parameters */
+#define CONFIG_SYS_SDRAM_SIZE_LOG    29 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS      0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG    0x80014102
+#define CONFIG_SYS_DDR_TIMING_3      0x00010000
+#define CONFIG_SYS_DDR_TIMING_0      0x00260802
+#define CONFIG_SYS_DDR_TIMING_1      0x5c47a432
+#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
+#define CONFIG_SYS_DDR_TIMING_2      0x03984cce
+#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
+#define CONFIG_SYS_DDR_MODE_1        0x00400442
+#define CONFIG_SYS_DDR_MODE_1_PERF   0x00480432
+#define CONFIG_SYS_DDR_MODE_2        0x00000000
+#define CONFIG_SYS_DDR_MODE_2_PERF   0x00000000
+#define CONFIG_SYS_DDR_INTERVAL      0x08200100
+#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
+#define CONFIG_SYS_DDR_CLK_CTRL      0x03800000
+#define CONFIG_SYS_DDR_CONTROL       0xc3008000 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2      0x04400000
+
+#define CONFIG_SYS_ALT_MEMTEST       1
+#define CONFIG_SYS_MEMTEST_START     0x0ff00000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END       0x0ffffffc
+
+/*
+ * RAM definitions
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK   1
+#define CONFIG_SYS_INIT_RAM_ADDR   0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE   0x4000     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+				    - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN     (256 * 1024)  /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN      (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+
+
+/*
+ * FLASH on the Local Bus
+ * One bank, 128M, using the CFI driver.
+ */
+#define CONFIG_SYS_BOOT_BLOCK 0xf8000000            /* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
+#else
+# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+/* 0xf8001801 */
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+			       | BR_PS_32 | BR_V)
+
+/* 0xf8006ff7 */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
+			       | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+			       | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
+			       | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FLASH_SHOW_PROGRESS     45   /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     1    /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      512  /* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500   /* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER        1
+#define CONFIG_SYS_FLASH_CFI           1
+#define CONFIG_SYS_FLASH_EMPTY_INFO    1
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 1
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash.
+ */
+#define CONFIG_ASSUME_AMD_FLASH        1
+
+/*
+ * Environment parameters
+ */
+#define CONFIG_ENV_IS_IN_FLASH  1
+#define CONFIG_ENV_OVERWRITE    1
+#define CONFIG_SYS_USE_PPCENV   1
+#define ENV_IS_EMBEDDED         1
+#define CONFIG_ENV_SECT_SIZE    0x40000   /* 256K */
+#define CONFIG_ENV_SIZE         0x800
+
+/* Environment at the start of flash sector, before text. */
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_TEXT_BASE    0xfffc0800
+
+/*
+ * Cypress CY7C67200 USB controller on the Local Bus.
+ * Not supported by u-boot at present.
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
+#else
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
+#endif
+
+/* 0xf0001001 */
+#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
+			       | BR_PS_16 | BR_V)
+
+/* fffff002 */
+#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
+			       | OR_GPCM_BCTLD | OR_GPCM_EHTR)
+
+/*
+ * Serial Ports
+ */
+#define CONFIG_CONS_INDEX           2
+#define CONFIG_SYS_NS16550          1
+#define CONFIG_SYS_NS16550_SERIAL   1
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE   {300, 600, 1200, 2400, 4800, 9600, \
+				     19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1     (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2     (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C buses and peripherals
+ */
+#define CONFIG_FSL_I2C         1      /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C        1      /* I2C with hardware support*/
+#define CONFIG_I2C_MULTI_BUS   1
+#define CONFIG_SYS_I2C_SPEED   400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE   0x7f
+#define CONFIG_SYS_I2C_OFFSET  0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/* I2C RTC - M41T81 */
+#define CONFIG_RTC_M41T62                     1
+#define CONFIG_SYS_I2C_RTC_ADDR               0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR           2000
+
+/* I2C EEPROM - 24C256 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR            0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        2
+#define CONFIG_SYS_EEPROM_BUS_NUM             1
+
+/*
+ * RapidIO MMU
+ */
+#ifdef CONFIG_RIO
+
+# define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
+
+# ifdef CONFIG_PHYS_64BIT
+#  define CONFIG_SYS_RIO_MEM_PHYS 0xfc0000000ull
+# else
+#  define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
+# endif
+
+# define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
+
+#endif
+
+/*
+ * Ethernet
+ */
+#ifdef CONFIG_TSEC_ENET
+
+# ifndef CONFIG_NET_MULTI
+#  define CONFIG_NET_MULTI       1
+# endif
+
+# define CONFIG_MII              1 /* MII PHY management */
+# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+
+# define CONFIG_TSEC1            1
+# define CONFIG_TSEC1_NAME       "eTSEC0"
+# define TSEC1_PHY_ADDR          0x10
+# define TSEC1_PHYIDX            0
+# define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC2            1
+# define CONFIG_TSEC2_NAME       "eTSEC1"
+# define TSEC2_PHY_ADDR          0x11
+# define TSEC2_PHYIDX            0
+# define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC3            1
+# define CONFIG_TSEC3_NAME       "eTSEC2"
+# define TSEC3_PHY_ADDR          0x12
+# define TSEC3_PHYIDX            0
+# define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC4            1
+# define CONFIG_TSEC4_NAME       "eTSEC3"
+# define TSEC4_PHY_ADDR          0x13
+# define TSEC4_PHYIDX            0
+# define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+# define CONFIG_ETHPRIME         "eTSEC0"
+# define CONFIG_PHY_GIGE         1 /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_JFFS2
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT             1
+#define CONFIG_OF_BOARD_SETUP        1
+#define CONFIG_OF_STDOUT_VIA_ALIAS   1
+
+/* new uImage format support */
+#define CONFIG_FIT                   1
+#define CONFIG_FIT_VERBOSE           1 /* enable fit_format_{error,warning}() */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER       1
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+# define CONFIG_SYS_PROMPT_HUSH_PS2  "> "
+#endif
+
+#define CONFIG_LOADS_ECHO            1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_SYS_LONGHELP          1 /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING       1 /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE         1 /* add autocompletion support */
+
+#define CONFIG_SYS_LOAD_ADDR         0x2000000    /* default load address */
+#define CONFIG_SYS_PROMPT            "MPQ-101=> " /* Monitor Command Prompt */
+
+/* Console I/O Buffer Size */
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE 1024
+#else
+# define CONFIG_SYS_CBSIZE 256
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
+# define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
+#endif
+
+/*
+ * Basic Environment Configuration
+ */
+#define CONFIG_BAUDRATE  115200
+#define CONFIG_BOOTDELAY 5            /* -1 disables auto-boot */
+
+/*default location for tftp and bootm*/
+#define CONFIG_LOADADDR  CONFIG_SYS_LOAD_ADDR
+
+#endif /* __CONFIG_H */
-- 
1.7.3.2



      

[U-Boot] [PATCH v4] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Kumar Gala]

On Jan 14, 2011, at 3:10 AM, Alex Dubov wrote:

> Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
> processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
> memory, real time clock and additional serial EEPROM on i2c bus (enabled).
> USB controller is available, but not presently enabled.
> 
> Additional board information is available at:
> http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx
> 
> Environment is configured to precede the actual u-boot image so that it's
> located at the beginning of flash erase block (made necessary by the recent
> changes to the embedded environment handling).
> 
> Signed-off-by: Alex Dubov <oakad@yahoo.com>
> ---
> Changes for v4:
>   - Replace config.mk supplied linker flags with custom linker script.
>   - Fix checkpatch errors.
> Changes for v3:
>   - Use io accessor functions for all mmio accesses.
>   - Add configuration options for RTC and EEPROM on I2C buses.
> Changes for v2:
>   - Remove some stale configuration code from board initialization functions.
> 
> MAINTAINERS                     |    3 +
> board/mercury/mpq101/Makefile   |   53 +++++
> board/mercury/mpq101/law.c      |   55 ++++++
> board/mercury/mpq101/mpq101.c   |  140 ++++++++++++++
> board/mercury/mpq101/tlb.c      |   82 ++++++++
> board/mercury/mpq101/u-boot.lds |  132 +++++++++++++
> boards.cfg                      |    1 +
> include/configs/mpq101.h        |  398 +++++++++++++++++++++++++++++++++++++++
> 8 files changed, 864 insertions(+), 0 deletions(-)
> create mode 100644 board/mercury/mpq101/Makefile
> create mode 100644 board/mercury/mpq101/law.c
> create mode 100644 board/mercury/mpq101/mpq101.c
> create mode 100644 board/mercury/mpq101/tlb.c
> create mode 100644 board/mercury/mpq101/u-boot.lds
> create mode 100644 include/configs/mpq101.h

Can you update this against the u-boot-mpc85xx.git and use the new common SRIO init code

I assume customer linker script is because of where you have the environment.  If so might be useful to add that to the commit comment.

- k

[U-Boot] [PATCH v4] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Kumar Gala]

On Jan 14, 2011, at 3:10 AM, Alex Dubov wrote:

> Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
> processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
> memory, real time clock and additional serial EEPROM on i2c bus (enabled).
> USB controller is available, but not presently enabled.
> 
> Additional board information is available at:
> http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx
> 
> Environment is configured to precede the actual u-boot image so that it's
> located at the beginning of flash erase block (made necessary by the recent
> changes to the embedded environment handling).
> 
> Signed-off-by: Alex Dubov <oakad@yahoo.com>
> ---
> Changes for v4:
>   - Replace config.mk supplied linker flags with custom linker script.
>   - Fix checkpatch errors.
> Changes for v3:
>   - Use io accessor functions for all mmio accesses.
>   - Add configuration options for RTC and EEPROM on I2C buses.
> Changes for v2:
>   - Remove some stale configuration code from board initialization functions.
> 
> MAINTAINERS                     |    3 +
> board/mercury/mpq101/Makefile   |   53 +++++
> board/mercury/mpq101/law.c      |   55 ++++++
> board/mercury/mpq101/mpq101.c   |  140 ++++++++++++++
> board/mercury/mpq101/tlb.c      |   82 ++++++++
> board/mercury/mpq101/u-boot.lds |  132 +++++++++++++
> boards.cfg                      |    1 +
> include/configs/mpq101.h        |  398 +++++++++++++++++++++++++++++++++++++++
> 8 files changed, 864 insertions(+), 0 deletions(-)
> create mode 100644 board/mercury/mpq101/Makefile
> create mode 100644 board/mercury/mpq101/law.c
> create mode 100644 board/mercury/mpq101/mpq101.c
> create mode 100644 board/mercury/mpq101/tlb.c
> create mode 100644 board/mercury/mpq101/u-boot.lds
> create mode 100644 include/configs/mpq101.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d7cd09c..220c39d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -138,6 +138,9 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
> 
> 	sbc8260		MPC8260
> 
> +Alex Dubov <oakad@yahoo.com>
> +	mpq101		MPC8548
> +
> Dirk Eibach <eibach@gdsys.de>
> 
> 	devconcenter	PPC460EX
> diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile
> new file mode 100644
> index 0000000..58bc1b3
> --- /dev/null
> +++ b/board/mercury/mpq101/Makefile
> @@ -0,0 +1,53 @@
> +#
> +# Copyright 2007 Freescale Semiconductor, Inc.
> +# (C) Copyright 2001-2006
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB	= $(obj)lib$(BOARD).o
> +
> +COBJS-y	+= $(BOARD).o
> +COBJS-y	+= law.o
> +COBJS-y	+= tlb.o
> +
> +SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
> +OBJS	:= $(addprefix $(obj),$(COBJS-y))
> +SOBJS	:= $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
> +	$(call cmd_link_o_target, $(OBJS))
> +
> +clean:
> +	rm -f $(OBJS) $(SOBJS)
> +
> +distclean:	clean
> +	rm -f $(LIB) core *.bak .depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c
> new file mode 100644
> index 0000000..726b5c2
> --- /dev/null
> +++ b/board/mercury/mpq101/law.c
> @@ -0,0 +1,55 @@
> +/*
> + * Copyright 2008 Freescale Semiconductor, Inc.
> + *
> + * (C) Copyright 2000
> + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/fsl_law.h>
> +#include <asm/mmu.h>
> +
> +/*
> + * LAW(Local Access Window) configuration:
> + *
> + * 0x0000_0000     0x1fff_ffff     DDR                     SYS_SDRAM_SIZE
> + * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
> + * 0xe000_0000     0xe000_ffff     CCSR                    1M
> + * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
> + *
> + * Notes:
> + *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
> + *    If flash is 8M at default position (last 8M), no LAW needed.
> + *
> + * LAW 0 is reserved for boot mapping
> + */
> +
> +struct law_entry law_table[] = {
> +	SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
> +		LAW_TRGT_IF_DDR_1),
> +#ifdef CONFIG_SYS_RIO_MEM_PHYS
> +	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
> +#endif
> +	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
> +		LAW_TRGT_IF_LBC)
> +};
> +
> +int num_law_entries = ARRAY_SIZE(law_table);
> diff --git a/board/mercury/mpq101/mpq101.c b/board/mercury/mpq101/mpq101.c
> new file mode 100644
> index 0000000..8d9b518
> --- /dev/null
> +++ b/board/mercury/mpq101/mpq101.c
> @@ -0,0 +1,140 @@
> +/*
> + * (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/processor.h>
> +#include <asm/mmu.h>
> +#include <asm/immap_85xx.h>
> +#include <asm/fsl_law.h>
> +#include <asm/io.h>
> +#include <miiphy.h>
> +#include <libfdt.h>
> +#include <fdt_support.h>
> +
> +unsigned long get_clock_freq(void)
> +{
> +	return 33000000;
> +}
> +
> +/*
> + * Initialize Local Bus
> + */
> +void local_bus_init(void)
> +{
> +	fsl_lbc_t *lbc = LBC_BASE_ADDR;
> +
> +	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
> +	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
> +}
> +
> +int checkboard(void)
> +{
> +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
> +
> +	puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
> +#ifdef CONFIG_PHYS_64BIT
> +	puts("(36-bit addrmap) ");
> +#endif
> +	putc('\n');
> +
> +	/*
> +	 * Initialize local bus.
> +	 */
> +	local_bus_init();
> +
> +	/*
> +	 * Hack TSEC 3 and 4 IO voltages.
> +	 */
> +	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
> +
> +	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
> +	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
> +	return 0;
> +}
> +
> +phys_size_t initdram(int board_type)
> +{
> +	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
> +	phys_size_t dram_size = 0;
> +	const char *p_mode = getenv("perf_mode");
> +
> +	puts("Initializing....");
> +
> +	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
> +	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
> +
> +	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
> +	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
> +
> +	if (p_mode && !strcmp("performance", p_mode)) {
> +		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
> +		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
> +		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
> +		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
> +		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
> +	} else {
> +		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
> +		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
> +		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
> +		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
> +		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
> +	}
> +
> +	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
> +	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
> +
> +	asm("sync;isync");
> +	udelay(500);
> +
> +	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
> +	asm("sync; isync");
> +	udelay(500);
> +
> +	dram_size = setup_ddr_tlbs(1ull << (CONFIG_SYS_SDRAM_SIZE_LOG - 20));
> +
> +	puts("    DDR: ");
> +
> +	return get_ram_size(0, dram_size << 20);
> +}
> +
> +
> +void pci_init_board(void)
> +{
> +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +
> +	/* PCI is disabled */
> +	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
> +				| MPC85xx_DEVDISR_PCI1
> +				| MPC85xx_DEVDISR_PCI2
> +				| MPC85xx_DEVDISR_PCIE);
> +}

> diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h
> new file mode 100644
> index 0000000..33d6b69
> --- /dev/null
> +++ b/include/configs/mpq101.h
> @@ -0,0 +1,398 @@
> +/*
> + * Copyright 2011 Alex Dubov <oakad@yahoo.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * Merury Computers MPQ101 board configuration file
> + *
> + */
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#ifdef CONFIG_36BIT
> +# define CONFIG_PHYS_64BIT 1
> +#endif
> +
> +/* High Level Configuration Options */
> +#define CONFIG_BOOKE      1 /* BOOKE */
> +#define CONFIG_E500       1 /* BOOKE e500 family */
> +#define CONFIG_MPC85xx    1 /* MPC8540/60/55/41/48 */
> +#define CONFIG_MPC8548    1 /* MPC8548 specific */
> +#define CONFIG_MPQ101     1 /* MPQ101 board specific */
> +
> +#define CONFIG_RIO        1
> +#define CONFIG_TSEC_ENET  1 /* tsec ethernet support */
> +#define CONFIG_INTERRUPTS 1 /* enable pci, srio, ddr interrupts */
> +#define CONFIG_FSL_LAW    1 /* Use common FSL init code */
> +
> +/*
> + * These can be toggled for performance analysis, otherwise use default.
> + */
> +#define CONFIG_L2_CACHE   1 /* toggle L2 cache */
> +#define CONFIG_BTB        1 /* toggle branch predition */
> +
> +#define CONFIG_PANIC_HANG 1
> +
> +/*
> + * Only possible on E500 Version 2 or newer cores.
> + */
> +#define CONFIG_ENABLE_36BIT_PHYS 1
> +
> +#ifdef CONFIG_PHYS_64BIT
> +# define CONFIG_ADDR_MAP         1
> +# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
> +#endif
> +
> +#ifndef __ASSEMBLY__
> +extern unsigned long get_clock_freq(void);
> +#endif
> +
> +#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
> +
> +/*

You don't really need a function here for get_clock_freq() you can just:

#define CONFIG_SYS_CLK_FREQ 33000000

- k

[U-Boot] [PATCH v4] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

> > 
> > Environment is configured to precede the actual u-boot
> image so that it's
> > located at the beginning of flash erase block (made
> necessary by the recent
> > changes to the embedded environment handling).
> > 

> 
> I assume customer linker script is because of where you
> have the environment.? If so might be useful to add
> that to the commit comment.
> 

I was under impression that commit message and comment in the linker script
make it rather clear.



      

[U-Boot] [PATCH v5] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
memory, real time clock and additional serial EEPROM on i2c bus (enabled).
USB controller is available, but not presently enabled.

Additional board information is available at:
http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx

Environment is configured to precede the actual u-boot image so that it's
located at the beginning of flash erase block (made necessary by the recent
changes to the embedded environment handling). This is achieved by means of
custom ld script.

Signed-off-by: Alex Dubov <oakad@yahoo.com>
---
Changes for v5:
   - Use new common SRIO configuration definitions.
   - Replace initdram() with platform required fixed_sdram().
   - Don't use get_ram_size() in fixed_sdram() as TLBs are set after it exits
     by common platform code.
Changes for v4:
   - Replace config.mk supplied linker flags with custom linker script.
   - Fix checkpatch errors.
Changes for v3:
   - Use io accessor functions for all mmio accesses.
   - Add configuration options for RTC and EEPROM on I2C buses.
Changes for v2:
   - Remove some stale configuration code from board initialization functions.

 MAINTAINERS                     |    3 +
 board/mercury/mpq101/Makefile   |   53 ++++++
 board/mercury/mpq101/law.c      |   52 +++++
 board/mercury/mpq101/mpq101.c   |  129 +++++++++++++
 board/mercury/mpq101/tlb.c      |   82 ++++++++
 board/mercury/mpq101/u-boot.lds |  132 +++++++++++++
 boards.cfg                      |    1 +
 include/configs/mpq101.h        |  391 +++++++++++++++++++++++++++++++++++++++
 8 files changed, 843 insertions(+), 0 deletions(-)
 create mode 100644 board/mercury/mpq101/Makefile
 create mode 100644 board/mercury/mpq101/law.c
 create mode 100644 board/mercury/mpq101/mpq101.c
 create mode 100644 board/mercury/mpq101/tlb.c
 create mode 100644 board/mercury/mpq101/u-boot.lds
 create mode 100644 include/configs/mpq101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index a799037..d0fc7dc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -138,6 +138,9 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260		MPC8260
 
+Alex Dubov <oakad@yahoo.com>
+	mpq101		MPC8548
+
 Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX
diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile
new file mode 100644
index 0000000..58bc1b3
--- /dev/null
+++ b/board/mercury/mpq101/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c
new file mode 100644
index 0000000..0e23a6a
--- /dev/null
+++ b/board/mercury/mpq101/law.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x1fff_ffff     DDR                     SYS_SDRAM_SIZE
+ * 0xc000_0000     0xdfff_ffff     RapidIO (set elsewhere) 512M
+ * 0xe000_0000     0xe000_ffff     CCSR    (set elsewhere) 1M
+ * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
+		LAW_TRGT_IF_DDR_1),
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
+		LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/mercury/mpq101/mpq101.c b/board/mercury/mpq101/mpq101.c
new file mode 100644
index 0000000..e02e87f
--- /dev/null
+++ b/board/mercury/mpq101/mpq101.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init(void)
+{
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+}
+
+int checkboard(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+	putc('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+phys_size_t fixed_sdram(void)
+{
+	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+	const char *p_mode = getenv("perf_mode");
+
+	puts("Initializing....");
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (p_mode && !strcmp("performance", p_mode)) {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
+	} else {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	}
+
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
+
+	asm("sync;isync");
+	udelay(500);
+
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+	asm("sync; isync");
+	udelay(500);
+
+	return ((phys_size_t)1) << CONFIG_SYS_SDRAM_SIZE_LOG;
+}
+
+void pci_init_board(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+
+#endif
diff --git a/board/mercury/mpq101/tlb.c b/board/mercury/mpq101/tlb.c
new file mode 100644
index 0000000..3e3d280
--- /dev/null
+++ b/board/mercury/mpq101/tlb.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	256M	Non-cacheable, guarded
+	 * 0xf0000000	256M	LBC (FLASH included)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+		      CONFIG_SYS_LBC_OPTION_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 1:	1M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+	/*
+	 * TLB 2:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+		      CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/mercury/mpq101/u-boot.lds b/board/mercury/mpq101/u-boot.lds
new file mode 100644
index 0000000..3af0274
--- /dev/null
+++ b/board/mercury/mpq101/u-boot.lds
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+#include <config.h>
+
+OUTPUT_ARCH(powerpc)
+
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  /* To simplify mass deployment, environment precedes the monitor text in the
+   * same flash sector.
+   */
+  .ppcenv CONFIG_ENV_ADDR : { *(.ppcenv) }
+  .text      :
+  {
+    *(.text*)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg RESET_VECTOR_ADDRESS - 0xffc :
+  {
+    arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  .resetvec RESET_VECTOR_ADDRESS :
+  {
+    KEEP(*(.resetvec))
+  } :text = 0xffff
+
+  . = RESET_VECTOR_ADDRESS + 0x4;
+
+  /*
+   * Make sure that the bss segment isn't linked at 0x0, otherwise its
+   * address won't be updated during relocation fixups.  Note that
+   * this is a temporary fix.  Code to dynamically the fixup the bss
+   * location will be added in the future.  When the bss relocation
+   * fixup code is present this workaround should be removed.
+   */
+#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
+  . |= 0x10;
+#endif
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss*)
+   *(.bss*)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/boards.cfg b/boards.cfg
index 3497408..0f94969 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -495,6 +495,7 @@ P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freesca
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SPIFLASH
 P4080DS                      powerpc     mpc85xx     corenet_ds          freescale
+mpq101                       powerpc     mpc85xx     mpq101              mercury        -           mpq101:SYS_LDSCRIPT=board/mercury/mpq101/u-boot.lds
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M
diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h
new file mode 100644
index 0000000..4996c89
--- /dev/null
+++ b/include/configs/mpq101.h
@@ -0,0 +1,391 @@
+/*
+ * Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Merury Computers MPQ101 board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+# define CONFIG_PHYS_64BIT 1
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE      1 /* BOOKE */
+#define CONFIG_E500       1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx    1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548    1 /* MPC8548 specific */
+#define CONFIG_MPQ101     1 /* MPQ101 board specific */
+
+#define CONFIG_SYS_SRIO   1 /* enable serial RapidIO */
+#define CONFIG_TSEC_ENET  1 /* tsec ethernet support */
+#define CONFIG_INTERRUPTS 1 /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW    1 /* Use common FSL init code */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE   1 /* toggle L2 cache */
+#define CONFIG_BTB        1 /* toggle branch predition */
+
+#define CONFIG_PANIC_HANG 1
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS   1
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_ADDR_MAP           1
+# define CONFIG_SYS_NUM_ADDR_MAP   16 /* number of TLB1 entries */
+#endif
+
+
+#define CONFIG_SYS_CLK_FREQ        33000000 /* sysclk for MPC85xx */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_CCSRBAR         0xe0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_CCSRBAR_PHYS   0xfe0000000ull
+#else
+# define CONFIG_SYS_CCSRBAR_PHYS   CONFIG_SYS_CCSRBAR
+#endif
+
+#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1  /* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE        0xDeadBeef
+#define CONFIG_SYS_DDR_SDRAM_BASE    0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE        CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS   1
+#define CONFIG_DIMM_SLOTS_PER_CTLR   1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* Fixed 512MB DDR2 parameters */
+#define CONFIG_SYS_SDRAM_SIZE_LOG    29 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS      0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG    0x80014102
+#define CONFIG_SYS_DDR_TIMING_3      0x00010000
+#define CONFIG_SYS_DDR_TIMING_0      0x00260802
+#define CONFIG_SYS_DDR_TIMING_1      0x5c47a432
+#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
+#define CONFIG_SYS_DDR_TIMING_2      0x03984cce
+#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
+#define CONFIG_SYS_DDR_MODE_1        0x00400442
+#define CONFIG_SYS_DDR_MODE_1_PERF   0x00480432
+#define CONFIG_SYS_DDR_MODE_2        0x00000000
+#define CONFIG_SYS_DDR_MODE_2_PERF   0x00000000
+#define CONFIG_SYS_DDR_INTERVAL      0x08200100
+#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
+#define CONFIG_SYS_DDR_CLK_CTRL      0x03800000
+#define CONFIG_SYS_DDR_CONTROL       0xc3008000 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2      0x04400000
+
+#define CONFIG_SYS_ALT_MEMTEST       1
+#define CONFIG_SYS_MEMTEST_START     0x0ff00000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END       0x0ffffffc
+
+/*
+ * RAM definitions
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK   1
+#define CONFIG_SYS_INIT_RAM_ADDR   0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE   0x4000     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+				    - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN     (256 * 1024)  /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN      (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+
+
+/*
+ * FLASH on the Local Bus
+ * One bank, 128M, using the CFI driver.
+ */
+#define CONFIG_SYS_BOOT_BLOCK 0xf8000000            /* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
+#else
+# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+/* 0xf8001801 */
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+			       | BR_PS_32 | BR_V)
+
+/* 0xf8006ff7 */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
+			       | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+			       | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
+			       | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FLASH_SHOW_PROGRESS     45   /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     1    /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      512  /* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500   /* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER        1
+#define CONFIG_SYS_FLASH_CFI           1
+#define CONFIG_SYS_FLASH_EMPTY_INFO    1
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 1
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash.
+ */
+#define CONFIG_ASSUME_AMD_FLASH        1
+
+/*
+ * Environment parameters
+ */
+#define CONFIG_ENV_IS_IN_FLASH  1
+#define CONFIG_ENV_OVERWRITE    1
+#define CONFIG_SYS_USE_PPCENV   1
+#define ENV_IS_EMBEDDED         1
+#define CONFIG_ENV_SECT_SIZE    0x40000   /* 256K */
+#define CONFIG_ENV_SIZE         0x800
+
+/* Environment at the start of flash sector, before text. */
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_TEXT_BASE    0xfffc0800
+
+/*
+ * Cypress CY7C67200 USB controller on the Local Bus.
+ * Not supported by u-boot at present.
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
+#else
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
+#endif
+
+/* 0xf0001001 */
+#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
+			       | BR_PS_16 | BR_V)
+
+/* fffff002 */
+#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
+			       | OR_GPCM_BCTLD | OR_GPCM_EHTR)
+
+/*
+ * Serial Ports
+ */
+#define CONFIG_CONS_INDEX           2
+#define CONFIG_SYS_NS16550          1
+#define CONFIG_SYS_NS16550_SERIAL   1
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE   {300, 600, 1200, 2400, 4800, 9600, \
+				     19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1     (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2     (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C buses and peripherals
+ */
+#define CONFIG_FSL_I2C         1      /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C        1      /* I2C with hardware support*/
+#define CONFIG_I2C_MULTI_BUS   1
+#define CONFIG_SYS_I2C_SPEED   400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE   0x7f
+#define CONFIG_SYS_I2C_OFFSET  0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/* I2C RTC - M41T81 */
+#define CONFIG_RTC_M41T62                     1
+#define CONFIG_SYS_I2C_RTC_ADDR               0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR           2000
+
+/* I2C EEPROM - 24C256 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR            0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        2
+#define CONFIG_SYS_EEPROM_BUS_NUM             1
+
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SRIO1               1
+#define CONFIG_SYS_SRIO1_MEM_VIRT  0xc0000000
+#define CONFIG_SYS_SRIO1_MEM_SIZE  0x20000000 /* 512M */
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
+#else
+# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
+#endif
+
+/*
+ * Ethernet
+ */
+#ifdef CONFIG_TSEC_ENET
+
+# ifndef CONFIG_NET_MULTI
+#  define CONFIG_NET_MULTI       1
+# endif
+
+# define CONFIG_MII              1 /* MII PHY management */
+# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+
+# define CONFIG_TSEC1            1
+# define CONFIG_TSEC1_NAME       "eTSEC0"
+# define TSEC1_PHY_ADDR          0x10
+# define TSEC1_PHYIDX            0
+# define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC2            1
+# define CONFIG_TSEC2_NAME       "eTSEC1"
+# define TSEC2_PHY_ADDR          0x11
+# define TSEC2_PHYIDX            0
+# define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC3            1
+# define CONFIG_TSEC3_NAME       "eTSEC2"
+# define TSEC3_PHY_ADDR          0x12
+# define TSEC3_PHYIDX            0
+# define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC4            1
+# define CONFIG_TSEC4_NAME       "eTSEC3"
+# define TSEC4_PHY_ADDR          0x13
+# define TSEC4_PHYIDX            0
+# define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+# define CONFIG_ETHPRIME         "eTSEC0"
+# define CONFIG_PHY_GIGE         1 /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_JFFS2
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT             1
+#define CONFIG_OF_BOARD_SETUP        1
+#define CONFIG_OF_STDOUT_VIA_ALIAS   1
+
+/* new uImage format support */
+#define CONFIG_FIT                   1
+#define CONFIG_FIT_VERBOSE           1 /* enable fit_format_{error,warning}() */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER       1
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+# define CONFIG_SYS_PROMPT_HUSH_PS2  "> "
+#endif
+
+#define CONFIG_LOADS_ECHO            1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_SYS_LONGHELP          1 /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING       1 /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE         1 /* add autocompletion support */
+
+#define CONFIG_SYS_LOAD_ADDR         0x2000000    /* default load address */
+#define CONFIG_SYS_PROMPT            "MPQ-101=> " /* Monitor Command Prompt */
+
+/* Console I/O Buffer Size */
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE 1024
+#else
+# define CONFIG_SYS_CBSIZE 256
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
+# define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
+#endif
+
+/*
+ * Basic Environment Configuration
+ */
+#define CONFIG_BAUDRATE  115200
+#define CONFIG_BOOTDELAY 5            /* -1 disables auto-boot */
+
+/*default location for tftp and bootm*/
+#define CONFIG_LOADADDR  CONFIG_SYS_LOAD_ADDR
+
+#endif /* __CONFIG_H */
-- 
1.7.3.2



      

[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Wolfgang Denk]

Dear Alex Dubov,

In message <369392.26813.qm@web37607.mail.mud.yahoo.com> you wrote:
> > 
> > Could you please be a bit more specific, i. e. like quoting
> > file names
> > and line numbers?
> > 
> 
> These were produced by 
> grep -nr ddr\-\> board/ | grep -v out_be
> 
> I can attach a listing, but it should be quicker this way.
> Up until now it seemed a rather common practice to initialize ddr
> controllers directly, bypassing io accessors.

Indeed. Even after the recent removal of some boards this list
remains:

	board/freescale/mpc8349itx/mpc8349itx.c
	board/freescale/mpc8536ds/mpc8536ds.c
	board/freescale/mpc8540ads/mpc8540ads.c
	board/freescale/mpc8560ads/mpc8560ads.c
	board/freescale/mpc8569mds/mpc8569mds.c
	board/freescale/mpc8572ds/mpc8572ds.c
	board/freescale/mpc8610hpcd/mpc8610hpcd.c
	board/freescale/mpc8641hpcn/mpc8641hpcn.c
	board/freescale/p2020ds/p2020ds.c
	board/sbc8560/sbc8560.c
	board/sbc8641d/sbc8641d.c
	board/socrates/sdram.c
	board/tqc/tqm85xx/sdram.c

Kumar, Andy - do you have any plans to fix this for the freescale
boards?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I've got a bad feeling about this.

[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Kumar Gala]

On Jan 17, 2011, at 4:38 PM, Wolfgang Denk wrote:

> Dear Alex Dubov,
> 
> In message <369392.26813.qm@web37607.mail.mud.yahoo.com> you wrote:
>>> 
>>> Could you please be a bit more specific, i. e. like quoting
>>> file names
>>> and line numbers?
>>> 
>> 
>> These were produced by 
>> grep -nr ddr\-\> board/ | grep -v out_be
>> 
>> I can attach a listing, but it should be quicker this way.
>> Up until now it seemed a rather common practice to initialize ddr
>> controllers directly, bypassing io accessors.
> 
> Indeed. Even after the recent removal of some boards this list
> remains:
> 
> 	board/freescale/mpc8349itx/mpc8349itx.c
> 	board/freescale/mpc8536ds/mpc8536ds.c
> 	board/freescale/mpc8540ads/mpc8540ads.c
> 	board/freescale/mpc8560ads/mpc8560ads.c
> 	board/freescale/mpc8569mds/mpc8569mds.c
> 	board/freescale/mpc8572ds/mpc8572ds.c
> 	board/freescale/mpc8610hpcd/mpc8610hpcd.c
> 	board/freescale/mpc8641hpcn/mpc8641hpcn.c
> 	board/freescale/p2020ds/p2020ds.c
> 	board/sbc8560/sbc8560.c
> 	board/sbc8641d/sbc8641d.c
> 	board/socrates/sdram.c
> 	board/tqc/tqm85xx/sdram.c
> 
> Kumar, Andy - do you have any plans to fix this for the freescale
> boards?
> 
> Best regards,
> 
> Wolfgang Denk

I don't have an plans to fix this, however we can add it to the TODO list.  Just isn't high priority at this point.

- k

[U-Boot] [PATCH v5] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Kumar Gala]

On Jan 17, 2011, at 1:26 AM, Alex Dubov wrote:

> 
> +/*
> + * Merury Computers MPQ101 board configuration file
> + *
> + */
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#ifdef CONFIG_36BIT
> +# define CONFIG_PHYS_64BIT 1
> +#endif
> +
> +/* High Level Configuration Options */
> +#define CONFIG_BOOKE      1 /* BOOKE */
> +#define CONFIG_E500       1 /* BOOKE e500 family */
> +#define CONFIG_MPC85xx    1 /* MPC8540/60/55/41/48 */
> +#define CONFIG_MPC8548    1 /* MPC8548 specific */
> +#define CONFIG_MPQ101     1 /* MPQ101 board specific */
> +
> +#define CONFIG_SYS_SRIO   1 /* enable serial RapidIO */
> +#define CONFIG_TSEC_ENET  1 /* tsec ethernet support */
> +#define CONFIG_INTERRUPTS 1 /* enable pci, srio, ddr interrupts */
> +#define CONFIG_FSL_LAW    1 /* Use common FSL init code */

Remove all the '1'.  Yes a ton of config.h do this and its not needed.  We need to clean them up but haven't gotten around to it.

> +
> +/*
> + * These can be toggled for performance analysis, otherwise use default.
> + */
> +#define CONFIG_L2_CACHE   1 /* toggle L2 cache */
> +#define CONFIG_BTB        1 /* toggle branch predition */
> +
> +#define CONFIG_PANIC_HANG 1
> +
> +/*
> + * Only possible on E500 Version 2 or newer cores.
> + */
> +#define CONFIG_ENABLE_36BIT_PHYS   1
> +
> +#ifdef CONFIG_PHYS_64BIT
> +# define CONFIG_ADDR_MAP           1
> +# define CONFIG_SYS_NUM_ADDR_MAP   16 /* number of TLB1 entries */
> +#endif
> +
> +
> +#define CONFIG_SYS_CLK_FREQ        33000000 /* sysclk for MPC85xx */
> +
> +/*
> + * Base addresses -- Note these are effective addresses where the
> + * actual resources get mapped (not physical addresses)
> + */
> +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
> +#define CONFIG_SYS_CCSRBAR         0xe0000000
> +
> +#ifdef CONFIG_PHYS_64BIT
> +# define CONFIG_SYS_CCSRBAR_PHYS   0xfe0000000ull
> +#else
> +# define CONFIG_SYS_CCSRBAR_PHYS   CONFIG_SYS_CCSRBAR
> +#endif
> +
> +#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
> +
> +/* DDR Setup */
> +#define CONFIG_FSL_DDR2
> +
> +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1  /* DDR controller or DMA? */
> +
> +#define CONFIG_MEM_INIT_VALUE        0xDeadBeef
> +#define CONFIG_SYS_DDR_SDRAM_BASE    0x00000000 /* DDR is system memory*/
> +#define CONFIG_SYS_SDRAM_BASE        CONFIG_SYS_DDR_SDRAM_BASE
> +
> +#define CONFIG_NUM_DDR_CONTROLLERS   1
> +#define CONFIG_DIMM_SLOTS_PER_CTLR   1
> +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
> +
> +/* Fixed 512MB DDR2 parameters */
> +#define CONFIG_SYS_SDRAM_SIZE_LOG    29 /* DDR is 512MB */
> +#define CONFIG_SYS_DDR_CS0_BNDS      0x0000001f
> +#define CONFIG_SYS_DDR_CS0_CONFIG    0x80014102
> +#define CONFIG_SYS_DDR_TIMING_3      0x00010000
> +#define CONFIG_SYS_DDR_TIMING_0      0x00260802
> +#define CONFIG_SYS_DDR_TIMING_1      0x5c47a432
> +#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
> +#define CONFIG_SYS_DDR_TIMING_2      0x03984cce
> +#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
> +#define CONFIG_SYS_DDR_MODE_1        0x00400442
> +#define CONFIG_SYS_DDR_MODE_1_PERF   0x00480432
> +#define CONFIG_SYS_DDR_MODE_2        0x00000000
> +#define CONFIG_SYS_DDR_MODE_2_PERF   0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL      0x08200100
> +#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
> +#define CONFIG_SYS_DDR_CLK_CTRL      0x03800000
> +#define CONFIG_SYS_DDR_CONTROL       0xc3008000 /* Type = DDR2 */
> +#define CONFIG_SYS_DDR_CONTROL2      0x04400000
> +
> +#define CONFIG_SYS_ALT_MEMTEST       1
> +#define CONFIG_SYS_MEMTEST_START     0x0ff00000 /* memtest works on */
> +#define CONFIG_SYS_MEMTEST_END       0x0ffffffc
> +
> +/*
> + * RAM definitions
> + */
> +#define CONFIG_SYS_INIT_RAM_LOCK   1
> +#define CONFIG_SYS_INIT_RAM_ADDR   0xe4010000 /* Initial RAM address */
> +#define CONFIG_SYS_INIT_RAM_SIZE   0x4000     /* Size of used area in RAM */
> +
> +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
> +				    - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
> +
> +#define CONFIG_SYS_MONITOR_LEN     (256 * 1024)  /* Reserve 256 kB for Mon */
> +#define CONFIG_SYS_MALLOC_LEN      (1024 * 1024) /* Reserved for malloc */
> +
> +/*
> + * Local Bus Definitions
> + */
> +#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
> +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
> +
> +
> +/*
> + * FLASH on the Local Bus
> + * One bank, 128M, using the CFI driver.
> + */
> +#define CONFIG_SYS_BOOT_BLOCK 0xf8000000            /* boot TLB block */
> +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
> +
> +#ifdef CONFIG_PHYS_64BIT
> +# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
> +#else
> +# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
> +#endif
> +
> +/* 0xf8001801 */
> +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
> +			       | BR_PS_32 | BR_V)
> +
> +/* 0xf8006ff7 */
> +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
> +			       | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
> +			       | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
> +			       | OR_GPCM_EHTR | OR_GPCM_EAD)
> +
> +#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
> +#define CONFIG_FLASH_SHOW_PROGRESS     45   /* count down from 45/5: 9..1 */
> +
> +#define CONFIG_SYS_MAX_FLASH_BANKS     1    /* number of banks */
> +#define CONFIG_SYS_MAX_FLASH_SECT      512  /* sectors per device */
> +
> +#define CONFIG_SYS_FLASH_ERASE_TOUT    60000 /* Flash Erase Timeout (ms) */
> +#define CONFIG_SYS_FLASH_WRITE_TOUT    500   /* Flash Write Timeout (ms) */
> +
> +#define CONFIG_FLASH_CFI_DRIVER        1
> +#define CONFIG_SYS_FLASH_CFI           1
> +#define CONFIG_SYS_FLASH_EMPTY_INFO    1
> +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 1
> +/*
> + * When initializing flash, if we cannot find the manufacturer ID,
> + * assume this is the AMD flash.
> + */
> +#define CONFIG_ASSUME_AMD_FLASH        1
> +
> +/*
> + * Environment parameters
> + */
> +#define CONFIG_ENV_IS_IN_FLASH  1
> +#define CONFIG_ENV_OVERWRITE    1
> +#define CONFIG_SYS_USE_PPCENV   1
> +#define ENV_IS_EMBEDDED         1
> +#define CONFIG_ENV_SECT_SIZE    0x40000   /* 256K */
> +#define CONFIG_ENV_SIZE         0x800
> +
> +/* Environment at the start of flash sector, before text. */
> +#define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> +#define CONFIG_SYS_TEXT_BASE    0xfffc0800
> +
> +/*
> + * Cypress CY7C67200 USB controller on the Local Bus.
> + * Not supported by u-boot at present.
> + */
> +#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
> +
> +#ifdef CONFIG_PHYS_64BIT
> +# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
> +#else
> +# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
> +#endif
> +
> +/* 0xf0001001 */
> +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
> +			       | BR_PS_16 | BR_V)
> +
> +/* fffff002 */
> +#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
> +			       | OR_GPCM_BCTLD | OR_GPCM_EHTR)
> +
> +/*
> + * Serial Ports
> + */
> +#define CONFIG_CONS_INDEX           2
> +#define CONFIG_SYS_NS16550          1
> +#define CONFIG_SYS_NS16550_SERIAL   1
> +#define CONFIG_SYS_NS16550_REG_SIZE 1
> +#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
> +
> +#define CONFIG_SYS_BAUDRATE_TABLE   {300, 600, 1200, 2400, 4800, 9600, \
> +				     19200, 38400, 115200}
> +
> +#define CONFIG_SYS_NS16550_COM1     (CONFIG_SYS_CCSRBAR+0x4500)
> +#define CONFIG_SYS_NS16550_COM2     (CONFIG_SYS_CCSRBAR+0x4600)
> +
> +/*
> + * I2C buses and peripherals
> + */
> +#define CONFIG_FSL_I2C         1      /* Use FSL common I2C driver */
> +#define CONFIG_HARD_I2C        1      /* I2C with hardware support*/
> +#define CONFIG_I2C_MULTI_BUS   1
> +#define CONFIG_SYS_I2C_SPEED   400000 /* I2C speed and slave address */
> +#define CONFIG_SYS_I2C_SLAVE   0x7f
> +#define CONFIG_SYS_I2C_OFFSET  0x3000
> +#define CONFIG_SYS_I2C2_OFFSET 0x3100
> +
> +/* I2C RTC - M41T81 */
> +#define CONFIG_RTC_M41T62                     1
> +#define CONFIG_SYS_I2C_RTC_ADDR               0x68
> +#define CONFIG_SYS_M41T11_BASE_YEAR           2000
> +
> +/* I2C EEPROM - 24C256 */
> +#define CONFIG_SYS_I2C_EEPROM_ADDR            0x50
> +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     6
> +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
> +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        2
> +#define CONFIG_SYS_EEPROM_BUS_NUM             1
> +
> +/*
> + * RapidIO MMU
> + */
> +#define CONFIG_SRIO1               1
> +#define CONFIG_SYS_SRIO1_MEM_VIRT  0xc0000000
> +#define CONFIG_SYS_SRIO1_MEM_SIZE  0x20000000 /* 512M */
> +
> +#ifdef CONFIG_PHYS_64BIT
> +# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
> +#else
> +# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
> +#endif
> +
> +/*
> + * Ethernet
> + */
> +#ifdef CONFIG_TSEC_ENET
> +
> +# ifndef CONFIG_NET_MULTI
> +#  define CONFIG_NET_MULTI       1
> +# endif
> +
> +# define CONFIG_MII              1 /* MII PHY management */
> +# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
> +
> +# define CONFIG_TSEC1            1
> +# define CONFIG_TSEC1_NAME       "eTSEC0"
> +# define TSEC1_PHY_ADDR          0x10
> +# define TSEC1_PHYIDX            0
> +# define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
> +
> +# define CONFIG_TSEC2            1
> +# define CONFIG_TSEC2_NAME       "eTSEC1"
> +# define TSEC2_PHY_ADDR          0x11
> +# define TSEC2_PHYIDX            0
> +# define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
> +
> +# define CONFIG_TSEC3            1
> +# define CONFIG_TSEC3_NAME       "eTSEC2"
> +# define TSEC3_PHY_ADDR          0x12
> +# define TSEC3_PHYIDX            0
> +# define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
> +
> +# define CONFIG_TSEC4            1
> +# define CONFIG_TSEC4_NAME       "eTSEC3"
> +# define TSEC4_PHY_ADDR          0x13
> +# define TSEC4_PHYIDX            0
> +# define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
> +
> +/* Options are: eTSEC[0-3] */
> +# define CONFIG_ETHPRIME         "eTSEC0"
> +# define CONFIG_PHY_GIGE         1 /* Include GbE speed/duplex detection */
> +#endif
> +
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_DATE
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_SNTP
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_EEPROM
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_ELF
> +#define CONFIG_CMD_IRQ
> +#define CONFIG_CMD_SETEXPR
> +#define CONFIG_CMD_JFFS2
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +
> +/* pass open firmware flat tree */
> +#define CONFIG_OF_LIBFDT             1
> +#define CONFIG_OF_BOARD_SETUP        1
> +#define CONFIG_OF_STDOUT_VIA_ALIAS   1
> +
> +/* new uImage format support */
> +#define CONFIG_FIT                   1
> +#define CONFIG_FIT_VERBOSE           1 /* enable fit_format_{error,warning}() */
> +
> +/* Use the HUSH parser */
> +#define CONFIG_SYS_HUSH_PARSER       1
> +
> +#ifdef CONFIG_SYS_HUSH_PARSER
> +# define CONFIG_SYS_PROMPT_HUSH_PS2  "> "
> +#endif
> +
> +#define CONFIG_LOADS_ECHO            1 /* echo on for serial download */
> +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> +
> +#define CONFIG_SYS_LONGHELP          1 /* undef to save memory */
> +#define CONFIG_CMDLINE_EDITING       1 /* Command-line editing */
> +#define CONFIG_AUTO_COMPLETE         1 /* add autocompletion support */
> +
> +#define CONFIG_SYS_LOAD_ADDR         0x2000000    /* default load address */
> +#define CONFIG_SYS_PROMPT            "MPQ-101=> " /* Monitor Command Prompt */
> +
> +/* Console I/O Buffer Size */
> +#ifdef CONFIG_CMD_KGDB
> +# define CONFIG_SYS_CBSIZE 1024
> +#else
> +# define CONFIG_SYS_CBSIZE 256
> +#endif
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
> +
> +#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
> +#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
> +
> +/*
> + * For booting Linux, the board info and command line data
> + * have to be in the first 16 MB of memory, since this is
> + * the maximum mapped by the Linux kernel during initialization.
> + */
> +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
> +
> +#ifdef CONFIG_CMD_KGDB
> +# define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
> +# define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
> +#endif
> +
> +/*
> + * Basic Environment Configuration
> + */
> +#define CONFIG_BAUDRATE  115200
> +#define CONFIG_BOOTDELAY 5            /* -1 disables auto-boot */
> +
> +/*default location for tftp and bootm*/
> +#define CONFIG_LOADADDR  CONFIG_SYS_LOAD_ADDR
> +
> +#endif /* __CONFIG_H */
> -- 
> 1.7.3.2
> 
> 
> 

[U-Boot] [PATCH v6] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
memory, real time clock and additional serial EEPROM on i2c bus (enabled).
USB controller is available, but not presently enabled.

Additional board information is available at:
http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx

Environment is configured to precede the actual u-boot image so that it's
located at the beginning of flash erase block (made necessary by the recent
changes to the embedded environment handling). This is achieved by means of
custom ld script.

Signed-off-by: Alex Dubov <oakad@yahoo.com>
---
Changes for v6:
   - Remove "1"s from feature defines and fix a SRIO ifdef in tlb.c
Changes for v5:
   - Use new common SRIO configuration definitions.
   - Replace initdram() with platform required fixed_sdram().
   - Don't use get_ram_size() in fixed_sdram() as TLBs are set after it exits
     by common platform code.
Changes for v4:
   - Replace config.mk supplied linker flags with custom linker script.
   - Fix checkpatch errors.
Changes for v3:
   - Use io accessor functions for all mmio accesses.
   - Add configuration options for RTC and EEPROM on I2C buses.
Changes for v2:
   - Remove some stale configuration code from board initialization functions.

 MAINTAINERS                     |    3 +
 board/mercury/mpq101/Makefile   |   53 ++++++
 board/mercury/mpq101/law.c      |   52 +++++
 board/mercury/mpq101/mpq101.c   |  129 +++++++++++++
 board/mercury/mpq101/tlb.c      |   82 ++++++++
 board/mercury/mpq101/u-boot.lds |  132 +++++++++++++
 boards.cfg                      |    1 +
 include/configs/mpq101.h        |  392 +++++++++++++++++++++++++++++++++++++++
 8 files changed, 844 insertions(+), 0 deletions(-)
 create mode 100644 board/mercury/mpq101/Makefile
 create mode 100644 board/mercury/mpq101/law.c
 create mode 100644 board/mercury/mpq101/mpq101.c
 create mode 100644 board/mercury/mpq101/tlb.c
 create mode 100644 board/mercury/mpq101/u-boot.lds
 create mode 100644 include/configs/mpq101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index a799037..d0fc7dc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -138,6 +138,9 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260		MPC8260
 
+Alex Dubov <oakad@yahoo.com>
+	mpq101		MPC8548
+
 Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX
diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile
new file mode 100644
index 0000000..58bc1b3
--- /dev/null
+++ b/board/mercury/mpq101/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c
new file mode 100644
index 0000000..0e23a6a
--- /dev/null
+++ b/board/mercury/mpq101/law.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x1fff_ffff     DDR                     SYS_SDRAM_SIZE
+ * 0xc000_0000     0xdfff_ffff     RapidIO (set elsewhere) 512M
+ * 0xe000_0000     0xe000_ffff     CCSR    (set elsewhere) 1M
+ * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
+		LAW_TRGT_IF_DDR_1),
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
+		LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/mercury/mpq101/mpq101.c b/board/mercury/mpq101/mpq101.c
new file mode 100644
index 0000000..e02e87f
--- /dev/null
+++ b/board/mercury/mpq101/mpq101.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init(void)
+{
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+}
+
+int checkboard(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+	putc('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+phys_size_t fixed_sdram(void)
+{
+	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+	const char *p_mode = getenv("perf_mode");
+
+	puts("Initializing....");
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (p_mode && !strcmp("performance", p_mode)) {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
+	} else {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	}
+
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
+
+	asm("sync;isync");
+	udelay(500);
+
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+	asm("sync; isync");
+	udelay(500);
+
+	return ((phys_size_t)1) << CONFIG_SYS_SDRAM_SIZE_LOG;
+}
+
+void pci_init_board(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+
+#endif
diff --git a/board/mercury/mpq101/tlb.c b/board/mercury/mpq101/tlb.c
new file mode 100644
index 0000000..fd2eaec
--- /dev/null
+++ b/board/mercury/mpq101/tlb.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	256M	Non-cacheable, guarded
+	 * 0xf0000000	256M	LBC (FLASH included)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+		      CONFIG_SYS_LBC_OPTION_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 1:	1M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
+	/*
+	 * TLB 2:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000,
+		      CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/mercury/mpq101/u-boot.lds b/board/mercury/mpq101/u-boot.lds
new file mode 100644
index 0000000..3af0274
--- /dev/null
+++ b/board/mercury/mpq101/u-boot.lds
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+#include <config.h>
+
+OUTPUT_ARCH(powerpc)
+
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  /* To simplify mass deployment, environment precedes the monitor text in the
+   * same flash sector.
+   */
+  .ppcenv CONFIG_ENV_ADDR : { *(.ppcenv) }
+  .text      :
+  {
+    *(.text*)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg RESET_VECTOR_ADDRESS - 0xffc :
+  {
+    arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  .resetvec RESET_VECTOR_ADDRESS :
+  {
+    KEEP(*(.resetvec))
+  } :text = 0xffff
+
+  . = RESET_VECTOR_ADDRESS + 0x4;
+
+  /*
+   * Make sure that the bss segment isn't linked at 0x0, otherwise its
+   * address won't be updated during relocation fixups.  Note that
+   * this is a temporary fix.  Code to dynamically the fixup the bss
+   * location will be added in the future.  When the bss relocation
+   * fixup code is present this workaround should be removed.
+   */
+#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
+  . |= 0x10;
+#endif
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss*)
+   *(.bss*)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/boards.cfg b/boards.cfg
index 3497408..0f94969 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -495,6 +495,7 @@ P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freesca
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SPIFLASH
 P4080DS                      powerpc     mpc85xx     corenet_ds          freescale
+mpq101                       powerpc     mpc85xx     mpq101              mercury        -           mpq101:SYS_LDSCRIPT=board/mercury/mpq101/u-boot.lds
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M
diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h
new file mode 100644
index 0000000..9b30ed4
--- /dev/null
+++ b/include/configs/mpq101.h
@@ -0,0 +1,392 @@
+/*
+ * Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Merury Computers MPQ101 board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+# define CONFIG_PHYS_64BIT
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE      /* BOOKE */
+#define CONFIG_E500       /* BOOKE e500 family */
+#define CONFIG_MPC85xx    /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548    /* MPC8548 specific */
+#define CONFIG_MPQ101     /* MPQ101 board specific */
+
+#define CONFIG_SYS_SRIO   /* enable serial RapidIO */
+#define CONFIG_TSEC_ENET  /* tsec ethernet support */
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW    /* Use common FSL init code */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE   /* toggle L2 cache */
+#define CONFIG_BTB        /* toggle branch predition */
+
+#define CONFIG_PANIC_HANG
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_ADDR_MAP
+# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+
+#define CONFIG_SYS_CLK_FREQ      33000000 /* sysclk for MPC85xx */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_CCSRBAR         0xe0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_CCSRBAR_PHYS   0xfe0000000ull
+#else
+# define CONFIG_SYS_CCSRBAR_PHYS   CONFIG_SYS_CCSRBAR
+#endif
+
+#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE        0xDeadBeef
+#define CONFIG_SYS_DDR_SDRAM_BASE    0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE        CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS   1
+#define CONFIG_DIMM_SLOTS_PER_CTLR   1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* Fixed 512MB DDR2 parameters */
+#define CONFIG_SYS_SDRAM_SIZE_LOG    29 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS      0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG    0x80014102
+#define CONFIG_SYS_DDR_TIMING_3      0x00010000
+#define CONFIG_SYS_DDR_TIMING_0      0x00260802
+#define CONFIG_SYS_DDR_TIMING_1      0x5c47a432
+#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
+#define CONFIG_SYS_DDR_TIMING_2      0x03984cce
+#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
+#define CONFIG_SYS_DDR_MODE_1        0x00400442
+#define CONFIG_SYS_DDR_MODE_1_PERF   0x00480432
+#define CONFIG_SYS_DDR_MODE_2        0x00000000
+#define CONFIG_SYS_DDR_MODE_2_PERF   0x00000000
+#define CONFIG_SYS_DDR_INTERVAL      0x08200100
+#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
+#define CONFIG_SYS_DDR_CLK_CTRL      0x03800000
+#define CONFIG_SYS_DDR_CONTROL       0xc3008000 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2      0x04400000
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START     0x0ff00000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END       0x0ffffffc
+
+/*
+ * RAM definitions
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR   0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE   0x4000     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+				    - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN     (256 * 1024)  /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN      (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+
+
+/*
+ * FLASH on the Local Bus
+ * One bank, 128M, using the CFI driver.
+ */
+#define CONFIG_SYS_BOOT_BLOCK 0xf8000000            /* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
+#else
+# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+/* 0xf8001801 */
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+			       | BR_PS_32 | BR_V)
+
+/* 0xf8006ff7 */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
+			       | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+			       | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
+			       | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FLASH_SHOW_PROGRESS     45   /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     1    /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      512  /* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500   /* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+/*
+ * Environment parameters
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_USE_PPCENV
+#define ENV_IS_EMBEDDED
+#define CONFIG_ENV_SECT_SIZE 0x40000   /* 256K */
+#define CONFIG_ENV_SIZE      0x800
+
+/* Environment at the start of flash sector, before text. */
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_TEXT_BASE    0xfffc0800
+
+/*
+ * Cypress CY7C67200 USB controller on the Local Bus.
+ * Not supported by u-boot at present.
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
+#else
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
+#endif
+
+/* 0xf0001001 */
+#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
+			       | BR_PS_16 | BR_V)
+
+/* fffff002 */
+#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
+			       | OR_GPCM_BCTLD | OR_GPCM_EHTR)
+
+/*
+ * Serial Ports
+ */
+#define CONFIG_CONS_INDEX           2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE   {300, 600, 1200, 2400, 4800, 9600, \
+				     19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1     (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2     (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C buses and peripherals
+ */
+#define CONFIG_FSL_I2C         /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C        /* I2C with hardware support*/
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED   400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE   0x7f
+#define CONFIG_SYS_I2C_OFFSET  0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/* I2C RTC - M41T81 */
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR     0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/* I2C EEPROM - 24C256 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR            0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        2
+#define CONFIG_SYS_EEPROM_BUS_NUM             1
+
+/*
+ * RapidIO MMU
+ */
+#ifdef CONFIG_SYS_SRIO
+# define CONFIG_SRIO1
+# define CONFIG_SYS_SRIO1_MEM_VIRT  0xc0000000
+# define CONFIG_SYS_SRIO1_MEM_SIZE  0x20000000 /* 512M */
+
+# ifdef CONFIG_PHYS_64BIT
+#  define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
+# else
+#  define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
+# endif
+#endif
+
+/*
+ * Ethernet
+ */
+#ifdef CONFIG_TSEC_ENET
+
+# ifndef CONFIG_NET_MULTI
+#  define CONFIG_NET_MULTI
+# endif
+
+# define CONFIG_MII                /* MII PHY management */
+# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+
+# define CONFIG_TSEC1
+# define CONFIG_TSEC1_NAME       "eTSEC0"
+# define TSEC1_PHY_ADDR          0x10
+# define TSEC1_PHYIDX            0
+# define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC2
+# define CONFIG_TSEC2_NAME       "eTSEC1"
+# define TSEC2_PHY_ADDR          0x11
+# define TSEC2_PHYIDX            0
+# define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC3
+# define CONFIG_TSEC3_NAME       "eTSEC2"
+# define TSEC3_PHY_ADDR          0x12
+# define TSEC3_PHYIDX            0
+# define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC4
+# define CONFIG_TSEC4_NAME       "eTSEC3"
+# define TSEC4_PHY_ADDR          0x13
+# define TSEC4_PHYIDX            0
+# define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+# define CONFIG_ETHPRIME         "eTSEC0"
+# define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_JFFS2
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#define CONFIG_FIT         /* new uImage format support */
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+# define CONFIG_SYS_PROMPT_HUSH_PS2  "> "
+#endif
+
+#define CONFIG_LOADS_ECHO            /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+#define CONFIG_SYS_LONGHELP          /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING       /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE         /* add autocompletion support */
+
+#define CONFIG_SYS_LOAD_ADDR         0x2000000    /* default load address */
+#define CONFIG_SYS_PROMPT            "MPQ-101=> " /* Monitor Command Prompt */
+
+/* Console I/O Buffer Size */
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE 1024
+#else
+# define CONFIG_SYS_CBSIZE 256
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
+# define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
+#endif
+
+/*
+ * Basic Environment Configuration
+ */
+#define CONFIG_BAUDRATE  115200
+#define CONFIG_BOOTDELAY 5            /* -1 disables auto-boot */
+
+/*default location for tftp and bootm*/
+#define CONFIG_LOADADDR  CONFIG_SYS_LOAD_ADDR
+
+#endif /* __CONFIG_H */
-- 
1.7.3.2




      

[U-Boot] [PATCH v6] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Kumar Gala]

On Jan 18, 2011, at 2:03 AM, Alex Dubov wrote:

> 
> +/*
> + * For booting Linux, the board info and command line data
> + * have to be in the first 16 MB of memory, since this is
> + * the maximum mapped by the Linux kernel during initialization.
> + */
> +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
> +

You might also want to set:

#define CONFIG_SYS_BOOTM_LEN   (16 << 20)      /* Increase max gunzip size */

to match BOOTMAPSZ.

Sorry, I keep nit picking ;)

- k

[U-Boot] [PATCH v6] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

> 
> > 
> > +/*
> > + * For booting Linux, the board info and command line
> data
> > + * have to be in the first 16 MB of memory, since
> this is
> > + * the maximum mapped by the Linux kernel during
> initialization.
> > + */
> > +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /*
> Initial Memory map for Linux*/
> > +
> 
> You might also want to set:
> 
> #define CONFIG_SYS_BOOTM_LEN???(16 <<
> 20)? ? ? /* Increase max gunzip size */
> 
> to match BOOTMAPSZ.
> 
> Sorry, I keep nit picking ;)
> 

Can you, please, assure me, that when this particular line is corrected
the patch will be accepted?
If not, what possible additional problems do you see there?




      

[U-Boot] [PATCH v7] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
memory, real time clock and additional serial EEPROM on i2c bus (enabled).
USB controller is available, but not presently enabled.

Additional board information is available at:
http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx

Environment is configured to precede the actual u-boot image so that it's
located at the beginning of flash erase block (made necessary by the recent
changes to the embedded environment handling). This is achieved by means of
custom ld script.

Signed-off-by: Alex Dubov <oakad@yahoo.com>
---
Cahnges for v7:
   - Add CONFIG_SYS_BOOTM_LEN define
Changes for v6:
   - Remove "1"s from feature defines and fix a SRIO ifdef in tlb.c
Changes for v5:
   - Use new common SRIO configuration definitions.
   - Replace initdram() with platform required fixed_sdram().
   - Don't use get_ram_size() in fixed_sdram() as TLBs are set after it exits
     by common platform code.
Changes for v4:
   - Replace config.mk supplied linker flags with custom linker script.
   - Fix checkpatch errors.
Changes for v3:
   - Use io accessor functions for all mmio accesses.
   - Add configuration options for RTC and EEPROM on I2C buses.
Changes for v2:
   - Remove some stale configuration code from board initialization functions.

 MAINTAINERS                     |    3 +
 board/mercury/mpq101/Makefile   |   53 ++++++
 board/mercury/mpq101/law.c      |   52 +++++
 board/mercury/mpq101/mpq101.c   |  129 +++++++++++++
 board/mercury/mpq101/tlb.c      |   82 ++++++++
 board/mercury/mpq101/u-boot.lds |  132 +++++++++++++
 boards.cfg                      |    1 +
 include/configs/mpq101.h        |  393 +++++++++++++++++++++++++++++++++++++++
 8 files changed, 845 insertions(+), 0 deletions(-)
 create mode 100644 board/mercury/mpq101/Makefile
 create mode 100644 board/mercury/mpq101/law.c
 create mode 100644 board/mercury/mpq101/mpq101.c
 create mode 100644 board/mercury/mpq101/tlb.c
 create mode 100644 board/mercury/mpq101/u-boot.lds
 create mode 100644 include/configs/mpq101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index a799037..d0fc7dc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -138,6 +138,9 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260		MPC8260
 
+Alex Dubov <oakad@yahoo.com>
+	mpq101		MPC8548
+
 Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX
diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile
new file mode 100644
index 0000000..58bc1b3
--- /dev/null
+++ b/board/mercury/mpq101/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c
new file mode 100644
index 0000000..0e23a6a
--- /dev/null
+++ b/board/mercury/mpq101/law.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x1fff_ffff     DDR                     SYS_SDRAM_SIZE
+ * 0xc000_0000     0xdfff_ffff     RapidIO (set elsewhere) 512M
+ * 0xe000_0000     0xe000_ffff     CCSR    (set elsewhere) 1M
+ * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
+		LAW_TRGT_IF_DDR_1),
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
+		LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/mercury/mpq101/mpq101.c b/board/mercury/mpq101/mpq101.c
new file mode 100644
index 0000000..e02e87f
--- /dev/null
+++ b/board/mercury/mpq101/mpq101.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init(void)
+{
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+}
+
+int checkboard(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+	putc('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+phys_size_t fixed_sdram(void)
+{
+	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+	const char *p_mode = getenv("perf_mode");
+
+	puts("Initializing....");
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (p_mode && !strcmp("performance", p_mode)) {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
+	} else {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	}
+
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
+
+	asm("sync;isync");
+	udelay(500);
+
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+	asm("sync; isync");
+	udelay(500);
+
+	return ((phys_size_t)1) << CONFIG_SYS_SDRAM_SIZE_LOG;
+}
+
+void pci_init_board(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+
+#endif
diff --git a/board/mercury/mpq101/tlb.c b/board/mercury/mpq101/tlb.c
new file mode 100644
index 0000000..fd2eaec
--- /dev/null
+++ b/board/mercury/mpq101/tlb.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	256M	Non-cacheable, guarded
+	 * 0xf0000000	256M	LBC (FLASH included)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+		      CONFIG_SYS_LBC_OPTION_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 1:	1M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
+	/*
+	 * TLB 2:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000,
+		      CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/mercury/mpq101/u-boot.lds b/board/mercury/mpq101/u-boot.lds
new file mode 100644
index 0000000..3af0274
--- /dev/null
+++ b/board/mercury/mpq101/u-boot.lds
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+#include <config.h>
+
+OUTPUT_ARCH(powerpc)
+
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  /* To simplify mass deployment, environment precedes the monitor text in the
+   * same flash sector.
+   */
+  .ppcenv CONFIG_ENV_ADDR : { *(.ppcenv) }
+  .text      :
+  {
+    *(.text*)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg RESET_VECTOR_ADDRESS - 0xffc :
+  {
+    arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  .resetvec RESET_VECTOR_ADDRESS :
+  {
+    KEEP(*(.resetvec))
+  } :text = 0xffff
+
+  . = RESET_VECTOR_ADDRESS + 0x4;
+
+  /*
+   * Make sure that the bss segment isn't linked at 0x0, otherwise its
+   * address won't be updated during relocation fixups.  Note that
+   * this is a temporary fix.  Code to dynamically the fixup the bss
+   * location will be added in the future.  When the bss relocation
+   * fixup code is present this workaround should be removed.
+   */
+#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
+  . |= 0x10;
+#endif
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss*)
+   *(.bss*)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/boards.cfg b/boards.cfg
index 3497408..0f94969 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -495,6 +495,7 @@ P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freesca
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SPIFLASH
 P4080DS                      powerpc     mpc85xx     corenet_ds          freescale
+mpq101                       powerpc     mpc85xx     mpq101              mercury        -           mpq101:SYS_LDSCRIPT=board/mercury/mpq101/u-boot.lds
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M
diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h
new file mode 100644
index 0000000..1b4137e
--- /dev/null
+++ b/include/configs/mpq101.h
@@ -0,0 +1,393 @@
+/*
+ * Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Merury Computers MPQ101 board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+# define CONFIG_PHYS_64BIT
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE      /* BOOKE */
+#define CONFIG_E500       /* BOOKE e500 family */
+#define CONFIG_MPC85xx    /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548    /* MPC8548 specific */
+#define CONFIG_MPQ101     /* MPQ101 board specific */
+
+#define CONFIG_SYS_SRIO   /* enable serial RapidIO */
+#define CONFIG_TSEC_ENET  /* tsec ethernet support */
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW    /* Use common FSL init code */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE   /* toggle L2 cache */
+#define CONFIG_BTB        /* toggle branch predition */
+
+#define CONFIG_PANIC_HANG
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_ADDR_MAP
+# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+
+#define CONFIG_SYS_CLK_FREQ      33000000 /* sysclk for MPC85xx */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_CCSRBAR         0xe0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_CCSRBAR_PHYS   0xfe0000000ull
+#else
+# define CONFIG_SYS_CCSRBAR_PHYS   CONFIG_SYS_CCSRBAR
+#endif
+
+#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE        0xDeadBeef
+#define CONFIG_SYS_DDR_SDRAM_BASE    0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE        CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS   1
+#define CONFIG_DIMM_SLOTS_PER_CTLR   1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* Fixed 512MB DDR2 parameters */
+#define CONFIG_SYS_SDRAM_SIZE_LOG    29 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS      0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG    0x80014102
+#define CONFIG_SYS_DDR_TIMING_3      0x00010000
+#define CONFIG_SYS_DDR_TIMING_0      0x00260802
+#define CONFIG_SYS_DDR_TIMING_1      0x5c47a432
+#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
+#define CONFIG_SYS_DDR_TIMING_2      0x03984cce
+#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
+#define CONFIG_SYS_DDR_MODE_1        0x00400442
+#define CONFIG_SYS_DDR_MODE_1_PERF   0x00480432
+#define CONFIG_SYS_DDR_MODE_2        0x00000000
+#define CONFIG_SYS_DDR_MODE_2_PERF   0x00000000
+#define CONFIG_SYS_DDR_INTERVAL      0x08200100
+#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
+#define CONFIG_SYS_DDR_CLK_CTRL      0x03800000
+#define CONFIG_SYS_DDR_CONTROL       0xc3008000 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2      0x04400000
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START     0x0ff00000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END       0x0ffffffc
+
+/*
+ * RAM definitions
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR   0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE   0x4000     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+				    - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN     (256 * 1024)  /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN      (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+
+
+/*
+ * FLASH on the Local Bus
+ * One bank, 128M, using the CFI driver.
+ */
+#define CONFIG_SYS_BOOT_BLOCK 0xf8000000            /* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
+#else
+# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+/* 0xf8001801 */
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+			       | BR_PS_32 | BR_V)
+
+/* 0xf8006ff7 */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
+			       | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+			       | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
+			       | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FLASH_SHOW_PROGRESS     45   /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     1    /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      512  /* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500   /* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+/*
+ * Environment parameters
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_USE_PPCENV
+#define ENV_IS_EMBEDDED
+#define CONFIG_ENV_SECT_SIZE 0x40000   /* 256K */
+#define CONFIG_ENV_SIZE      0x800
+
+/* Environment at the start of flash sector, before text. */
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_TEXT_BASE    0xfffc0800
+
+/*
+ * Cypress CY7C67200 USB controller on the Local Bus.
+ * Not supported by u-boot at present.
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
+#else
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
+#endif
+
+/* 0xf0001001 */
+#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
+			       | BR_PS_16 | BR_V)
+
+/* fffff002 */
+#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
+			       | OR_GPCM_BCTLD | OR_GPCM_EHTR)
+
+/*
+ * Serial Ports
+ */
+#define CONFIG_CONS_INDEX           2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE   {300, 600, 1200, 2400, 4800, 9600, \
+				     19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1     (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2     (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C buses and peripherals
+ */
+#define CONFIG_FSL_I2C         /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C        /* I2C with hardware support*/
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED   400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE   0x7f
+#define CONFIG_SYS_I2C_OFFSET  0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/* I2C RTC - M41T81 */
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR     0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/* I2C EEPROM - 24C256 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR            0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        2
+#define CONFIG_SYS_EEPROM_BUS_NUM             1
+
+/*
+ * RapidIO MMU
+ */
+#ifdef CONFIG_SYS_SRIO
+# define CONFIG_SRIO1
+# define CONFIG_SYS_SRIO1_MEM_VIRT  0xc0000000
+# define CONFIG_SYS_SRIO1_MEM_SIZE  0x20000000 /* 512M */
+
+# ifdef CONFIG_PHYS_64BIT
+#  define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
+# else
+#  define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
+# endif
+#endif
+
+/*
+ * Ethernet
+ */
+#ifdef CONFIG_TSEC_ENET
+
+# ifndef CONFIG_NET_MULTI
+#  define CONFIG_NET_MULTI
+# endif
+
+# define CONFIG_MII                /* MII PHY management */
+# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+
+# define CONFIG_TSEC1
+# define CONFIG_TSEC1_NAME       "eTSEC0"
+# define TSEC1_PHY_ADDR          0x10
+# define TSEC1_PHYIDX            0
+# define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC2
+# define CONFIG_TSEC2_NAME       "eTSEC1"
+# define TSEC2_PHY_ADDR          0x11
+# define TSEC2_PHYIDX            0
+# define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC3
+# define CONFIG_TSEC3_NAME       "eTSEC2"
+# define TSEC3_PHY_ADDR          0x12
+# define TSEC3_PHYIDX            0
+# define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC4
+# define CONFIG_TSEC4_NAME       "eTSEC3"
+# define TSEC4_PHY_ADDR          0x13
+# define TSEC4_PHYIDX            0
+# define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+# define CONFIG_ETHPRIME         "eTSEC0"
+# define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_JFFS2
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#define CONFIG_FIT         /* new uImage format support */
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+# define CONFIG_SYS_PROMPT_HUSH_PS2  "> "
+#endif
+
+#define CONFIG_LOADS_ECHO            /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+#define CONFIG_SYS_LONGHELP          /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING       /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE         /* add autocompletion support */
+
+#define CONFIG_SYS_LOAD_ADDR         0x2000000    /* default load address */
+#define CONFIG_SYS_PROMPT            "MPQ-101=> " /* Monitor Command Prompt */
+
+/* Console I/O Buffer Size */
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE 1024
+#else
+# define CONFIG_SYS_CBSIZE 256
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
+# define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
+#endif
+
+/*
+ * Basic Environment Configuration
+ */
+#define CONFIG_BAUDRATE  115200
+#define CONFIG_BOOTDELAY 5            /* -1 disables auto-boot */
+
+/*default location for tftp and bootm*/
+#define CONFIG_LOADADDR  CONFIG_SYS_LOAD_ADDR
+
+#endif /* __CONFIG_H */
-- 
1.7.3.2



      

[U-Boot] [PATCH v7] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Kumar Gala]

On Jan 19, 2011, at 11:02 PM, Alex Dubov wrote:

> Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
> processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
> memory, real time clock and additional serial EEPROM on i2c bus (enabled).
> USB controller is available, but not presently enabled.
> 
> Additional board information is available at:
> http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx
> 
> Environment is configured to precede the actual u-boot image so that it's
> located at the beginning of flash erase block (made necessary by the recent
> changes to the embedded environment handling). This is achieved by means of
> custom ld script.
> 
> Signed-off-by: Alex Dubov <oakad@yahoo.com>
> ---
> Cahnges for v7:
>   - Add CONFIG_SYS_BOOTM_LEN define
> Changes for v6:
>   - Remove "1"s from feature defines and fix a SRIO ifdef in tlb.c
> Changes for v5:
>   - Use new common SRIO configuration definitions.
>   - Replace initdram() with platform required fixed_sdram().
>   - Don't use get_ram_size() in fixed_sdram() as TLBs are set after it exits
>     by common platform code.
> Changes for v4:
>   - Replace config.mk supplied linker flags with custom linker script.
>   - Fix checkpatch errors.
> Changes for v3:
>   - Use io accessor functions for all mmio accesses.
>   - Add configuration options for RTC and EEPROM on I2C buses.
> Changes for v2:
>   - Remove some stale configuration code from board initialization functions.
> 
> MAINTAINERS                     |    3 +
> board/mercury/mpq101/Makefile   |   53 ++++++
> board/mercury/mpq101/law.c      |   52 +++++
> board/mercury/mpq101/mpq101.c   |  129 +++++++++++++
> board/mercury/mpq101/tlb.c      |   82 ++++++++
> board/mercury/mpq101/u-boot.lds |  132 +++++++++++++
> boards.cfg                      |    1 +
> include/configs/mpq101.h        |  393 +++++++++++++++++++++++++++++++++++++++
> 8 files changed, 845 insertions(+), 0 deletions(-)
> create mode 100644 board/mercury/mpq101/Makefile
> create mode 100644 board/mercury/mpq101/law.c
> create mode 100644 board/mercury/mpq101/mpq101.c
> create mode 100644 board/mercury/mpq101/tlb.c
> create mode 100644 board/mercury/mpq101/u-boot.lds
> create mode 100644 include/configs/mpq101.h

Doesn't build for me:

common/libcommon.o:(.sdata.env_ptr+0x0): undefined reference to `environment'
make: *** [u-boot] Error 1
[galak at right u-boot-85xx]$ 

- k

[U-Boot] [PATCH v7] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Wolfgang Denk]

Dear Alex Dubov,

In message <25376.26093.qm@web37608.mail.mud.yahoo.com> you wrote:
> Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
> processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
> memory, real time clock and additional serial EEPROM on i2c bus (enabled).
> USB controller is available, but not presently enabled.
...
> diff --git a/boards.cfg b/boards.cfg
> index 3497408..0f94969 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -495,6 +495,7 @@ P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freesca
>  P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SDCARD
>  P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SPIFLASH
>  P4080DS                      powerpc     mpc85xx     corenet_ds          freescale
> +mpq101                       powerpc     mpc85xx     mpq101              mercury        -           mpq101:SYS_LDSCRIPT=board/mercury/mpq101/u-boot.lds

Please keep the boards.cfg clean from configuration settings.  Move
the definition of CONFIG_SYS_LDSCRIPT into your board config header
file.

[Kumar also reported that this does not even build. I confirm this.]

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Quantum Mechanics is God's version of "Trust me."

[U-Boot] [PATCH v7] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

> 
> Please keep the boards.cfg clean from configuration
> settings.? Move
> the definition of CONFIG_SYS_LDSCRIPT into your board
> config header
> file.
> 
> [Kumar also reported that this does not even build. I
> confirm this.]
> 

That's because of the relatively recent change to how the env_embedded.o
is treated by the build system, so I need to refer to it explicitly, rather
then by wildcard.

Shall I send a whole patch again or incremental fix will do?

[U-Boot] [PATCH v8] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
memory, real time clock and additional serial EEPROM on i2c bus (enabled).
USB controller is available, but not presently enabled.

Additional board information is available at:
http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx

Environment is configured to precede the actual u-boot image so that it's
located at the beginning of flash erase block (made necessary by the recent
changes to the embedded environment handling). This is achieved by means of
custom ld script.

Signed-off-by: Alex Dubov <oakad@yahoo.com>
---
Changes for v8:
   - Move CONFIG_SYS_LDSCRIPT to board config file
   - Explicitly refer to env_embedded.o in ld script, as this object is no
     longer linked into libcommon.o
Changes for v7:
   - Add CONFIG_SYS_BOOTM_LEN define
Changes for v6:
   - Remove "1"s from feature defines and fix a SRIO ifdef in tlb.c
Changes for v5:
   - Use new common SRIO configuration definitions.
   - Replace initdram() with platform required fixed_sdram().
   - Don't use get_ram_size() in fixed_sdram() as TLBs are set after it exits
     by common platform code.
Changes for v4:
   - Replace config.mk supplied linker flags with custom linker script.
   - Fix checkpatch errors.
Changes for v3:
   - Use io accessor functions for all mmio accesses.
   - Add configuration options for RTC and EEPROM on I2C buses.
Changes for v2:
   - Remove some stale configuration code from board initialization functions.

 MAINTAINERS                     |    4 +
 board/mercury/mpq101/Makefile   |   53 ++++++
 board/mercury/mpq101/law.c      |   52 +++++
 board/mercury/mpq101/mpq101.c   |  129 +++++++++++++
 board/mercury/mpq101/tlb.c      |   82 ++++++++
 board/mercury/mpq101/u-boot.lds |  132 +++++++++++++
 boards.cfg                      |    1 +
 include/configs/mpq101.h        |  394 +++++++++++++++++++++++++++++++++++++++
 8 files changed, 847 insertions(+), 0 deletions(-)
 create mode 100644 board/mercury/mpq101/Makefile
 create mode 100644 board/mercury/mpq101/law.c
 create mode 100644 board/mercury/mpq101/mpq101.c
 create mode 100644 board/mercury/mpq101/tlb.c
 create mode 100644 board/mercury/mpq101/u-boot.lds
 create mode 100644 include/configs/mpq101.h

diff --git a/MAINTAINERS b/MAINTAINERS
index a799037..ab215c6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -138,6 +138,10 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260		MPC8260
 
+Alex Dubov <oakad@yahoo.com>
+
+	mpq101		MPC8548
+
 Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX
diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile
new file mode 100644
index 0000000..58bc1b3
--- /dev/null
+++ b/board/mercury/mpq101/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c
new file mode 100644
index 0000000..0e23a6a
--- /dev/null
+++ b/board/mercury/mpq101/law.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x1fff_ffff     DDR                     SYS_SDRAM_SIZE
+ * 0xc000_0000     0xdfff_ffff     RapidIO (set elsewhere) 512M
+ * 0xe000_0000     0xe000_ffff     CCSR    (set elsewhere) 1M
+ * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
+		LAW_TRGT_IF_DDR_1),
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
+		LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/mercury/mpq101/mpq101.c b/board/mercury/mpq101/mpq101.c
new file mode 100644
index 0000000..e02e87f
--- /dev/null
+++ b/board/mercury/mpq101/mpq101.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init(void)
+{
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+}
+
+int checkboard(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+	putc('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+phys_size_t fixed_sdram(void)
+{
+	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+	const char *p_mode = getenv("perf_mode");
+
+	puts("Initializing....");
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (p_mode && !strcmp("performance", p_mode)) {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
+	} else {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	}
+
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
+
+	asm("sync;isync");
+	udelay(500);
+
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+	asm("sync; isync");
+	udelay(500);
+
+	return ((phys_size_t)1) << CONFIG_SYS_SDRAM_SIZE_LOG;
+}
+
+void pci_init_board(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+
+#endif
diff --git a/board/mercury/mpq101/tlb.c b/board/mercury/mpq101/tlb.c
new file mode 100644
index 0000000..fd2eaec
--- /dev/null
+++ b/board/mercury/mpq101/tlb.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	256M	Non-cacheable, guarded
+	 * 0xf0000000	256M	LBC (FLASH included)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+		      CONFIG_SYS_LBC_OPTION_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 1:	1M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
+	/*
+	 * TLB 2:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000,
+		      CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/mercury/mpq101/u-boot.lds b/board/mercury/mpq101/u-boot.lds
new file mode 100644
index 0000000..4f4dda5
--- /dev/null
+++ b/board/mercury/mpq101/u-boot.lds
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+#include <config.h>
+
+OUTPUT_ARCH(powerpc)
+
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  /* To simplify mass deployment, environment precedes the monitor text in the
+   * same flash sector.
+   */
+  .ppcenv CONFIG_ENV_ADDR : { common/env_embedded.o (.ppcenv) }
+  .text      :
+  {
+    *(.text*)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg RESET_VECTOR_ADDRESS - 0xffc :
+  {
+    arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  .resetvec RESET_VECTOR_ADDRESS :
+  {
+    KEEP(*(.resetvec))
+  } :text = 0xffff
+
+  . = RESET_VECTOR_ADDRESS + 0x4;
+
+  /*
+   * Make sure that the bss segment isn't linked at 0x0, otherwise its
+   * address won't be updated during relocation fixups.  Note that
+   * this is a temporary fix.  Code to dynamically the fixup the bss
+   * location will be added in the future.  When the bss relocation
+   * fixup code is present this workaround should be removed.
+   */
+#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
+  . |= 0x10;
+#endif
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss*)
+   *(.bss*)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/boards.cfg b/boards.cfg
index 3497408..356acab 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -495,6 +495,7 @@ P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freesca
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SPIFLASH
 P4080DS                      powerpc     mpc85xx     corenet_ds          freescale
+mpq101                       powerpc     mpc85xx     mpq101              mercury        -           mpq101
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M
diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h
new file mode 100644
index 0000000..e76ca73
--- /dev/null
+++ b/include/configs/mpq101.h
@@ -0,0 +1,394 @@
+/*
+ * Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Merury Computers MPQ101 board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+# define CONFIG_PHYS_64BIT
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE      /* BOOKE */
+#define CONFIG_E500       /* BOOKE e500 family */
+#define CONFIG_MPC85xx    /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548    /* MPC8548 specific */
+#define CONFIG_MPQ101     /* MPQ101 board specific */
+
+#define CONFIG_SYS_SRIO   /* enable serial RapidIO */
+#define CONFIG_TSEC_ENET  /* tsec ethernet support */
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW    /* Use common FSL init code */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE   /* toggle L2 cache */
+#define CONFIG_BTB        /* toggle branch predition */
+
+#define CONFIG_PANIC_HANG
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_ADDR_MAP
+# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+
+#define CONFIG_SYS_CLK_FREQ      33000000 /* sysclk for MPC85xx */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_CCSRBAR         0xe0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_CCSRBAR_PHYS   0xfe0000000ull
+#else
+# define CONFIG_SYS_CCSRBAR_PHYS   CONFIG_SYS_CCSRBAR
+#endif
+
+#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE        0xDeadBeef
+#define CONFIG_SYS_DDR_SDRAM_BASE    0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE        CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS   1
+#define CONFIG_DIMM_SLOTS_PER_CTLR   1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* Fixed 512MB DDR2 parameters */
+#define CONFIG_SYS_SDRAM_SIZE_LOG    29 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS      0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG    0x80014102
+#define CONFIG_SYS_DDR_TIMING_3      0x00010000
+#define CONFIG_SYS_DDR_TIMING_0      0x00260802
+#define CONFIG_SYS_DDR_TIMING_1      0x5c47a432
+#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
+#define CONFIG_SYS_DDR_TIMING_2      0x03984cce
+#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
+#define CONFIG_SYS_DDR_MODE_1        0x00400442
+#define CONFIG_SYS_DDR_MODE_1_PERF   0x00480432
+#define CONFIG_SYS_DDR_MODE_2        0x00000000
+#define CONFIG_SYS_DDR_MODE_2_PERF   0x00000000
+#define CONFIG_SYS_DDR_INTERVAL      0x08200100
+#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
+#define CONFIG_SYS_DDR_CLK_CTRL      0x03800000
+#define CONFIG_SYS_DDR_CONTROL       0xc3008000 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2      0x04400000
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START     0x0ff00000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END       0x0ffffffc
+
+/*
+ * RAM definitions
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR   0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE   0x4000     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+				    - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN     (256 * 1024)  /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN      (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+
+
+/*
+ * FLASH on the Local Bus
+ * One bank, 128M, using the CFI driver.
+ */
+#define CONFIG_SYS_BOOT_BLOCK 0xf8000000            /* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
+#else
+# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+/* 0xf8001801 */
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+			       | BR_PS_32 | BR_V)
+
+/* 0xf8006ff7 */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
+			       | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+			       | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
+			       | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FLASH_SHOW_PROGRESS     45   /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     1    /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      512  /* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500   /* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+/*
+ * Environment parameters
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_USE_PPCENV
+#define ENV_IS_EMBEDDED
+#define CONFIG_ENV_SECT_SIZE 0x40000   /* 256K */
+#define CONFIG_ENV_SIZE      0x800
+
+/* Environment at the start of flash sector, before text. */
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_TEXT_BASE    0xfffc0800
+#define CONFIG_SYS_LDSCRIPT     "board/mercury/mpq101/u-boot.lds"
+
+/*
+ * Cypress CY7C67200 USB controller on the Local Bus.
+ * Not supported by u-boot at present.
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
+#else
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
+#endif
+
+/* 0xf0001001 */
+#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
+			       | BR_PS_16 | BR_V)
+
+/* fffff002 */
+#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
+			       | OR_GPCM_BCTLD | OR_GPCM_EHTR)
+
+/*
+ * Serial Ports
+ */
+#define CONFIG_CONS_INDEX           2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE   {300, 600, 1200, 2400, 4800, 9600, \
+				     19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1     (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2     (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C buses and peripherals
+ */
+#define CONFIG_FSL_I2C         /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C        /* I2C with hardware support*/
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED   400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE   0x7f
+#define CONFIG_SYS_I2C_OFFSET  0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/* I2C RTC - M41T81 */
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR     0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/* I2C EEPROM - 24C256 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR            0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        2
+#define CONFIG_SYS_EEPROM_BUS_NUM             1
+
+/*
+ * RapidIO MMU
+ */
+#ifdef CONFIG_SYS_SRIO
+# define CONFIG_SRIO1
+# define CONFIG_SYS_SRIO1_MEM_VIRT  0xc0000000
+# define CONFIG_SYS_SRIO1_MEM_SIZE  0x20000000 /* 512M */
+
+# ifdef CONFIG_PHYS_64BIT
+#  define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
+# else
+#  define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
+# endif
+#endif
+
+/*
+ * Ethernet
+ */
+#ifdef CONFIG_TSEC_ENET
+
+# ifndef CONFIG_NET_MULTI
+#  define CONFIG_NET_MULTI
+# endif
+
+# define CONFIG_MII                /* MII PHY management */
+# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+
+# define CONFIG_TSEC1
+# define CONFIG_TSEC1_NAME       "eTSEC0"
+# define TSEC1_PHY_ADDR          0x10
+# define TSEC1_PHYIDX            0
+# define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC2
+# define CONFIG_TSEC2_NAME       "eTSEC1"
+# define TSEC2_PHY_ADDR          0x11
+# define TSEC2_PHYIDX            0
+# define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC3
+# define CONFIG_TSEC3_NAME       "eTSEC2"
+# define TSEC3_PHY_ADDR          0x12
+# define TSEC3_PHYIDX            0
+# define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC4
+# define CONFIG_TSEC4_NAME       "eTSEC3"
+# define TSEC4_PHY_ADDR          0x13
+# define TSEC4_PHYIDX            0
+# define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+# define CONFIG_ETHPRIME         "eTSEC0"
+# define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_JFFS2
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#define CONFIG_FIT         /* new uImage format support */
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+# define CONFIG_SYS_PROMPT_HUSH_PS2  "> "
+#endif
+
+#define CONFIG_LOADS_ECHO            /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+#define CONFIG_SYS_LONGHELP          /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING       /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE         /* add autocompletion support */
+
+#define CONFIG_SYS_LOAD_ADDR         0x2000000    /* default load address */
+#define CONFIG_SYS_PROMPT            "MPQ-101=> " /* Monitor Command Prompt */
+
+/* Console I/O Buffer Size */
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE 1024
+#else
+# define CONFIG_SYS_CBSIZE 256
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
+# define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
+#endif
+
+/*
+ * Basic Environment Configuration
+ */
+#define CONFIG_BAUDRATE  115200
+#define CONFIG_BOOTDELAY 5            /* -1 disables auto-boot */
+
+/*default location for tftp and bootm*/
+#define CONFIG_LOADADDR  CONFIG_SYS_LOAD_ADDR
+
+#endif /* __CONFIG_H */
-- 
1.7.3.2

[U-Boot] [PATCH v8] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Kumar Gala]

On Jan 23, 2011, at 11:59 PM, Alex Dubov wrote:

> Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
> processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
> memory, real time clock and additional serial EEPROM on i2c bus (enabled).
> USB controller is available, but not presently enabled.
> 
> Additional board information is available at:
> http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx
> 
> Environment is configured to precede the actual u-boot image so that it's
> located at the beginning of flash erase block (made necessary by the recent
> changes to the embedded environment handling). This is achieved by means of
> custom ld script.
> 
> Signed-off-by: Alex Dubov <oakad@yahoo.com>
> ---
> Changes for v8:
>   - Move CONFIG_SYS_LDSCRIPT to board config file
>   - Explicitly refer to env_embedded.o in ld script, as this object is no
>     longer linked into libcommon.o
> Changes for v7:
>   - Add CONFIG_SYS_BOOTM_LEN define
> Changes for v6:
>   - Remove "1"s from feature defines and fix a SRIO ifdef in tlb.c
> Changes for v5:
>   - Use new common SRIO configuration definitions.
>   - Replace initdram() with platform required fixed_sdram().
>   - Don't use get_ram_size() in fixed_sdram() as TLBs are set after it exits
>     by common platform code.
> Changes for v4:
>   - Replace config.mk supplied linker flags with custom linker script.
>   - Fix checkpatch errors.
> Changes for v3:
>   - Use io accessor functions for all mmio accesses.
>   - Add configuration options for RTC and EEPROM on I2C buses.
> Changes for v2:
>   - Remove some stale configuration code from board initialization functions.

applied

- k

[U-Boot] [PATCH v8] mpq101: initial support for Mercury Computer Systems MPQ101 board

[Alex Dubov]

> 
> applied
> 
> - k

Thank you.
I have another board config for your consideration.